acpi_cpu_md.c revision 1.34.2.3
1 /* $NetBSD: acpi_cpu_md.c,v 1.34.2.3 2011/01/10 00:37:36 jym Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Jukka Ruohonen <jruohonen (at) iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.34.2.3 2011/01/10 00:37:36 jym Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/kcore.h> 35 #include <sys/sysctl.h> 36 #include <sys/xcall.h> 37 38 #include <x86/cpu.h> 39 #include <x86/cpufunc.h> 40 #include <x86/cputypes.h> 41 #include <x86/cpuvar.h> 42 #include <x86/cpu_msr.h> 43 #include <x86/machdep.h> 44 45 #include <dev/acpi/acpica.h> 46 #include <dev/acpi/acpi_cpu.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 /* 52 * AMD C1E. 53 */ 54 #define MSR_CMPHALT 0xc0010055 55 56 #define MSR_CMPHALT_SMI __BIT(27) 57 #define MSR_CMPHALT_C1E __BIT(28) 58 #define MSR_CMPHALT_BMSTS __BIT(29) 59 60 /* 61 * AMD families 10h and 11h. 62 */ 63 #define MSR_10H_LIMIT 0xc0010061 64 #define MSR_10H_CONTROL 0xc0010062 65 #define MSR_10H_STATUS 0xc0010063 66 #define MSR_10H_CONFIG 0xc0010064 67 68 /* 69 * AMD family 0Fh. 70 */ 71 #define MSR_0FH_CONTROL 0xc0010041 72 #define MSR_0FH_STATUS 0xc0010042 73 74 #define MSR_0FH_STATUS_CFID __BITS( 0, 5) 75 #define MSR_0FH_STATUS_CVID __BITS(32, 36) 76 #define MSR_0FH_STATUS_PENDING __BITS(31, 31) 77 78 #define MSR_0FH_CONTROL_FID __BITS( 0, 5) 79 #define MSR_0FH_CONTROL_VID __BITS( 8, 12) 80 #define MSR_0FH_CONTROL_CHG __BITS(16, 16) 81 #define MSR_0FH_CONTROL_CNT __BITS(32, 51) 82 83 #define ACPI_0FH_STATUS_FID __BITS( 0, 5) 84 #define ACPI_0FH_STATUS_VID __BITS( 6, 10) 85 86 #define ACPI_0FH_CONTROL_FID __BITS( 0, 5) 87 #define ACPI_0FH_CONTROL_VID __BITS( 6, 10) 88 #define ACPI_0FH_CONTROL_VST __BITS(11, 17) 89 #define ACPI_0FH_CONTROL_MVS __BITS(18, 19) 90 #define ACPI_0FH_CONTROL_PLL __BITS(20, 26) 91 #define ACPI_0FH_CONTROL_RVO __BITS(28, 29) 92 #define ACPI_0FH_CONTROL_IRT __BITS(30, 31) 93 94 #define FID_TO_VCO_FID(fidd) (((fid) < 8) ? (8 + ((fid) << 1)) : (fid)) 95 96 static char native_idle_text[16]; 97 void (*native_idle)(void) = NULL; 98 99 static int acpicpu_md_quirks_piix4(struct pci_attach_args *); 100 static void acpicpu_md_pstate_status(void *, void *); 101 static int acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *, 102 uint32_t *); 103 static int acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *); 104 static int acpicpu_md_pstate_fidvid_read(uint32_t *, uint32_t *); 105 static void acpicpu_md_pstate_fidvid_write(uint32_t, uint32_t, 106 uint32_t, uint32_t); 107 static void acpicpu_md_tstate_status(void *, void *); 108 static int acpicpu_md_pstate_sysctl_init(void); 109 static int acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO); 110 static int acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO); 111 static int acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO); 112 113 extern uint32_t cpus_running; 114 extern struct acpicpu_softc **acpicpu_sc; 115 static bool acpicpu_pstate_status = false; 116 static struct sysctllog *acpicpu_log = NULL; 117 118 uint32_t 119 acpicpu_md_cap(void) 120 { 121 struct cpu_info *ci = curcpu(); 122 uint32_t val = 0; 123 124 if (cpu_vendor != CPUVENDOR_IDT && 125 cpu_vendor != CPUVENDOR_INTEL) 126 return val; 127 128 /* 129 * Basic SMP C-states (required for _CST). 130 */ 131 val |= ACPICPU_PDC_C_C1PT | ACPICPU_PDC_C_C2C3; 132 133 /* 134 * If MONITOR/MWAIT is available, announce 135 * support for native instructions in all C-states. 136 */ 137 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 138 val |= ACPICPU_PDC_C_C1_FFH | ACPICPU_PDC_C_C2C3_FFH; 139 140 /* 141 * Set native P- and T-states, if available. 142 */ 143 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 144 val |= ACPICPU_PDC_P_FFH; 145 146 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 147 val |= ACPICPU_PDC_T_FFH; 148 149 return val; 150 } 151 152 uint32_t 153 acpicpu_md_quirks(void) 154 { 155 struct cpu_info *ci = curcpu(); 156 struct pci_attach_args pa; 157 uint32_t family, val = 0; 158 uint32_t regs[4]; 159 160 if (acpicpu_md_cpus_running() == 1) 161 val |= ACPICPU_FLAG_C_BM; 162 163 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 164 val |= ACPICPU_FLAG_C_FFH; 165 166 val |= ACPICPU_FLAG_C_APIC | ACPICPU_FLAG_C_TSC; 167 168 switch (cpu_vendor) { 169 170 case CPUVENDOR_IDT: 171 172 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 173 val |= ACPICPU_FLAG_P_FFH; 174 175 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 176 val |= ACPICPU_FLAG_T_FFH; 177 178 break; 179 180 case CPUVENDOR_INTEL: 181 182 val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB; 183 184 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 185 val |= ACPICPU_FLAG_P_FFH; 186 187 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 188 val |= ACPICPU_FLAG_T_FFH; 189 190 /* 191 * Check whether MSR_APERF, MSR_MPERF, and Turbo 192 * Boost are available. Also see if we might have 193 * an invariant local APIC timer ("ARAT"). 194 */ 195 if (cpuid_level >= 0x06) { 196 197 x86_cpuid(0x06, regs); 198 199 if ((regs[2] & CPUID_DSPM_HWF) != 0) 200 val |= ACPICPU_FLAG_P_HW; 201 202 if ((regs[0] & CPUID_DSPM_IDA) != 0) 203 val |= ACPICPU_FLAG_P_TURBO; 204 205 if ((regs[0] & CPUID_DSPM_ARAT) != 0) 206 val &= ~ACPICPU_FLAG_C_APIC; 207 } 208 209 /* 210 * Detect whether TSC is invariant. If it is not, 211 * we keep the flag to note that TSC will not run 212 * at constant rate. Depending on the CPU, this may 213 * affect P- and T-state changes, but especially 214 * relevant are C-states; with variant TSC, states 215 * larger than C1 may completely stop the counter. 216 */ 217 x86_cpuid(0x80000000, regs); 218 219 if (regs[0] >= 0x80000007) { 220 221 x86_cpuid(0x80000007, regs); 222 223 if ((regs[3] & __BIT(8)) != 0) 224 val &= ~ACPICPU_FLAG_C_TSC; 225 } 226 227 break; 228 229 case CPUVENDOR_AMD: 230 231 x86_cpuid(0x80000000, regs); 232 233 if (regs[0] < 0x80000007) 234 break; 235 236 x86_cpuid(0x80000007, regs); 237 238 family = CPUID2FAMILY(ci->ci_signature); 239 240 if (family == 0xf) 241 family += CPUID2EXTFAMILY(ci->ci_signature); 242 243 switch (family) { 244 245 case 0x0f: 246 247 if ((regs[3] & CPUID_APM_FID) == 0) 248 break; 249 250 if ((regs[3] & CPUID_APM_VID) == 0) 251 break; 252 253 val |= ACPICPU_FLAG_P_FFH | ACPICPU_FLAG_P_FIDVID; 254 break; 255 256 case 0x10: 257 case 0x11: 258 259 if ((regs[3] & CPUID_APM_TSC) != 0) 260 val &= ~ACPICPU_FLAG_C_TSC; 261 262 if ((regs[3] & CPUID_APM_HWP) != 0) 263 val |= ACPICPU_FLAG_P_FFH; 264 265 if ((regs[3] & CPUID_APM_CPB) != 0) 266 val |= ACPICPU_FLAG_P_TURBO; 267 268 val |= ACPICPU_FLAG_C_C1E; 269 break; 270 } 271 272 break; 273 } 274 275 /* 276 * There are several erratums for PIIX4. 277 */ 278 if (pci_find_device(&pa, acpicpu_md_quirks_piix4) != 0) 279 val |= ACPICPU_FLAG_PIIX4; 280 281 return val; 282 } 283 284 static int 285 acpicpu_md_quirks_piix4(struct pci_attach_args *pa) 286 { 287 288 /* 289 * XXX: The pci_find_device(9) function only 290 * deals with attached devices. Change this 291 * to use something like pci_device_foreach(). 292 */ 293 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 294 return 0; 295 296 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_ISA || 297 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_PMC) 298 return 1; 299 300 return 0; 301 } 302 303 void 304 acpicpu_md_quirks_c1e(void) 305 { 306 const uint64_t c1e = MSR_CMPHALT_SMI | MSR_CMPHALT_C1E; 307 uint64_t val; 308 309 val = rdmsr(MSR_CMPHALT); 310 311 if ((val & c1e) != 0) 312 wrmsr(MSR_CMPHALT, val & ~c1e); 313 } 314 315 uint32_t 316 acpicpu_md_cpus_running(void) 317 { 318 319 return popcount32(cpus_running); 320 } 321 322 int 323 acpicpu_md_idle_start(struct acpicpu_softc *sc) 324 { 325 const size_t size = sizeof(native_idle_text); 326 struct acpicpu_cstate *cs; 327 bool ipi = false; 328 int i; 329 330 x86_cpu_idle_get(&native_idle, native_idle_text, size); 331 332 for (i = 0; i < ACPI_C_STATE_COUNT; i++) { 333 334 cs = &sc->sc_cstate[i]; 335 336 if (cs->cs_method == ACPICPU_C_STATE_HALT) { 337 ipi = true; 338 break; 339 } 340 } 341 342 x86_cpu_idle_set(acpicpu_cstate_idle, "acpi", ipi); 343 344 return 0; 345 } 346 347 int 348 acpicpu_md_idle_stop(void) 349 { 350 uint64_t xc; 351 bool ipi; 352 353 ipi = (native_idle != x86_cpu_idle_halt) ? false : true; 354 x86_cpu_idle_set(native_idle, native_idle_text, ipi); 355 356 /* 357 * Run a cross-call to ensure that all CPUs are 358 * out from the ACPI idle-loop before detachment. 359 */ 360 xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL); 361 xc_wait(xc); 362 363 return 0; 364 } 365 366 /* 367 * Called with interrupts disabled. 368 * Caller should enable interrupts after return. 369 */ 370 void 371 acpicpu_md_idle_enter(int method, int state) 372 { 373 struct cpu_info *ci = curcpu(); 374 375 switch (method) { 376 377 case ACPICPU_C_STATE_FFH: 378 379 x86_enable_intr(); 380 x86_monitor(&ci->ci_want_resched, 0, 0); 381 382 if (__predict_false(ci->ci_want_resched != 0)) 383 return; 384 385 x86_mwait((state - 1) << 4, 0); 386 break; 387 388 case ACPICPU_C_STATE_HALT: 389 390 if (__predict_false(ci->ci_want_resched != 0)) 391 return; 392 393 x86_stihlt(); 394 break; 395 } 396 } 397 398 int 399 acpicpu_md_pstate_start(void) 400 { 401 const uint64_t est = __BIT(16); 402 uint64_t val; 403 404 switch (cpu_vendor) { 405 406 case CPUVENDOR_IDT: 407 case CPUVENDOR_INTEL: 408 409 val = rdmsr(MSR_MISC_ENABLE); 410 411 if ((val & est) == 0) { 412 413 val |= est; 414 415 wrmsr(MSR_MISC_ENABLE, val); 416 val = rdmsr(MSR_MISC_ENABLE); 417 418 if ((val & est) == 0) 419 return ENOTTY; 420 } 421 } 422 423 return acpicpu_md_pstate_sysctl_init(); 424 } 425 426 int 427 acpicpu_md_pstate_stop(void) 428 { 429 430 if (acpicpu_log != NULL) 431 sysctl_teardown(&acpicpu_log); 432 433 return 0; 434 } 435 436 int 437 acpicpu_md_pstate_pss(struct acpicpu_softc *sc) 438 { 439 struct acpicpu_pstate *ps, msr; 440 struct cpu_info *ci = curcpu(); 441 uint32_t family, i = 0; 442 443 (void)memset(&msr, 0, sizeof(struct acpicpu_pstate)); 444 445 switch (cpu_vendor) { 446 447 case CPUVENDOR_IDT: 448 case CPUVENDOR_INTEL: 449 450 /* 451 * If the so-called Turbo Boost is present, 452 * the P0-state is always the "turbo state". 453 * 454 * For discussion, see: 455 * 456 * Intel Corporation: Intel Turbo Boost Technology 457 * in Intel Core(tm) Microarchitectures (Nehalem) 458 * Based Processors. White Paper, November 2008. 459 */ 460 if ((sc->sc_flags & ACPICPU_FLAG_P_TURBO) != 0) 461 sc->sc_pstate[0].ps_flags |= ACPICPU_FLAG_P_TURBO; 462 463 msr.ps_control_addr = MSR_PERF_CTL; 464 msr.ps_control_mask = __BITS(0, 15); 465 466 msr.ps_status_addr = MSR_PERF_STATUS; 467 msr.ps_status_mask = __BITS(0, 15); 468 break; 469 470 case CPUVENDOR_AMD: 471 472 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 473 msr.ps_flags |= ACPICPU_FLAG_P_FIDVID; 474 475 family = CPUID2FAMILY(ci->ci_signature); 476 477 if (family == 0xf) 478 family += CPUID2EXTFAMILY(ci->ci_signature); 479 480 switch (family) { 481 482 case 0x0f: 483 msr.ps_control_addr = MSR_0FH_CONTROL; 484 msr.ps_status_addr = MSR_0FH_STATUS; 485 break; 486 487 case 0x10: 488 case 0x11: 489 msr.ps_control_addr = MSR_10H_CONTROL; 490 msr.ps_control_mask = __BITS(0, 2); 491 492 msr.ps_status_addr = MSR_10H_STATUS; 493 msr.ps_status_mask = __BITS(0, 2); 494 break; 495 496 default: 497 498 if ((sc->sc_flags & ACPICPU_FLAG_P_XPSS) == 0) 499 return EOPNOTSUPP; 500 } 501 502 break; 503 504 default: 505 return ENODEV; 506 } 507 508 /* 509 * Fill the P-state structures with MSR addresses that are 510 * known to be correct. If we do not know the addresses, 511 * leave the values intact. If a vendor uses XPSS, we do 512 * not necessary need to do anything to support new CPUs. 513 */ 514 while (i < sc->sc_pstate_count) { 515 516 ps = &sc->sc_pstate[i]; 517 518 if (msr.ps_flags != 0) 519 ps->ps_flags |= msr.ps_flags; 520 521 if (msr.ps_status_addr != 0) 522 ps->ps_status_addr = msr.ps_status_addr; 523 524 if (msr.ps_status_mask != 0) 525 ps->ps_status_mask = msr.ps_status_mask; 526 527 if (msr.ps_control_addr != 0) 528 ps->ps_control_addr = msr.ps_control_addr; 529 530 if (msr.ps_control_mask != 0) 531 ps->ps_control_mask = msr.ps_control_mask; 532 533 i++; 534 } 535 536 return 0; 537 } 538 539 int 540 acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq) 541 { 542 struct acpicpu_pstate *ps = NULL; 543 uint64_t val; 544 uint32_t i; 545 546 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 547 return acpicpu_md_pstate_fidvid_get(sc, freq); 548 549 for (i = 0; i < sc->sc_pstate_count; i++) { 550 551 ps = &sc->sc_pstate[i]; 552 553 if (__predict_true(ps->ps_freq != 0)) 554 break; 555 } 556 557 if (__predict_false(ps == NULL)) 558 return ENODEV; 559 560 if (__predict_false(ps->ps_status_addr == 0)) 561 return EINVAL; 562 563 val = rdmsr(ps->ps_status_addr); 564 565 if (__predict_true(ps->ps_status_mask != 0)) 566 val = val & ps->ps_status_mask; 567 568 for (i = 0; i < sc->sc_pstate_count; i++) { 569 570 ps = &sc->sc_pstate[i]; 571 572 if (__predict_false(ps->ps_freq == 0)) 573 continue; 574 575 if (val == ps->ps_status) { 576 *freq = ps->ps_freq; 577 return 0; 578 } 579 } 580 581 return EIO; 582 } 583 584 int 585 acpicpu_md_pstate_set(struct acpicpu_pstate *ps) 586 { 587 struct msr_rw_info msr; 588 uint64_t xc; 589 int rv = 0; 590 591 if (__predict_false(ps->ps_control_addr == 0)) 592 return EINVAL; 593 594 if ((ps->ps_flags & ACPICPU_FLAG_P_FIDVID) != 0) 595 return acpicpu_md_pstate_fidvid_set(ps); 596 597 msr.msr_read = false; 598 msr.msr_type = ps->ps_control_addr; 599 msr.msr_value = ps->ps_control; 600 601 if (__predict_true(ps->ps_control_mask != 0)) { 602 msr.msr_mask = ps->ps_control_mask; 603 msr.msr_read = true; 604 } 605 606 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 607 xc_wait(xc); 608 609 /* 610 * Due several problems, we bypass the 611 * relatively expensive status check. 612 */ 613 if (acpicpu_pstate_status != true) { 614 DELAY(ps->ps_latency); 615 return 0; 616 } 617 618 xc = xc_broadcast(0, (xcfunc_t)acpicpu_md_pstate_status, ps, &rv); 619 xc_wait(xc); 620 621 return rv; 622 } 623 624 static void 625 acpicpu_md_pstate_status(void *arg1, void *arg2) 626 { 627 struct acpicpu_pstate *ps = arg1; 628 uint64_t val; 629 int i; 630 631 for (i = val = 0; i < ACPICPU_P_STATE_RETRY; i++) { 632 633 val = rdmsr(ps->ps_status_addr); 634 635 if (__predict_true(ps->ps_status_mask != 0)) 636 val = val & ps->ps_status_mask; 637 638 if (val == ps->ps_status) 639 return; 640 641 DELAY(ps->ps_latency); 642 } 643 644 *(uintptr_t *)arg2 = EAGAIN; 645 } 646 647 static int 648 acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *sc, uint32_t *freq) 649 { 650 struct acpicpu_pstate *ps; 651 uint32_t fid, i, vid; 652 uint32_t cfid, cvid; 653 int rv; 654 655 /* 656 * AMD family 0Fh needs special treatment. 657 * While it wants to use ACPI, it does not 658 * comply with the ACPI specifications. 659 */ 660 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 661 662 if (rv != 0) 663 return rv; 664 665 for (i = 0; i < sc->sc_pstate_count; i++) { 666 667 ps = &sc->sc_pstate[i]; 668 669 if (__predict_false(ps->ps_freq == 0)) 670 continue; 671 672 fid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_FID); 673 vid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_VID); 674 675 if (cfid == fid && cvid == vid) { 676 *freq = ps->ps_freq; 677 return 0; 678 } 679 } 680 681 return EIO; 682 } 683 684 static int 685 acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *ps) 686 { 687 const uint64_t ctrl = ps->ps_control; 688 uint32_t cfid, cvid, fid, i, irt; 689 uint32_t pll, vco_cfid, vco_fid; 690 uint32_t val, vid, vst; 691 int rv; 692 693 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 694 695 if (rv != 0) 696 return rv; 697 698 fid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_FID); 699 vid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VID); 700 irt = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_IRT); 701 vst = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VST); 702 pll = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_PLL); 703 704 vst = vst * 20; 705 pll = pll * 1000 / 5; 706 irt = 10 * __BIT(irt); 707 708 /* 709 * Phase 1. 710 */ 711 while (cvid > vid) { 712 713 val = 1 << __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_MVS); 714 val = (val > cvid) ? 0 : cvid - val; 715 716 acpicpu_md_pstate_fidvid_write(cfid, val, 1, vst); 717 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 718 719 if (rv != 0) 720 return rv; 721 } 722 723 i = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_RVO); 724 725 for (; i > 0 && cvid > 0; --i) { 726 727 acpicpu_md_pstate_fidvid_write(cfid, cvid - 1, 1, vst); 728 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 729 730 if (rv != 0) 731 return rv; 732 } 733 734 /* 735 * Phase 2. 736 */ 737 if (cfid != fid) { 738 739 vco_fid = FID_TO_VCO_FID(fid); 740 vco_cfid = FID_TO_VCO_FID(cfid); 741 742 while (abs(vco_fid - vco_cfid) > 2) { 743 744 if (fid <= cfid) 745 val = cfid - 2; 746 else { 747 val = (cfid > 6) ? cfid + 2 : 748 FID_TO_VCO_FID(cfid) + 2; 749 } 750 751 acpicpu_md_pstate_fidvid_write(val, cvid, pll, irt); 752 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 753 754 if (rv != 0) 755 return rv; 756 757 vco_cfid = FID_TO_VCO_FID(cfid); 758 } 759 760 acpicpu_md_pstate_fidvid_write(fid, cvid, pll, irt); 761 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 762 763 if (rv != 0) 764 return rv; 765 } 766 767 /* 768 * Phase 3. 769 */ 770 if (cvid != vid) { 771 772 acpicpu_md_pstate_fidvid_write(cfid, vid, 1, vst); 773 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 774 775 if (rv != 0) 776 return rv; 777 } 778 779 if (cfid != fid || cvid != vid) 780 return EIO; 781 782 return 0; 783 } 784 785 static int 786 acpicpu_md_pstate_fidvid_read(uint32_t *cfid, uint32_t *cvid) 787 { 788 int i = ACPICPU_P_STATE_RETRY * 100; 789 uint64_t val; 790 791 do { 792 val = rdmsr(MSR_0FH_STATUS); 793 794 } while (__SHIFTOUT(val, MSR_0FH_STATUS_PENDING) != 0 && --i >= 0); 795 796 if (i == 0) 797 return EAGAIN; 798 799 if (cfid != NULL) 800 *cfid = __SHIFTOUT(val, MSR_0FH_STATUS_CFID); 801 802 if (cvid != NULL) 803 *cvid = __SHIFTOUT(val, MSR_0FH_STATUS_CVID); 804 805 return 0; 806 } 807 808 static void 809 acpicpu_md_pstate_fidvid_write(uint32_t fid, 810 uint32_t vid, uint32_t cnt, uint32_t tmo) 811 { 812 struct msr_rw_info msr; 813 uint64_t xc; 814 815 msr.msr_read = false; 816 msr.msr_type = MSR_0FH_CONTROL; 817 msr.msr_value = 0; 818 819 msr.msr_value |= __SHIFTIN(fid, MSR_0FH_CONTROL_FID); 820 msr.msr_value |= __SHIFTIN(vid, MSR_0FH_CONTROL_VID); 821 msr.msr_value |= __SHIFTIN(cnt, MSR_0FH_CONTROL_CNT); 822 msr.msr_value |= __SHIFTIN(0x1, MSR_0FH_CONTROL_CHG); 823 824 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 825 xc_wait(xc); 826 827 DELAY(tmo); 828 } 829 830 int 831 acpicpu_md_tstate_get(struct acpicpu_softc *sc, uint32_t *percent) 832 { 833 struct acpicpu_tstate *ts; 834 uint64_t val; 835 uint32_t i; 836 837 val = rdmsr(MSR_THERM_CONTROL); 838 839 for (i = 0; i < sc->sc_tstate_count; i++) { 840 841 ts = &sc->sc_tstate[i]; 842 843 if (ts->ts_percent == 0) 844 continue; 845 846 if (val == ts->ts_status) { 847 *percent = ts->ts_percent; 848 return 0; 849 } 850 } 851 852 return EIO; 853 } 854 855 int 856 acpicpu_md_tstate_set(struct acpicpu_tstate *ts) 857 { 858 struct msr_rw_info msr; 859 uint64_t xc; 860 int rv = 0; 861 862 msr.msr_read = true; 863 msr.msr_type = MSR_THERM_CONTROL; 864 msr.msr_value = ts->ts_control; 865 msr.msr_mask = __BITS(1, 4); 866 867 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 868 xc_wait(xc); 869 870 if (ts->ts_status == 0) { 871 DELAY(ts->ts_latency); 872 return 0; 873 } 874 875 xc = xc_broadcast(0, (xcfunc_t)acpicpu_md_tstate_status, ts, &rv); 876 xc_wait(xc); 877 878 return rv; 879 } 880 881 static void 882 acpicpu_md_tstate_status(void *arg1, void *arg2) 883 { 884 struct acpicpu_tstate *ts = arg1; 885 uint64_t val; 886 int i; 887 888 for (i = val = 0; i < ACPICPU_T_STATE_RETRY; i++) { 889 890 val = rdmsr(MSR_THERM_CONTROL); 891 892 if (val == ts->ts_status) 893 return; 894 895 DELAY(ts->ts_latency); 896 } 897 898 *(uintptr_t *)arg2 = EAGAIN; 899 } 900 901 /* 902 * A kludge for backwards compatibility. 903 */ 904 static int 905 acpicpu_md_pstate_sysctl_init(void) 906 { 907 const struct sysctlnode *fnode, *mnode, *rnode; 908 const char *str; 909 int rv; 910 911 switch (cpu_vendor) { 912 913 case CPUVENDOR_IDT: 914 case CPUVENDOR_INTEL: 915 str = "est"; 916 break; 917 918 case CPUVENDOR_AMD: 919 str = "powernow"; 920 break; 921 922 default: 923 return ENODEV; 924 } 925 926 927 rv = sysctl_createv(&acpicpu_log, 0, NULL, &rnode, 928 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 929 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 930 931 if (rv != 0) 932 goto fail; 933 934 rv = sysctl_createv(&acpicpu_log, 0, &rnode, &mnode, 935 0, CTLTYPE_NODE, str, NULL, 936 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 937 938 if (rv != 0) 939 goto fail; 940 941 rv = sysctl_createv(&acpicpu_log, 0, &mnode, &fnode, 942 0, CTLTYPE_NODE, "frequency", NULL, 943 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 944 945 if (rv != 0) 946 goto fail; 947 948 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 949 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 950 acpicpu_md_pstate_sysctl_set, 0, NULL, 0, CTL_CREATE, CTL_EOL); 951 952 if (rv != 0) 953 goto fail; 954 955 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 956 CTLFLAG_READONLY, CTLTYPE_INT, "current", NULL, 957 acpicpu_md_pstate_sysctl_get, 0, NULL, 0, CTL_CREATE, CTL_EOL); 958 959 if (rv != 0) 960 goto fail; 961 962 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 963 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 964 acpicpu_md_pstate_sysctl_all, 0, NULL, 0, CTL_CREATE, CTL_EOL); 965 966 if (rv != 0) 967 goto fail; 968 969 return 0; 970 971 fail: 972 if (acpicpu_log != NULL) { 973 sysctl_teardown(&acpicpu_log); 974 acpicpu_log = NULL; 975 } 976 977 return rv; 978 } 979 980 static int 981 acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS) 982 { 983 struct cpu_info *ci = curcpu(); 984 struct acpicpu_softc *sc; 985 struct sysctlnode node; 986 uint32_t freq; 987 int err; 988 989 sc = acpicpu_sc[ci->ci_acpiid]; 990 991 if (sc == NULL) 992 return ENXIO; 993 994 err = acpicpu_pstate_get(sc, &freq); 995 996 if (err != 0) 997 return err; 998 999 node = *rnode; 1000 node.sysctl_data = &freq; 1001 1002 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1003 1004 if (err != 0 || newp == NULL) 1005 return err; 1006 1007 return 0; 1008 } 1009 1010 static int 1011 acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS) 1012 { 1013 struct cpu_info *ci = curcpu(); 1014 struct acpicpu_softc *sc; 1015 struct sysctlnode node; 1016 uint32_t freq; 1017 int err; 1018 1019 sc = acpicpu_sc[ci->ci_acpiid]; 1020 1021 if (sc == NULL) 1022 return ENXIO; 1023 1024 err = acpicpu_pstate_get(sc, &freq); 1025 1026 if (err != 0) 1027 return err; 1028 1029 node = *rnode; 1030 node.sysctl_data = &freq; 1031 1032 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1033 1034 if (err != 0 || newp == NULL) 1035 return err; 1036 1037 err = acpicpu_pstate_set(sc, freq); 1038 1039 if (err != 0) 1040 return err; 1041 1042 return 0; 1043 } 1044 1045 static int 1046 acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS) 1047 { 1048 struct cpu_info *ci = curcpu(); 1049 struct acpicpu_softc *sc; 1050 struct sysctlnode node; 1051 char buf[1024]; 1052 size_t len; 1053 uint32_t i; 1054 int err; 1055 1056 sc = acpicpu_sc[ci->ci_acpiid]; 1057 1058 if (sc == NULL) 1059 return ENXIO; 1060 1061 (void)memset(&buf, 0, sizeof(buf)); 1062 1063 mutex_enter(&sc->sc_mtx); 1064 1065 for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) { 1066 1067 if (sc->sc_pstate[i].ps_freq == 0) 1068 continue; 1069 1070 len += snprintf(buf + len, sizeof(buf) - len, "%u%s", 1071 sc->sc_pstate[i].ps_freq, 1072 i < (sc->sc_pstate_count - 1) ? " " : ""); 1073 } 1074 1075 mutex_exit(&sc->sc_mtx); 1076 1077 node = *rnode; 1078 node.sysctl_data = buf; 1079 1080 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1081 1082 if (err != 0 || newp == NULL) 1083 return err; 1084 1085 return 0; 1086 } 1087 1088
Indexes created Tue Sep 30 20:09:53 GMT 2025