acpi_cpu_md.c revision 1.46
1 /* $NetBSD: acpi_cpu_md.c,v 1.46 2011/02/25 17:23:34 jruoho Exp $ */ 2 3 /*- 4 * Copyright (c) 2010, 2011 Jukka Ruohonen <jruohonen (at) iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.46 2011/02/25 17:23:34 jruoho Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/kcore.h> 35 #include <sys/sysctl.h> 36 #include <sys/xcall.h> 37 38 #include <x86/cpu.h> 39 #include <x86/cpufunc.h> 40 #include <x86/cputypes.h> 41 #include <x86/cpuvar.h> 42 #include <x86/cpu_msr.h> 43 #include <x86/machdep.h> 44 45 #include <dev/acpi/acpica.h> 46 #include <dev/acpi/acpi_cpu.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 #include <machine/acpi_machdep.h> 52 53 /* 54 * AMD C1E. 55 */ 56 #define MSR_CMPHALT 0xc0010055 57 58 #define MSR_CMPHALT_SMI __BIT(27) 59 #define MSR_CMPHALT_C1E __BIT(28) 60 #define MSR_CMPHALT_BMSTS __BIT(29) 61 62 /* 63 * AMD families 10h, 11h, and 14h 64 */ 65 #define MSR_10H_LIMIT 0xc0010061 66 #define MSR_10H_CONTROL 0xc0010062 67 #define MSR_10H_STATUS 0xc0010063 68 #define MSR_10H_CONFIG 0xc0010064 69 70 /* 71 * AMD family 0Fh. 72 */ 73 #define MSR_0FH_CONTROL 0xc0010041 74 #define MSR_0FH_STATUS 0xc0010042 75 76 #define MSR_0FH_STATUS_CFID __BITS( 0, 5) 77 #define MSR_0FH_STATUS_CVID __BITS(32, 36) 78 #define MSR_0FH_STATUS_PENDING __BITS(31, 31) 79 80 #define MSR_0FH_CONTROL_FID __BITS( 0, 5) 81 #define MSR_0FH_CONTROL_VID __BITS( 8, 12) 82 #define MSR_0FH_CONTROL_CHG __BITS(16, 16) 83 #define MSR_0FH_CONTROL_CNT __BITS(32, 51) 84 85 #define ACPI_0FH_STATUS_FID __BITS( 0, 5) 86 #define ACPI_0FH_STATUS_VID __BITS( 6, 10) 87 88 #define ACPI_0FH_CONTROL_FID __BITS( 0, 5) 89 #define ACPI_0FH_CONTROL_VID __BITS( 6, 10) 90 #define ACPI_0FH_CONTROL_VST __BITS(11, 17) 91 #define ACPI_0FH_CONTROL_MVS __BITS(18, 19) 92 #define ACPI_0FH_CONTROL_PLL __BITS(20, 26) 93 #define ACPI_0FH_CONTROL_RVO __BITS(28, 29) 94 #define ACPI_0FH_CONTROL_IRT __BITS(30, 31) 95 96 #define FID_TO_VCO_FID(fidd) (((fid) < 8) ? (8 + ((fid) << 1)) : (fid)) 97 98 static char native_idle_text[16]; 99 void (*native_idle)(void) = NULL; 100 101 static int acpicpu_md_quirk_piix4(struct pci_attach_args *); 102 static void acpicpu_md_pstate_percent_reset(struct acpicpu_softc *); 103 static void acpicpu_md_pstate_percent_status(void *, void *); 104 static void acpicpu_md_pstate_status(void *, void *); 105 static int acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *, 106 uint32_t *); 107 static int acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *); 108 static int acpicpu_md_pstate_fidvid_read(uint32_t *, uint32_t *); 109 static void acpicpu_md_pstate_fidvid_write(uint32_t, uint32_t, 110 uint32_t, uint32_t); 111 static void acpicpu_md_tstate_status(void *, void *); 112 static int acpicpu_md_pstate_sysctl_init(void); 113 static int acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO); 114 static int acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO); 115 static int acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO); 116 117 extern struct acpicpu_softc **acpicpu_sc; 118 static bool acpicpu_pstate_status = false; 119 static struct sysctllog *acpicpu_log = NULL; 120 121 uint32_t 122 acpicpu_md_cap(void) 123 { 124 struct cpu_info *ci = curcpu(); 125 uint32_t regs[4]; 126 uint32_t val = 0; 127 128 if (cpu_vendor != CPUVENDOR_IDT && 129 cpu_vendor != CPUVENDOR_INTEL) 130 return val; 131 132 /* 133 * Basic SMP C-states (required for _CST). 134 */ 135 val |= ACPICPU_PDC_C_C1PT | ACPICPU_PDC_C_C2C3; 136 137 /* 138 * If MONITOR/MWAIT is available, announce 139 * support for native instructions in all C-states. 140 */ 141 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 142 val |= ACPICPU_PDC_C_C1_FFH | ACPICPU_PDC_C_C2C3_FFH; 143 144 /* 145 * Set native P- and T-states, if available. 146 */ 147 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 148 val |= ACPICPU_PDC_P_FFH; 149 150 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 151 val |= ACPICPU_PDC_T_FFH; 152 153 /* 154 * Declare support for APERF and MPERF. 155 */ 156 if (cpuid_level >= 0x06) { 157 158 x86_cpuid(0x00000006, regs); 159 160 if ((regs[2] & CPUID_DSPM_HWF) != 0) 161 val |= ACPICPU_PDC_P_HW; 162 } 163 164 return val; 165 } 166 167 uint32_t 168 acpicpu_md_flags(void) 169 { 170 struct cpu_info *ci = curcpu(); 171 struct pci_attach_args pa; 172 uint32_t family, val = 0; 173 uint32_t regs[4]; 174 175 if (acpi_md_ncpus() == 1) 176 val |= ACPICPU_FLAG_C_BM; 177 178 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 179 val |= ACPICPU_FLAG_C_FFH; 180 181 /* 182 * By default, assume that the local APIC timer 183 * as well as TSC are stalled during C3 sleep. 184 */ 185 val |= ACPICPU_FLAG_C_APIC | ACPICPU_FLAG_C_TSC; 186 187 switch (cpu_vendor) { 188 189 case CPUVENDOR_IDT: 190 191 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 192 val |= ACPICPU_FLAG_P_FFH; 193 194 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 195 val |= ACPICPU_FLAG_T_FFH; 196 197 break; 198 199 case CPUVENDOR_INTEL: 200 201 /* 202 * Bus master control and arbitration should be 203 * available on all supported Intel CPUs (to be 204 * sure, this is double-checked later from the 205 * firmware data). These flags imply that it is 206 * not necessary to flush caches before C3 state. 207 */ 208 val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB; 209 210 /* 211 * Check if we can use "native", MSR-based, 212 * access. If not, we have to resort to I/O. 213 */ 214 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 215 val |= ACPICPU_FLAG_P_FFH; 216 217 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 218 val |= ACPICPU_FLAG_T_FFH; 219 220 /* 221 * Check whether MSR_APERF, MSR_MPERF, and Turbo 222 * Boost are available. Also see if we might have 223 * an invariant local APIC timer ("ARAT"). 224 */ 225 if (cpuid_level >= 0x06) { 226 227 x86_cpuid(0x00000006, regs); 228 229 if ((regs[2] & CPUID_DSPM_HWF) != 0) 230 val |= ACPICPU_FLAG_P_HW; 231 232 if ((regs[0] & CPUID_DSPM_IDA) != 0) 233 val |= ACPICPU_FLAG_P_TURBO; 234 235 if ((regs[0] & CPUID_DSPM_ARAT) != 0) 236 val &= ~ACPICPU_FLAG_C_APIC; 237 } 238 239 /* 240 * Detect whether TSC is invariant. If it is not, 241 * we keep the flag to note that TSC will not run 242 * at constant rate. Depending on the CPU, this may 243 * affect P- and T-state changes, but especially 244 * relevant are C-states; with variant TSC, states 245 * larger than C1 may completely stop the counter. 246 */ 247 x86_cpuid(0x80000000, regs); 248 249 if (regs[0] >= 0x80000007) { 250 251 x86_cpuid(0x80000007, regs); 252 253 if ((regs[3] & __BIT(8)) != 0) 254 val &= ~ACPICPU_FLAG_C_TSC; 255 } 256 257 break; 258 259 case CPUVENDOR_AMD: 260 261 x86_cpuid(0x80000000, regs); 262 263 if (regs[0] < 0x80000007) 264 break; 265 266 x86_cpuid(0x80000007, regs); 267 268 family = CPUID2FAMILY(ci->ci_signature); 269 270 if (family == 0xf) 271 family += CPUID2EXTFAMILY(ci->ci_signature); 272 273 switch (family) { 274 275 case 0x0f: 276 277 /* 278 * Evaluate support for the "FID/VID 279 * algorithm" also used by powernow(4). 280 */ 281 if ((regs[3] & CPUID_APM_FID) == 0) 282 break; 283 284 if ((regs[3] & CPUID_APM_VID) == 0) 285 break; 286 287 val |= ACPICPU_FLAG_P_FFH | ACPICPU_FLAG_P_FIDVID; 288 break; 289 290 case 0x10: 291 case 0x11: 292 val |= ACPICPU_FLAG_C_C1E; 293 /* FALLTHROUGH */ 294 295 case 0x14: /* AMD Fusion */ 296 297 /* 298 * Like with Intel, detect invariant TSC, 299 * MSR-based P-states, and AMD's "turbo" 300 * (Core Performance Boost), respectively. 301 */ 302 if ((regs[3] & CPUID_APM_TSC) != 0) 303 val &= ~ACPICPU_FLAG_C_TSC; 304 305 if ((regs[3] & CPUID_APM_HWP) != 0) 306 val |= ACPICPU_FLAG_P_FFH; 307 308 if ((regs[3] & CPUID_APM_CPB) != 0) 309 val |= ACPICPU_FLAG_P_TURBO; 310 311 /* 312 * Also check for APERF and MPERF, 313 * first available in the family 10h. 314 */ 315 if (cpuid_level >= 0x06) { 316 317 x86_cpuid(0x00000006, regs); 318 319 if ((regs[2] & CPUID_DSPM_HWF) != 0) 320 val |= ACPICPU_FLAG_P_HW; 321 } 322 323 break; 324 } 325 326 break; 327 } 328 329 /* 330 * There are several erratums for PIIX4. 331 */ 332 if (pci_find_device(&pa, acpicpu_md_quirk_piix4) != 0) 333 val |= ACPICPU_FLAG_PIIX4; 334 335 return val; 336 } 337 338 static int 339 acpicpu_md_quirk_piix4(struct pci_attach_args *pa) 340 { 341 342 /* 343 * XXX: The pci_find_device(9) function only 344 * deals with attached devices. Change this 345 * to use something like pci_device_foreach(). 346 */ 347 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 348 return 0; 349 350 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_ISA || 351 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_PMC) 352 return 1; 353 354 return 0; 355 } 356 357 void 358 acpicpu_md_quirk_c1e(void) 359 { 360 const uint64_t c1e = MSR_CMPHALT_SMI | MSR_CMPHALT_C1E; 361 uint64_t val; 362 363 val = rdmsr(MSR_CMPHALT); 364 365 if ((val & c1e) != 0) 366 wrmsr(MSR_CMPHALT, val & ~c1e); 367 } 368 369 int 370 acpicpu_md_cstate_start(struct acpicpu_softc *sc) 371 { 372 const size_t size = sizeof(native_idle_text); 373 struct acpicpu_cstate *cs; 374 bool ipi = false; 375 int i; 376 377 /* 378 * Save the cpu_idle(9) loop used by default. 379 */ 380 x86_cpu_idle_get(&native_idle, native_idle_text, size); 381 382 for (i = 0; i < ACPI_C_STATE_COUNT; i++) { 383 384 cs = &sc->sc_cstate[i]; 385 386 if (cs->cs_method == ACPICPU_C_STATE_HALT) { 387 ipi = true; 388 break; 389 } 390 } 391 392 x86_cpu_idle_set(acpicpu_cstate_idle, "acpi", ipi); 393 394 return 0; 395 } 396 397 int 398 acpicpu_md_cstate_stop(void) 399 { 400 uint64_t xc; 401 bool ipi; 402 403 ipi = (native_idle != x86_cpu_idle_halt) ? false : true; 404 x86_cpu_idle_set(native_idle, native_idle_text, ipi); 405 406 /* 407 * Run a cross-call to ensure that all CPUs are 408 * out from the ACPI idle-loop before detachment. 409 */ 410 xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL); 411 xc_wait(xc); 412 413 return 0; 414 } 415 416 /* 417 * Called with interrupts disabled. 418 * Caller should enable interrupts after return. 419 */ 420 void 421 acpicpu_md_cstate_enter(int method, int state) 422 { 423 struct cpu_info *ci = curcpu(); 424 425 switch (method) { 426 427 case ACPICPU_C_STATE_FFH: 428 429 x86_enable_intr(); 430 x86_monitor(&ci->ci_want_resched, 0, 0); 431 432 if (__predict_false(ci->ci_want_resched != 0)) 433 return; 434 435 x86_mwait((state - 1) << 4, 0); 436 break; 437 438 case ACPICPU_C_STATE_HALT: 439 440 if (__predict_false(ci->ci_want_resched != 0)) 441 return; 442 443 x86_stihlt(); 444 break; 445 } 446 } 447 448 int 449 acpicpu_md_pstate_start(struct acpicpu_softc *sc) 450 { 451 const uint64_t est = __BIT(16); 452 uint64_t val; 453 454 if ((sc->sc_flags & ACPICPU_FLAG_P) == 0) 455 return ENODEV; 456 457 switch (cpu_vendor) { 458 459 case CPUVENDOR_IDT: 460 case CPUVENDOR_INTEL: 461 462 /* 463 * Make sure EST is enabled. 464 */ 465 val = rdmsr(MSR_MISC_ENABLE); 466 467 if ((val & est) == 0) { 468 469 val |= est; 470 471 wrmsr(MSR_MISC_ENABLE, val); 472 val = rdmsr(MSR_MISC_ENABLE); 473 474 if ((val & est) == 0) 475 return ENOTTY; 476 } 477 } 478 479 /* 480 * Reset the APERF and MPERF counters. 481 */ 482 if ((sc->sc_flags & ACPICPU_FLAG_P_HW) != 0) 483 acpicpu_md_pstate_percent_reset(sc); 484 485 return acpicpu_md_pstate_sysctl_init(); 486 } 487 488 int 489 acpicpu_md_pstate_stop(void) 490 { 491 492 if (acpicpu_log != NULL) 493 sysctl_teardown(&acpicpu_log); 494 495 return 0; 496 } 497 498 int 499 acpicpu_md_pstate_pss(struct acpicpu_softc *sc) 500 { 501 struct acpicpu_pstate *ps, msr; 502 struct cpu_info *ci = curcpu(); 503 uint32_t family, i = 0; 504 505 (void)memset(&msr, 0, sizeof(struct acpicpu_pstate)); 506 507 switch (cpu_vendor) { 508 509 case CPUVENDOR_IDT: 510 case CPUVENDOR_INTEL: 511 512 /* 513 * If the so-called Turbo Boost is present, 514 * the P0-state is always the "turbo state". 515 * 516 * For discussion, see: 517 * 518 * Intel Corporation: Intel Turbo Boost Technology 519 * in Intel Core(tm) Microarchitectures (Nehalem) 520 * Based Processors. White Paper, November 2008. 521 */ 522 if ((sc->sc_flags & ACPICPU_FLAG_P_TURBO) != 0) 523 sc->sc_pstate[0].ps_flags |= ACPICPU_FLAG_P_TURBO; 524 525 msr.ps_control_addr = MSR_PERF_CTL; 526 msr.ps_control_mask = __BITS(0, 15); 527 528 msr.ps_status_addr = MSR_PERF_STATUS; 529 msr.ps_status_mask = __BITS(0, 15); 530 break; 531 532 case CPUVENDOR_AMD: 533 534 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 535 msr.ps_flags |= ACPICPU_FLAG_P_FIDVID; 536 537 family = CPUID2FAMILY(ci->ci_signature); 538 539 if (family == 0xf) 540 family += CPUID2EXTFAMILY(ci->ci_signature); 541 542 switch (family) { 543 544 case 0x0f: 545 msr.ps_control_addr = MSR_0FH_CONTROL; 546 msr.ps_status_addr = MSR_0FH_STATUS; 547 break; 548 549 case 0x10: 550 case 0x11: 551 case 0x14: /* AMD Fusion */ 552 msr.ps_control_addr = MSR_10H_CONTROL; 553 msr.ps_control_mask = __BITS(0, 2); 554 555 msr.ps_status_addr = MSR_10H_STATUS; 556 msr.ps_status_mask = __BITS(0, 2); 557 break; 558 559 default: 560 561 if ((sc->sc_flags & ACPICPU_FLAG_P_XPSS) == 0) 562 return EOPNOTSUPP; 563 } 564 565 break; 566 567 default: 568 return ENODEV; 569 } 570 571 /* 572 * Fill the P-state structures with MSR addresses that are 573 * known to be correct. If we do not know the addresses, 574 * leave the values intact. If a vendor uses XPSS, we do 575 * not necessarily need to do anything to support new CPUs. 576 */ 577 while (i < sc->sc_pstate_count) { 578 579 ps = &sc->sc_pstate[i]; 580 581 if (msr.ps_flags != 0) 582 ps->ps_flags |= msr.ps_flags; 583 584 if (msr.ps_status_addr != 0) 585 ps->ps_status_addr = msr.ps_status_addr; 586 587 if (msr.ps_status_mask != 0) 588 ps->ps_status_mask = msr.ps_status_mask; 589 590 if (msr.ps_control_addr != 0) 591 ps->ps_control_addr = msr.ps_control_addr; 592 593 if (msr.ps_control_mask != 0) 594 ps->ps_control_mask = msr.ps_control_mask; 595 596 i++; 597 } 598 599 return 0; 600 } 601 602 /* 603 * Returns the percentage of the actual frequency in 604 * terms of the maximum frequency of the calling CPU 605 * since the last call. A value zero implies an error. 606 */ 607 uint8_t 608 acpicpu_md_pstate_percent(struct acpicpu_softc *sc) 609 { 610 struct cpu_info *ci = sc->sc_ci; 611 uint64_t aperf, mperf; 612 uint64_t xc, rv = 0; 613 614 if (__predict_false((sc->sc_flags & ACPICPU_FLAG_P) == 0)) 615 return 0; 616 617 if (__predict_false((sc->sc_flags & ACPICPU_FLAG_P_HW) == 0)) 618 return 0; 619 620 /* 621 * Read the IA32_APERF and IA32_MPERF counters. The first 622 * increments at the rate of the fixed maximum frequency 623 * configured during the boot, whereas APERF counts at the 624 * rate of the actual frequency. Note that the MSRs must be 625 * read without delay, and that only the ratio between 626 * IA32_APERF and IA32_MPERF is architecturally defined. 627 * 628 * For further details, refer to: 629 * 630 * Intel Corporation: Intel 64 and IA-32 Architectures 631 * Software Developer's Manual. Section 13.2, Volume 3A: 632 * System Programming Guide, Part 1. July, 2008. 633 * 634 * Advanced Micro Devices: BIOS and Kernel Developer's 635 * Guide (BKDG) for AMD Family 10h Processors. Section 636 * 2.4.5, Revision 3.48, April 2010. 637 */ 638 x86_disable_intr(); 639 640 aperf = sc->sc_pstate_aperf; 641 mperf = sc->sc_pstate_mperf; 642 643 xc = xc_unicast(0, acpicpu_md_pstate_percent_status, sc, NULL, ci); 644 xc_wait(xc); 645 646 x86_enable_intr(); 647 648 aperf = sc->sc_pstate_aperf - aperf; 649 mperf = sc->sc_pstate_mperf - mperf; 650 651 if (__predict_true(mperf != 0)) 652 rv = (aperf * 100) / mperf; 653 654 return rv; 655 } 656 657 static void 658 acpicpu_md_pstate_percent_status(void *arg1, void *arg2) 659 { 660 struct acpicpu_softc *sc = arg1; 661 662 sc->sc_pstate_aperf = rdmsr(MSR_APERF); 663 sc->sc_pstate_mperf = rdmsr(MSR_MPERF); 664 } 665 666 static void 667 acpicpu_md_pstate_percent_reset(struct acpicpu_softc *sc) 668 { 669 struct msr_rw_info msr; 670 uint64_t xc; 671 672 KASSERT((sc->sc_flags & ACPICPU_FLAG_P) != 0); 673 KASSERT((sc->sc_flags & ACPICPU_FLAG_P_HW) != 0); 674 675 msr.msr_value = 0; 676 msr.msr_read = false; 677 msr.msr_type = MSR_APERF; 678 679 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 680 xc_wait(xc); 681 682 msr.msr_value = 0; 683 msr.msr_read = false; 684 msr.msr_type = MSR_MPERF; 685 686 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 687 xc_wait(xc); 688 689 sc->sc_pstate_aperf = 0; 690 sc->sc_pstate_mperf = 0; 691 } 692 693 int 694 acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq) 695 { 696 struct acpicpu_pstate *ps = NULL; 697 uint64_t val; 698 uint32_t i; 699 700 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 701 return acpicpu_md_pstate_fidvid_get(sc, freq); 702 703 for (i = 0; i < sc->sc_pstate_count; i++) { 704 705 ps = &sc->sc_pstate[i]; 706 707 if (__predict_true(ps->ps_freq != 0)) 708 break; 709 } 710 711 if (__predict_false(ps == NULL)) 712 return ENODEV; 713 714 if (__predict_false(ps->ps_status_addr == 0)) 715 return EINVAL; 716 717 val = rdmsr(ps->ps_status_addr); 718 719 if (__predict_true(ps->ps_status_mask != 0)) 720 val = val & ps->ps_status_mask; 721 722 for (i = 0; i < sc->sc_pstate_count; i++) { 723 724 ps = &sc->sc_pstate[i]; 725 726 if (__predict_false(ps->ps_freq == 0)) 727 continue; 728 729 if (val == ps->ps_status) { 730 *freq = ps->ps_freq; 731 return 0; 732 } 733 } 734 735 return EIO; 736 } 737 738 int 739 acpicpu_md_pstate_set(struct acpicpu_pstate *ps) 740 { 741 struct msr_rw_info msr; 742 uint64_t xc; 743 int rv = 0; 744 745 if (__predict_false(ps->ps_control_addr == 0)) 746 return EINVAL; 747 748 if ((ps->ps_flags & ACPICPU_FLAG_P_FIDVID) != 0) 749 return acpicpu_md_pstate_fidvid_set(ps); 750 751 msr.msr_read = false; 752 msr.msr_type = ps->ps_control_addr; 753 msr.msr_value = ps->ps_control; 754 755 if (__predict_true(ps->ps_control_mask != 0)) { 756 msr.msr_mask = ps->ps_control_mask; 757 msr.msr_read = true; 758 } 759 760 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 761 xc_wait(xc); 762 763 /* 764 * Due several problems, we bypass the 765 * relatively expensive status check. 766 */ 767 if (acpicpu_pstate_status != true) { 768 DELAY(ps->ps_latency); 769 return 0; 770 } 771 772 xc = xc_broadcast(0, (xcfunc_t)acpicpu_md_pstate_status, ps, &rv); 773 xc_wait(xc); 774 775 return rv; 776 } 777 778 static void 779 acpicpu_md_pstate_status(void *arg1, void *arg2) 780 { 781 struct acpicpu_pstate *ps = arg1; 782 uint64_t val; 783 int i; 784 785 for (i = val = 0; i < ACPICPU_P_STATE_RETRY; i++) { 786 787 val = rdmsr(ps->ps_status_addr); 788 789 if (__predict_true(ps->ps_status_mask != 0)) 790 val = val & ps->ps_status_mask; 791 792 if (val == ps->ps_status) 793 return; 794 795 DELAY(ps->ps_latency); 796 } 797 798 *(uintptr_t *)arg2 = EAGAIN; 799 } 800 801 static int 802 acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *sc, uint32_t *freq) 803 { 804 struct acpicpu_pstate *ps; 805 uint32_t fid, i, vid; 806 uint32_t cfid, cvid; 807 int rv; 808 809 /* 810 * AMD family 0Fh needs special treatment. 811 * While it wants to use ACPI, it does not 812 * comply with the ACPI specifications. 813 */ 814 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 815 816 if (rv != 0) 817 return rv; 818 819 for (i = 0; i < sc->sc_pstate_count; i++) { 820 821 ps = &sc->sc_pstate[i]; 822 823 if (__predict_false(ps->ps_freq == 0)) 824 continue; 825 826 fid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_FID); 827 vid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_VID); 828 829 if (cfid == fid && cvid == vid) { 830 *freq = ps->ps_freq; 831 return 0; 832 } 833 } 834 835 return EIO; 836 } 837 838 static int 839 acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *ps) 840 { 841 const uint64_t ctrl = ps->ps_control; 842 uint32_t cfid, cvid, fid, i, irt; 843 uint32_t pll, vco_cfid, vco_fid; 844 uint32_t val, vid, vst; 845 int rv; 846 847 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 848 849 if (rv != 0) 850 return rv; 851 852 fid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_FID); 853 vid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VID); 854 irt = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_IRT); 855 vst = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VST); 856 pll = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_PLL); 857 858 vst = vst * 20; 859 pll = pll * 1000 / 5; 860 irt = 10 * __BIT(irt); 861 862 /* 863 * Phase 1. 864 */ 865 while (cvid > vid) { 866 867 val = 1 << __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_MVS); 868 val = (val > cvid) ? 0 : cvid - val; 869 870 acpicpu_md_pstate_fidvid_write(cfid, val, 1, vst); 871 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 872 873 if (rv != 0) 874 return rv; 875 } 876 877 i = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_RVO); 878 879 for (; i > 0 && cvid > 0; --i) { 880 881 acpicpu_md_pstate_fidvid_write(cfid, cvid - 1, 1, vst); 882 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 883 884 if (rv != 0) 885 return rv; 886 } 887 888 /* 889 * Phase 2. 890 */ 891 if (cfid != fid) { 892 893 vco_fid = FID_TO_VCO_FID(fid); 894 vco_cfid = FID_TO_VCO_FID(cfid); 895 896 while (abs(vco_fid - vco_cfid) > 2) { 897 898 if (fid <= cfid) 899 val = cfid - 2; 900 else { 901 val = (cfid > 6) ? cfid + 2 : 902 FID_TO_VCO_FID(cfid) + 2; 903 } 904 905 acpicpu_md_pstate_fidvid_write(val, cvid, pll, irt); 906 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 907 908 if (rv != 0) 909 return rv; 910 911 vco_cfid = FID_TO_VCO_FID(cfid); 912 } 913 914 acpicpu_md_pstate_fidvid_write(fid, cvid, pll, irt); 915 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 916 917 if (rv != 0) 918 return rv; 919 } 920 921 /* 922 * Phase 3. 923 */ 924 if (cvid != vid) { 925 926 acpicpu_md_pstate_fidvid_write(cfid, vid, 1, vst); 927 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 928 929 if (rv != 0) 930 return rv; 931 } 932 933 if (cfid != fid || cvid != vid) 934 return EIO; 935 936 return 0; 937 } 938 939 static int 940 acpicpu_md_pstate_fidvid_read(uint32_t *cfid, uint32_t *cvid) 941 { 942 int i = ACPICPU_P_STATE_RETRY * 100; 943 uint64_t val; 944 945 do { 946 val = rdmsr(MSR_0FH_STATUS); 947 948 } while (__SHIFTOUT(val, MSR_0FH_STATUS_PENDING) != 0 && --i >= 0); 949 950 if (i == 0) 951 return EAGAIN; 952 953 if (cfid != NULL) 954 *cfid = __SHIFTOUT(val, MSR_0FH_STATUS_CFID); 955 956 if (cvid != NULL) 957 *cvid = __SHIFTOUT(val, MSR_0FH_STATUS_CVID); 958 959 return 0; 960 } 961 962 static void 963 acpicpu_md_pstate_fidvid_write(uint32_t fid, 964 uint32_t vid, uint32_t cnt, uint32_t tmo) 965 { 966 struct msr_rw_info msr; 967 uint64_t xc; 968 969 msr.msr_read = false; 970 msr.msr_type = MSR_0FH_CONTROL; 971 msr.msr_value = 0; 972 973 msr.msr_value |= __SHIFTIN(fid, MSR_0FH_CONTROL_FID); 974 msr.msr_value |= __SHIFTIN(vid, MSR_0FH_CONTROL_VID); 975 msr.msr_value |= __SHIFTIN(cnt, MSR_0FH_CONTROL_CNT); 976 msr.msr_value |= __SHIFTIN(0x1, MSR_0FH_CONTROL_CHG); 977 978 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 979 xc_wait(xc); 980 981 DELAY(tmo); 982 } 983 984 int 985 acpicpu_md_tstate_get(struct acpicpu_softc *sc, uint32_t *percent) 986 { 987 struct acpicpu_tstate *ts; 988 uint64_t val; 989 uint32_t i; 990 991 val = rdmsr(MSR_THERM_CONTROL); 992 993 for (i = 0; i < sc->sc_tstate_count; i++) { 994 995 ts = &sc->sc_tstate[i]; 996 997 if (ts->ts_percent == 0) 998 continue; 999 1000 if (val == ts->ts_status) { 1001 *percent = ts->ts_percent; 1002 return 0; 1003 } 1004 } 1005 1006 return EIO; 1007 } 1008 1009 int 1010 acpicpu_md_tstate_set(struct acpicpu_tstate *ts) 1011 { 1012 struct msr_rw_info msr; 1013 uint64_t xc; 1014 int rv = 0; 1015 1016 msr.msr_read = true; 1017 msr.msr_type = MSR_THERM_CONTROL; 1018 msr.msr_value = ts->ts_control; 1019 msr.msr_mask = __BITS(1, 4); 1020 1021 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 1022 xc_wait(xc); 1023 1024 if (ts->ts_status == 0) { 1025 DELAY(ts->ts_latency); 1026 return 0; 1027 } 1028 1029 xc = xc_broadcast(0, (xcfunc_t)acpicpu_md_tstate_status, ts, &rv); 1030 xc_wait(xc); 1031 1032 return rv; 1033 } 1034 1035 static void 1036 acpicpu_md_tstate_status(void *arg1, void *arg2) 1037 { 1038 struct acpicpu_tstate *ts = arg1; 1039 uint64_t val; 1040 int i; 1041 1042 for (i = val = 0; i < ACPICPU_T_STATE_RETRY; i++) { 1043 1044 val = rdmsr(MSR_THERM_CONTROL); 1045 1046 if (val == ts->ts_status) 1047 return; 1048 1049 DELAY(ts->ts_latency); 1050 } 1051 1052 *(uintptr_t *)arg2 = EAGAIN; 1053 } 1054 1055 /* 1056 * A kludge for backwards compatibility. 1057 */ 1058 static int 1059 acpicpu_md_pstate_sysctl_init(void) 1060 { 1061 const struct sysctlnode *fnode, *mnode, *rnode; 1062 const char *str; 1063 int rv; 1064 1065 switch (cpu_vendor) { 1066 1067 case CPUVENDOR_IDT: 1068 case CPUVENDOR_INTEL: 1069 str = "est"; 1070 break; 1071 1072 case CPUVENDOR_AMD: 1073 str = "powernow"; 1074 break; 1075 1076 default: 1077 return ENODEV; 1078 } 1079 1080 1081 rv = sysctl_createv(&acpicpu_log, 0, NULL, &rnode, 1082 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 1083 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 1084 1085 if (rv != 0) 1086 goto fail; 1087 1088 rv = sysctl_createv(&acpicpu_log, 0, &rnode, &mnode, 1089 0, CTLTYPE_NODE, str, NULL, 1090 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1091 1092 if (rv != 0) 1093 goto fail; 1094 1095 rv = sysctl_createv(&acpicpu_log, 0, &mnode, &fnode, 1096 0, CTLTYPE_NODE, "frequency", NULL, 1097 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1098 1099 if (rv != 0) 1100 goto fail; 1101 1102 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1103 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 1104 acpicpu_md_pstate_sysctl_set, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1105 1106 if (rv != 0) 1107 goto fail; 1108 1109 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1110 CTLFLAG_READONLY, CTLTYPE_INT, "current", NULL, 1111 acpicpu_md_pstate_sysctl_get, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1112 1113 if (rv != 0) 1114 goto fail; 1115 1116 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1117 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 1118 acpicpu_md_pstate_sysctl_all, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1119 1120 if (rv != 0) 1121 goto fail; 1122 1123 return 0; 1124 1125 fail: 1126 if (acpicpu_log != NULL) { 1127 sysctl_teardown(&acpicpu_log); 1128 acpicpu_log = NULL; 1129 } 1130 1131 return rv; 1132 } 1133 1134 static int 1135 acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS) 1136 { 1137 struct cpu_info *ci = curcpu(); 1138 struct acpicpu_softc *sc; 1139 struct sysctlnode node; 1140 uint32_t freq; 1141 int err; 1142 1143 sc = acpicpu_sc[ci->ci_acpiid]; 1144 1145 if (sc == NULL) 1146 return ENXIO; 1147 1148 err = acpicpu_pstate_get(sc, &freq); 1149 1150 if (err != 0) 1151 return err; 1152 1153 node = *rnode; 1154 node.sysctl_data = &freq; 1155 1156 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1157 1158 if (err != 0 || newp == NULL) 1159 return err; 1160 1161 return 0; 1162 } 1163 1164 static int 1165 acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS) 1166 { 1167 struct cpu_info *ci = curcpu(); 1168 struct acpicpu_softc *sc; 1169 struct sysctlnode node; 1170 uint32_t freq; 1171 int err; 1172 1173 sc = acpicpu_sc[ci->ci_acpiid]; 1174 1175 if (sc == NULL) 1176 return ENXIO; 1177 1178 err = acpicpu_pstate_get(sc, &freq); 1179 1180 if (err != 0) 1181 return err; 1182 1183 node = *rnode; 1184 node.sysctl_data = &freq; 1185 1186 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1187 1188 if (err != 0 || newp == NULL) 1189 return err; 1190 1191 err = acpicpu_pstate_set(sc, freq); 1192 1193 if (err != 0) 1194 return err; 1195 1196 return 0; 1197 } 1198 1199 static int 1200 acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS) 1201 { 1202 struct cpu_info *ci = curcpu(); 1203 struct acpicpu_softc *sc; 1204 struct sysctlnode node; 1205 char buf[1024]; 1206 size_t len; 1207 uint32_t i; 1208 int err; 1209 1210 sc = acpicpu_sc[ci->ci_acpiid]; 1211 1212 if (sc == NULL) 1213 return ENXIO; 1214 1215 (void)memset(&buf, 0, sizeof(buf)); 1216 1217 mutex_enter(&sc->sc_mtx); 1218 1219 for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) { 1220 1221 if (sc->sc_pstate[i].ps_freq == 0) 1222 continue; 1223 1224 len += snprintf(buf + len, sizeof(buf) - len, "%u%s", 1225 sc->sc_pstate[i].ps_freq, 1226 i < (sc->sc_pstate_count - 1) ? " " : ""); 1227 } 1228 1229 mutex_exit(&sc->sc_mtx); 1230 1231 node = *rnode; 1232 node.sysctl_data = buf; 1233 1234 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1235 1236 if (err != 0 || newp == NULL) 1237 return err; 1238 1239 return 0; 1240 } 1241 1242
Indexes created Tue Sep 30 20:09:53 GMT 2025