acpi_cpu_md.c revision 1.47
1 /* $NetBSD: acpi_cpu_md.c,v 1.47 2011/02/27 17:27:28 jruoho Exp $ */ 2 3 /*- 4 * Copyright (c) 2010, 2011 Jukka Ruohonen <jruohonen (at) iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.47 2011/02/27 17:27:28 jruoho Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/kcore.h> 35 #include <sys/sysctl.h> 36 #include <sys/xcall.h> 37 38 #include <x86/cpu.h> 39 #include <x86/cpufunc.h> 40 #include <x86/cputypes.h> 41 #include <x86/cpuvar.h> 42 #include <x86/cpu_msr.h> 43 #include <x86/machdep.h> 44 45 #include <dev/acpi/acpica.h> 46 #include <dev/acpi/acpi_cpu.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 #include <machine/acpi_machdep.h> 52 53 /* 54 * AMD C1E. 55 */ 56 #define MSR_CMPHALT 0xc0010055 57 58 #define MSR_CMPHALT_SMI __BIT(27) 59 #define MSR_CMPHALT_C1E __BIT(28) 60 #define MSR_CMPHALT_BMSTS __BIT(29) 61 62 /* 63 * AMD families 10h, 11h, and 14h 64 */ 65 #define MSR_10H_LIMIT 0xc0010061 66 #define MSR_10H_CONTROL 0xc0010062 67 #define MSR_10H_STATUS 0xc0010063 68 #define MSR_10H_CONFIG 0xc0010064 69 70 /* 71 * AMD family 0Fh. 72 */ 73 #define MSR_0FH_CONTROL 0xc0010041 74 #define MSR_0FH_STATUS 0xc0010042 75 76 #define MSR_0FH_STATUS_CFID __BITS( 0, 5) 77 #define MSR_0FH_STATUS_CVID __BITS(32, 36) 78 #define MSR_0FH_STATUS_PENDING __BITS(31, 31) 79 80 #define MSR_0FH_CONTROL_FID __BITS( 0, 5) 81 #define MSR_0FH_CONTROL_VID __BITS( 8, 12) 82 #define MSR_0FH_CONTROL_CHG __BITS(16, 16) 83 #define MSR_0FH_CONTROL_CNT __BITS(32, 51) 84 85 #define ACPI_0FH_STATUS_FID __BITS( 0, 5) 86 #define ACPI_0FH_STATUS_VID __BITS( 6, 10) 87 88 #define ACPI_0FH_CONTROL_FID __BITS( 0, 5) 89 #define ACPI_0FH_CONTROL_VID __BITS( 6, 10) 90 #define ACPI_0FH_CONTROL_VST __BITS(11, 17) 91 #define ACPI_0FH_CONTROL_MVS __BITS(18, 19) 92 #define ACPI_0FH_CONTROL_PLL __BITS(20, 26) 93 #define ACPI_0FH_CONTROL_RVO __BITS(28, 29) 94 #define ACPI_0FH_CONTROL_IRT __BITS(30, 31) 95 96 #define FID_TO_VCO_FID(fidd) (((fid) < 8) ? (8 + ((fid) << 1)) : (fid)) 97 98 static char native_idle_text[16]; 99 void (*native_idle)(void) = NULL; 100 101 static int acpicpu_md_quirk_piix4(struct pci_attach_args *); 102 static void acpicpu_md_pstate_percent_reset(struct acpicpu_softc *); 103 static void acpicpu_md_pstate_percent_status(void *, void *); 104 static void acpicpu_md_pstate_status(void *, void *); 105 static int acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *, 106 uint32_t *); 107 static int acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *); 108 static int acpicpu_md_pstate_fidvid_read(uint32_t *, uint32_t *); 109 static void acpicpu_md_pstate_fidvid_write(uint32_t, uint32_t, 110 uint32_t, uint32_t); 111 static void acpicpu_md_tstate_status(void *, void *); 112 static int acpicpu_md_pstate_sysctl_init(void); 113 static int acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO); 114 static int acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO); 115 static int acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO); 116 117 extern struct acpicpu_softc **acpicpu_sc; 118 static bool acpicpu_pstate_status = false; 119 static struct sysctllog *acpicpu_log = NULL; 120 121 uint32_t 122 acpicpu_md_cap(void) 123 { 124 struct cpu_info *ci = curcpu(); 125 uint32_t regs[4]; 126 uint32_t val = 0; 127 128 if (cpu_vendor != CPUVENDOR_IDT && 129 cpu_vendor != CPUVENDOR_INTEL) 130 return val; 131 132 /* 133 * Basic SMP C-states (required for e.g. _CST). 134 */ 135 val |= ACPICPU_PDC_C_C1PT | ACPICPU_PDC_C_C2C3; 136 137 /* 138 * Claim to support dependency coordination. 139 */ 140 val |= ACPICPU_PDC_P_SW | ACPICPU_PDC_C_SW | ACPICPU_PDC_T_SW; 141 142 /* 143 * If MONITOR/MWAIT is available, announce 144 * support for native instructions in all C-states. 145 */ 146 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 147 val |= ACPICPU_PDC_C_C1_FFH | ACPICPU_PDC_C_C2C3_FFH; 148 149 /* 150 * Set native P- and T-states, if available. 151 */ 152 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 153 val |= ACPICPU_PDC_P_FFH; 154 155 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 156 val |= ACPICPU_PDC_T_FFH; 157 158 /* 159 * Declare support for APERF and MPERF. 160 */ 161 if (cpuid_level >= 0x06) { 162 163 x86_cpuid(0x00000006, regs); 164 165 if ((regs[2] & CPUID_DSPM_HWF) != 0) 166 val |= ACPICPU_PDC_P_HW; 167 } 168 169 return val; 170 } 171 172 uint32_t 173 acpicpu_md_flags(void) 174 { 175 struct cpu_info *ci = curcpu(); 176 struct pci_attach_args pa; 177 uint32_t family, val = 0; 178 uint32_t regs[4]; 179 180 if (acpi_md_ncpus() == 1) 181 val |= ACPICPU_FLAG_C_BM; 182 183 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 184 val |= ACPICPU_FLAG_C_FFH; 185 186 /* 187 * By default, assume that the local APIC timer 188 * as well as TSC are stalled during C3 sleep. 189 */ 190 val |= ACPICPU_FLAG_C_APIC | ACPICPU_FLAG_C_TSC; 191 192 switch (cpu_vendor) { 193 194 case CPUVENDOR_IDT: 195 196 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 197 val |= ACPICPU_FLAG_P_FFH; 198 199 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 200 val |= ACPICPU_FLAG_T_FFH; 201 202 break; 203 204 case CPUVENDOR_INTEL: 205 206 /* 207 * Bus master control and arbitration should be 208 * available on all supported Intel CPUs (to be 209 * sure, this is double-checked later from the 210 * firmware data). These flags imply that it is 211 * not necessary to flush caches before C3 state. 212 */ 213 val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB; 214 215 /* 216 * Check if we can use "native", MSR-based, 217 * access. If not, we have to resort to I/O. 218 */ 219 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 220 val |= ACPICPU_FLAG_P_FFH; 221 222 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 223 val |= ACPICPU_FLAG_T_FFH; 224 225 /* 226 * Check whether MSR_APERF, MSR_MPERF, and Turbo 227 * Boost are available. Also see if we might have 228 * an invariant local APIC timer ("ARAT"). 229 */ 230 if (cpuid_level >= 0x06) { 231 232 x86_cpuid(0x00000006, regs); 233 234 if ((regs[2] & CPUID_DSPM_HWF) != 0) 235 val |= ACPICPU_FLAG_P_HW; 236 237 if ((regs[0] & CPUID_DSPM_IDA) != 0) 238 val |= ACPICPU_FLAG_P_TURBO; 239 240 if ((regs[0] & CPUID_DSPM_ARAT) != 0) 241 val &= ~ACPICPU_FLAG_C_APIC; 242 } 243 244 /* 245 * Detect whether TSC is invariant. If it is not, 246 * we keep the flag to note that TSC will not run 247 * at constant rate. Depending on the CPU, this may 248 * affect P- and T-state changes, but especially 249 * relevant are C-states; with variant TSC, states 250 * larger than C1 may completely stop the counter. 251 */ 252 x86_cpuid(0x80000000, regs); 253 254 if (regs[0] >= 0x80000007) { 255 256 x86_cpuid(0x80000007, regs); 257 258 if ((regs[3] & __BIT(8)) != 0) 259 val &= ~ACPICPU_FLAG_C_TSC; 260 } 261 262 break; 263 264 case CPUVENDOR_AMD: 265 266 x86_cpuid(0x80000000, regs); 267 268 if (regs[0] < 0x80000007) 269 break; 270 271 x86_cpuid(0x80000007, regs); 272 273 family = CPUID2FAMILY(ci->ci_signature); 274 275 if (family == 0xf) 276 family += CPUID2EXTFAMILY(ci->ci_signature); 277 278 switch (family) { 279 280 case 0x0f: 281 282 /* 283 * Evaluate support for the "FID/VID 284 * algorithm" also used by powernow(4). 285 */ 286 if ((regs[3] & CPUID_APM_FID) == 0) 287 break; 288 289 if ((regs[3] & CPUID_APM_VID) == 0) 290 break; 291 292 val |= ACPICPU_FLAG_P_FFH | ACPICPU_FLAG_P_FIDVID; 293 break; 294 295 case 0x10: 296 case 0x11: 297 val |= ACPICPU_FLAG_C_C1E; 298 /* FALLTHROUGH */ 299 300 case 0x14: /* AMD Fusion */ 301 302 /* 303 * Like with Intel, detect invariant TSC, 304 * MSR-based P-states, and AMD's "turbo" 305 * (Core Performance Boost), respectively. 306 */ 307 if ((regs[3] & CPUID_APM_TSC) != 0) 308 val &= ~ACPICPU_FLAG_C_TSC; 309 310 if ((regs[3] & CPUID_APM_HWP) != 0) 311 val |= ACPICPU_FLAG_P_FFH; 312 313 if ((regs[3] & CPUID_APM_CPB) != 0) 314 val |= ACPICPU_FLAG_P_TURBO; 315 316 /* 317 * Also check for APERF and MPERF, 318 * first available in the family 10h. 319 */ 320 if (cpuid_level >= 0x06) { 321 322 x86_cpuid(0x00000006, regs); 323 324 if ((regs[2] & CPUID_DSPM_HWF) != 0) 325 val |= ACPICPU_FLAG_P_HW; 326 } 327 328 break; 329 } 330 331 break; 332 } 333 334 /* 335 * There are several erratums for PIIX4. 336 */ 337 if (pci_find_device(&pa, acpicpu_md_quirk_piix4) != 0) 338 val |= ACPICPU_FLAG_PIIX4; 339 340 return val; 341 } 342 343 static int 344 acpicpu_md_quirk_piix4(struct pci_attach_args *pa) 345 { 346 347 /* 348 * XXX: The pci_find_device(9) function only 349 * deals with attached devices. Change this 350 * to use something like pci_device_foreach(). 351 */ 352 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 353 return 0; 354 355 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_ISA || 356 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_PMC) 357 return 1; 358 359 return 0; 360 } 361 362 void 363 acpicpu_md_quirk_c1e(void) 364 { 365 const uint64_t c1e = MSR_CMPHALT_SMI | MSR_CMPHALT_C1E; 366 uint64_t val; 367 368 val = rdmsr(MSR_CMPHALT); 369 370 if ((val & c1e) != 0) 371 wrmsr(MSR_CMPHALT, val & ~c1e); 372 } 373 374 int 375 acpicpu_md_cstate_start(struct acpicpu_softc *sc) 376 { 377 const size_t size = sizeof(native_idle_text); 378 struct acpicpu_cstate *cs; 379 bool ipi = false; 380 int i; 381 382 /* 383 * Save the cpu_idle(9) loop used by default. 384 */ 385 x86_cpu_idle_get(&native_idle, native_idle_text, size); 386 387 for (i = 0; i < ACPI_C_STATE_COUNT; i++) { 388 389 cs = &sc->sc_cstate[i]; 390 391 if (cs->cs_method == ACPICPU_C_STATE_HALT) { 392 ipi = true; 393 break; 394 } 395 } 396 397 x86_cpu_idle_set(acpicpu_cstate_idle, "acpi", ipi); 398 399 return 0; 400 } 401 402 int 403 acpicpu_md_cstate_stop(void) 404 { 405 uint64_t xc; 406 bool ipi; 407 408 ipi = (native_idle != x86_cpu_idle_halt) ? false : true; 409 x86_cpu_idle_set(native_idle, native_idle_text, ipi); 410 411 /* 412 * Run a cross-call to ensure that all CPUs are 413 * out from the ACPI idle-loop before detachment. 414 */ 415 xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL); 416 xc_wait(xc); 417 418 return 0; 419 } 420 421 /* 422 * Called with interrupts disabled. 423 * Caller should enable interrupts after return. 424 */ 425 void 426 acpicpu_md_cstate_enter(int method, int state) 427 { 428 struct cpu_info *ci = curcpu(); 429 430 switch (method) { 431 432 case ACPICPU_C_STATE_FFH: 433 434 x86_enable_intr(); 435 x86_monitor(&ci->ci_want_resched, 0, 0); 436 437 if (__predict_false(ci->ci_want_resched != 0)) 438 return; 439 440 x86_mwait((state - 1) << 4, 0); 441 break; 442 443 case ACPICPU_C_STATE_HALT: 444 445 if (__predict_false(ci->ci_want_resched != 0)) 446 return; 447 448 x86_stihlt(); 449 break; 450 } 451 } 452 453 int 454 acpicpu_md_pstate_start(struct acpicpu_softc *sc) 455 { 456 const uint64_t est = __BIT(16); 457 uint64_t val; 458 459 if ((sc->sc_flags & ACPICPU_FLAG_P) == 0) 460 return ENODEV; 461 462 switch (cpu_vendor) { 463 464 case CPUVENDOR_IDT: 465 case CPUVENDOR_INTEL: 466 467 /* 468 * Make sure EST is enabled. 469 */ 470 val = rdmsr(MSR_MISC_ENABLE); 471 472 if ((val & est) == 0) { 473 474 val |= est; 475 476 wrmsr(MSR_MISC_ENABLE, val); 477 val = rdmsr(MSR_MISC_ENABLE); 478 479 if ((val & est) == 0) 480 return ENOTTY; 481 } 482 } 483 484 /* 485 * Reset the APERF and MPERF counters. 486 */ 487 if ((sc->sc_flags & ACPICPU_FLAG_P_HW) != 0) 488 acpicpu_md_pstate_percent_reset(sc); 489 490 return acpicpu_md_pstate_sysctl_init(); 491 } 492 493 int 494 acpicpu_md_pstate_stop(void) 495 { 496 497 if (acpicpu_log != NULL) 498 sysctl_teardown(&acpicpu_log); 499 500 return 0; 501 } 502 503 int 504 acpicpu_md_pstate_pss(struct acpicpu_softc *sc) 505 { 506 struct acpicpu_pstate *ps, msr; 507 struct cpu_info *ci = curcpu(); 508 uint32_t family, i = 0; 509 510 (void)memset(&msr, 0, sizeof(struct acpicpu_pstate)); 511 512 switch (cpu_vendor) { 513 514 case CPUVENDOR_IDT: 515 case CPUVENDOR_INTEL: 516 517 /* 518 * If the so-called Turbo Boost is present, 519 * the P0-state is always the "turbo state". 520 * 521 * For discussion, see: 522 * 523 * Intel Corporation: Intel Turbo Boost Technology 524 * in Intel Core(tm) Microarchitectures (Nehalem) 525 * Based Processors. White Paper, November 2008. 526 */ 527 if ((sc->sc_flags & ACPICPU_FLAG_P_TURBO) != 0) 528 sc->sc_pstate[0].ps_flags |= ACPICPU_FLAG_P_TURBO; 529 530 msr.ps_control_addr = MSR_PERF_CTL; 531 msr.ps_control_mask = __BITS(0, 15); 532 533 msr.ps_status_addr = MSR_PERF_STATUS; 534 msr.ps_status_mask = __BITS(0, 15); 535 break; 536 537 case CPUVENDOR_AMD: 538 539 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 540 msr.ps_flags |= ACPICPU_FLAG_P_FIDVID; 541 542 family = CPUID2FAMILY(ci->ci_signature); 543 544 if (family == 0xf) 545 family += CPUID2EXTFAMILY(ci->ci_signature); 546 547 switch (family) { 548 549 case 0x0f: 550 msr.ps_control_addr = MSR_0FH_CONTROL; 551 msr.ps_status_addr = MSR_0FH_STATUS; 552 break; 553 554 case 0x10: 555 case 0x11: 556 case 0x14: /* AMD Fusion */ 557 msr.ps_control_addr = MSR_10H_CONTROL; 558 msr.ps_control_mask = __BITS(0, 2); 559 560 msr.ps_status_addr = MSR_10H_STATUS; 561 msr.ps_status_mask = __BITS(0, 2); 562 break; 563 564 default: 565 566 if ((sc->sc_flags & ACPICPU_FLAG_P_XPSS) == 0) 567 return EOPNOTSUPP; 568 } 569 570 break; 571 572 default: 573 return ENODEV; 574 } 575 576 /* 577 * Fill the P-state structures with MSR addresses that are 578 * known to be correct. If we do not know the addresses, 579 * leave the values intact. If a vendor uses XPSS, we do 580 * not necessarily need to do anything to support new CPUs. 581 */ 582 while (i < sc->sc_pstate_count) { 583 584 ps = &sc->sc_pstate[i]; 585 586 if (msr.ps_flags != 0) 587 ps->ps_flags |= msr.ps_flags; 588 589 if (msr.ps_status_addr != 0) 590 ps->ps_status_addr = msr.ps_status_addr; 591 592 if (msr.ps_status_mask != 0) 593 ps->ps_status_mask = msr.ps_status_mask; 594 595 if (msr.ps_control_addr != 0) 596 ps->ps_control_addr = msr.ps_control_addr; 597 598 if (msr.ps_control_mask != 0) 599 ps->ps_control_mask = msr.ps_control_mask; 600 601 i++; 602 } 603 604 return 0; 605 } 606 607 /* 608 * Returns the percentage of the actual frequency in 609 * terms of the maximum frequency of the calling CPU 610 * since the last call. A value zero implies an error. 611 */ 612 uint8_t 613 acpicpu_md_pstate_percent(struct acpicpu_softc *sc) 614 { 615 struct cpu_info *ci = sc->sc_ci; 616 uint64_t aperf, mperf; 617 uint64_t xc, rv = 0; 618 619 if (__predict_false((sc->sc_flags & ACPICPU_FLAG_P) == 0)) 620 return 0; 621 622 if (__predict_false((sc->sc_flags & ACPICPU_FLAG_P_HW) == 0)) 623 return 0; 624 625 /* 626 * Read the IA32_APERF and IA32_MPERF counters. The first 627 * increments at the rate of the fixed maximum frequency 628 * configured during the boot, whereas APERF counts at the 629 * rate of the actual frequency. Note that the MSRs must be 630 * read without delay, and that only the ratio between 631 * IA32_APERF and IA32_MPERF is architecturally defined. 632 * 633 * For further details, refer to: 634 * 635 * Intel Corporation: Intel 64 and IA-32 Architectures 636 * Software Developer's Manual. Section 13.2, Volume 3A: 637 * System Programming Guide, Part 1. July, 2008. 638 * 639 * Advanced Micro Devices: BIOS and Kernel Developer's 640 * Guide (BKDG) for AMD Family 10h Processors. Section 641 * 2.4.5, Revision 3.48, April 2010. 642 */ 643 x86_disable_intr(); 644 645 aperf = sc->sc_pstate_aperf; 646 mperf = sc->sc_pstate_mperf; 647 648 xc = xc_unicast(0, acpicpu_md_pstate_percent_status, sc, NULL, ci); 649 xc_wait(xc); 650 651 x86_enable_intr(); 652 653 aperf = sc->sc_pstate_aperf - aperf; 654 mperf = sc->sc_pstate_mperf - mperf; 655 656 if (__predict_true(mperf != 0)) 657 rv = (aperf * 100) / mperf; 658 659 return rv; 660 } 661 662 static void 663 acpicpu_md_pstate_percent_status(void *arg1, void *arg2) 664 { 665 struct acpicpu_softc *sc = arg1; 666 667 sc->sc_pstate_aperf = rdmsr(MSR_APERF); 668 sc->sc_pstate_mperf = rdmsr(MSR_MPERF); 669 } 670 671 static void 672 acpicpu_md_pstate_percent_reset(struct acpicpu_softc *sc) 673 { 674 struct msr_rw_info msr; 675 uint64_t xc; 676 677 KASSERT((sc->sc_flags & ACPICPU_FLAG_P) != 0); 678 KASSERT((sc->sc_flags & ACPICPU_FLAG_P_HW) != 0); 679 680 msr.msr_value = 0; 681 msr.msr_read = false; 682 msr.msr_type = MSR_APERF; 683 684 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 685 xc_wait(xc); 686 687 msr.msr_value = 0; 688 msr.msr_read = false; 689 msr.msr_type = MSR_MPERF; 690 691 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 692 xc_wait(xc); 693 694 sc->sc_pstate_aperf = 0; 695 sc->sc_pstate_mperf = 0; 696 } 697 698 int 699 acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq) 700 { 701 struct acpicpu_pstate *ps = NULL; 702 uint64_t val; 703 uint32_t i; 704 705 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 706 return acpicpu_md_pstate_fidvid_get(sc, freq); 707 708 for (i = 0; i < sc->sc_pstate_count; i++) { 709 710 ps = &sc->sc_pstate[i]; 711 712 if (__predict_true(ps->ps_freq != 0)) 713 break; 714 } 715 716 if (__predict_false(ps == NULL)) 717 return ENODEV; 718 719 if (__predict_false(ps->ps_status_addr == 0)) 720 return EINVAL; 721 722 val = rdmsr(ps->ps_status_addr); 723 724 if (__predict_true(ps->ps_status_mask != 0)) 725 val = val & ps->ps_status_mask; 726 727 for (i = 0; i < sc->sc_pstate_count; i++) { 728 729 ps = &sc->sc_pstate[i]; 730 731 if (__predict_false(ps->ps_freq == 0)) 732 continue; 733 734 if (val == ps->ps_status) { 735 *freq = ps->ps_freq; 736 return 0; 737 } 738 } 739 740 return EIO; 741 } 742 743 int 744 acpicpu_md_pstate_set(struct acpicpu_pstate *ps) 745 { 746 struct msr_rw_info msr; 747 uint64_t xc; 748 int rv = 0; 749 750 if (__predict_false(ps->ps_control_addr == 0)) 751 return EINVAL; 752 753 if ((ps->ps_flags & ACPICPU_FLAG_P_FIDVID) != 0) 754 return acpicpu_md_pstate_fidvid_set(ps); 755 756 msr.msr_read = false; 757 msr.msr_type = ps->ps_control_addr; 758 msr.msr_value = ps->ps_control; 759 760 if (__predict_true(ps->ps_control_mask != 0)) { 761 msr.msr_mask = ps->ps_control_mask; 762 msr.msr_read = true; 763 } 764 765 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 766 xc_wait(xc); 767 768 /* 769 * Due several problems, we bypass the 770 * relatively expensive status check. 771 */ 772 if (acpicpu_pstate_status != true) { 773 DELAY(ps->ps_latency); 774 return 0; 775 } 776 777 xc = xc_broadcast(0, (xcfunc_t)acpicpu_md_pstate_status, ps, &rv); 778 xc_wait(xc); 779 780 return rv; 781 } 782 783 static void 784 acpicpu_md_pstate_status(void *arg1, void *arg2) 785 { 786 struct acpicpu_pstate *ps = arg1; 787 uint64_t val; 788 int i; 789 790 for (i = val = 0; i < ACPICPU_P_STATE_RETRY; i++) { 791 792 val = rdmsr(ps->ps_status_addr); 793 794 if (__predict_true(ps->ps_status_mask != 0)) 795 val = val & ps->ps_status_mask; 796 797 if (val == ps->ps_status) 798 return; 799 800 DELAY(ps->ps_latency); 801 } 802 803 *(uintptr_t *)arg2 = EAGAIN; 804 } 805 806 static int 807 acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *sc, uint32_t *freq) 808 { 809 struct acpicpu_pstate *ps; 810 uint32_t fid, i, vid; 811 uint32_t cfid, cvid; 812 int rv; 813 814 /* 815 * AMD family 0Fh needs special treatment. 816 * While it wants to use ACPI, it does not 817 * comply with the ACPI specifications. 818 */ 819 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 820 821 if (rv != 0) 822 return rv; 823 824 for (i = 0; i < sc->sc_pstate_count; i++) { 825 826 ps = &sc->sc_pstate[i]; 827 828 if (__predict_false(ps->ps_freq == 0)) 829 continue; 830 831 fid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_FID); 832 vid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_VID); 833 834 if (cfid == fid && cvid == vid) { 835 *freq = ps->ps_freq; 836 return 0; 837 } 838 } 839 840 return EIO; 841 } 842 843 static int 844 acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *ps) 845 { 846 const uint64_t ctrl = ps->ps_control; 847 uint32_t cfid, cvid, fid, i, irt; 848 uint32_t pll, vco_cfid, vco_fid; 849 uint32_t val, vid, vst; 850 int rv; 851 852 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 853 854 if (rv != 0) 855 return rv; 856 857 fid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_FID); 858 vid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VID); 859 irt = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_IRT); 860 vst = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VST); 861 pll = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_PLL); 862 863 vst = vst * 20; 864 pll = pll * 1000 / 5; 865 irt = 10 * __BIT(irt); 866 867 /* 868 * Phase 1. 869 */ 870 while (cvid > vid) { 871 872 val = 1 << __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_MVS); 873 val = (val > cvid) ? 0 : cvid - val; 874 875 acpicpu_md_pstate_fidvid_write(cfid, val, 1, vst); 876 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 877 878 if (rv != 0) 879 return rv; 880 } 881 882 i = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_RVO); 883 884 for (; i > 0 && cvid > 0; --i) { 885 886 acpicpu_md_pstate_fidvid_write(cfid, cvid - 1, 1, vst); 887 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 888 889 if (rv != 0) 890 return rv; 891 } 892 893 /* 894 * Phase 2. 895 */ 896 if (cfid != fid) { 897 898 vco_fid = FID_TO_VCO_FID(fid); 899 vco_cfid = FID_TO_VCO_FID(cfid); 900 901 while (abs(vco_fid - vco_cfid) > 2) { 902 903 if (fid <= cfid) 904 val = cfid - 2; 905 else { 906 val = (cfid > 6) ? cfid + 2 : 907 FID_TO_VCO_FID(cfid) + 2; 908 } 909 910 acpicpu_md_pstate_fidvid_write(val, cvid, pll, irt); 911 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 912 913 if (rv != 0) 914 return rv; 915 916 vco_cfid = FID_TO_VCO_FID(cfid); 917 } 918 919 acpicpu_md_pstate_fidvid_write(fid, cvid, pll, irt); 920 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 921 922 if (rv != 0) 923 return rv; 924 } 925 926 /* 927 * Phase 3. 928 */ 929 if (cvid != vid) { 930 931 acpicpu_md_pstate_fidvid_write(cfid, vid, 1, vst); 932 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 933 934 if (rv != 0) 935 return rv; 936 } 937 938 if (cfid != fid || cvid != vid) 939 return EIO; 940 941 return 0; 942 } 943 944 static int 945 acpicpu_md_pstate_fidvid_read(uint32_t *cfid, uint32_t *cvid) 946 { 947 int i = ACPICPU_P_STATE_RETRY * 100; 948 uint64_t val; 949 950 do { 951 val = rdmsr(MSR_0FH_STATUS); 952 953 } while (__SHIFTOUT(val, MSR_0FH_STATUS_PENDING) != 0 && --i >= 0); 954 955 if (i == 0) 956 return EAGAIN; 957 958 if (cfid != NULL) 959 *cfid = __SHIFTOUT(val, MSR_0FH_STATUS_CFID); 960 961 if (cvid != NULL) 962 *cvid = __SHIFTOUT(val, MSR_0FH_STATUS_CVID); 963 964 return 0; 965 } 966 967 static void 968 acpicpu_md_pstate_fidvid_write(uint32_t fid, 969 uint32_t vid, uint32_t cnt, uint32_t tmo) 970 { 971 struct msr_rw_info msr; 972 uint64_t xc; 973 974 msr.msr_read = false; 975 msr.msr_type = MSR_0FH_CONTROL; 976 msr.msr_value = 0; 977 978 msr.msr_value |= __SHIFTIN(fid, MSR_0FH_CONTROL_FID); 979 msr.msr_value |= __SHIFTIN(vid, MSR_0FH_CONTROL_VID); 980 msr.msr_value |= __SHIFTIN(cnt, MSR_0FH_CONTROL_CNT); 981 msr.msr_value |= __SHIFTIN(0x1, MSR_0FH_CONTROL_CHG); 982 983 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 984 xc_wait(xc); 985 986 DELAY(tmo); 987 } 988 989 int 990 acpicpu_md_tstate_get(struct acpicpu_softc *sc, uint32_t *percent) 991 { 992 struct acpicpu_tstate *ts; 993 uint64_t val; 994 uint32_t i; 995 996 val = rdmsr(MSR_THERM_CONTROL); 997 998 for (i = 0; i < sc->sc_tstate_count; i++) { 999 1000 ts = &sc->sc_tstate[i]; 1001 1002 if (ts->ts_percent == 0) 1003 continue; 1004 1005 if (val == ts->ts_status) { 1006 *percent = ts->ts_percent; 1007 return 0; 1008 } 1009 } 1010 1011 return EIO; 1012 } 1013 1014 int 1015 acpicpu_md_tstate_set(struct acpicpu_tstate *ts) 1016 { 1017 struct msr_rw_info msr; 1018 uint64_t xc; 1019 int rv = 0; 1020 1021 msr.msr_read = true; 1022 msr.msr_type = MSR_THERM_CONTROL; 1023 msr.msr_value = ts->ts_control; 1024 msr.msr_mask = __BITS(1, 4); 1025 1026 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 1027 xc_wait(xc); 1028 1029 if (ts->ts_status == 0) { 1030 DELAY(ts->ts_latency); 1031 return 0; 1032 } 1033 1034 xc = xc_broadcast(0, (xcfunc_t)acpicpu_md_tstate_status, ts, &rv); 1035 xc_wait(xc); 1036 1037 return rv; 1038 } 1039 1040 static void 1041 acpicpu_md_tstate_status(void *arg1, void *arg2) 1042 { 1043 struct acpicpu_tstate *ts = arg1; 1044 uint64_t val; 1045 int i; 1046 1047 for (i = val = 0; i < ACPICPU_T_STATE_RETRY; i++) { 1048 1049 val = rdmsr(MSR_THERM_CONTROL); 1050 1051 if (val == ts->ts_status) 1052 return; 1053 1054 DELAY(ts->ts_latency); 1055 } 1056 1057 *(uintptr_t *)arg2 = EAGAIN; 1058 } 1059 1060 /* 1061 * A kludge for backwards compatibility. 1062 */ 1063 static int 1064 acpicpu_md_pstate_sysctl_init(void) 1065 { 1066 const struct sysctlnode *fnode, *mnode, *rnode; 1067 const char *str; 1068 int rv; 1069 1070 switch (cpu_vendor) { 1071 1072 case CPUVENDOR_IDT: 1073 case CPUVENDOR_INTEL: 1074 str = "est"; 1075 break; 1076 1077 case CPUVENDOR_AMD: 1078 str = "powernow"; 1079 break; 1080 1081 default: 1082 return ENODEV; 1083 } 1084 1085 1086 rv = sysctl_createv(&acpicpu_log, 0, NULL, &rnode, 1087 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 1088 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 1089 1090 if (rv != 0) 1091 goto fail; 1092 1093 rv = sysctl_createv(&acpicpu_log, 0, &rnode, &mnode, 1094 0, CTLTYPE_NODE, str, NULL, 1095 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1096 1097 if (rv != 0) 1098 goto fail; 1099 1100 rv = sysctl_createv(&acpicpu_log, 0, &mnode, &fnode, 1101 0, CTLTYPE_NODE, "frequency", NULL, 1102 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1103 1104 if (rv != 0) 1105 goto fail; 1106 1107 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1108 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 1109 acpicpu_md_pstate_sysctl_set, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1110 1111 if (rv != 0) 1112 goto fail; 1113 1114 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1115 CTLFLAG_READONLY, CTLTYPE_INT, "current", NULL, 1116 acpicpu_md_pstate_sysctl_get, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1117 1118 if (rv != 0) 1119 goto fail; 1120 1121 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1122 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 1123 acpicpu_md_pstate_sysctl_all, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1124 1125 if (rv != 0) 1126 goto fail; 1127 1128 return 0; 1129 1130 fail: 1131 if (acpicpu_log != NULL) { 1132 sysctl_teardown(&acpicpu_log); 1133 acpicpu_log = NULL; 1134 } 1135 1136 return rv; 1137 } 1138 1139 static int 1140 acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS) 1141 { 1142 struct cpu_info *ci = curcpu(); 1143 struct acpicpu_softc *sc; 1144 struct sysctlnode node; 1145 uint32_t freq; 1146 int err; 1147 1148 sc = acpicpu_sc[ci->ci_acpiid]; 1149 1150 if (sc == NULL) 1151 return ENXIO; 1152 1153 err = acpicpu_pstate_get(sc, &freq); 1154 1155 if (err != 0) 1156 return err; 1157 1158 node = *rnode; 1159 node.sysctl_data = &freq; 1160 1161 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1162 1163 if (err != 0 || newp == NULL) 1164 return err; 1165 1166 return 0; 1167 } 1168 1169 static int 1170 acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS) 1171 { 1172 struct cpu_info *ci = curcpu(); 1173 struct acpicpu_softc *sc; 1174 struct sysctlnode node; 1175 uint32_t freq; 1176 int err; 1177 1178 sc = acpicpu_sc[ci->ci_acpiid]; 1179 1180 if (sc == NULL) 1181 return ENXIO; 1182 1183 err = acpicpu_pstate_get(sc, &freq); 1184 1185 if (err != 0) 1186 return err; 1187 1188 node = *rnode; 1189 node.sysctl_data = &freq; 1190 1191 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1192 1193 if (err != 0 || newp == NULL) 1194 return err; 1195 1196 err = acpicpu_pstate_set(sc, freq); 1197 1198 if (err != 0) 1199 return err; 1200 1201 return 0; 1202 } 1203 1204 static int 1205 acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS) 1206 { 1207 struct cpu_info *ci = curcpu(); 1208 struct acpicpu_softc *sc; 1209 struct sysctlnode node; 1210 char buf[1024]; 1211 size_t len; 1212 uint32_t i; 1213 int err; 1214 1215 sc = acpicpu_sc[ci->ci_acpiid]; 1216 1217 if (sc == NULL) 1218 return ENXIO; 1219 1220 (void)memset(&buf, 0, sizeof(buf)); 1221 1222 mutex_enter(&sc->sc_mtx); 1223 1224 for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) { 1225 1226 if (sc->sc_pstate[i].ps_freq == 0) 1227 continue; 1228 1229 len += snprintf(buf + len, sizeof(buf) - len, "%u%s", 1230 sc->sc_pstate[i].ps_freq, 1231 i < (sc->sc_pstate_count - 1) ? " " : ""); 1232 } 1233 1234 mutex_exit(&sc->sc_mtx); 1235 1236 node = *rnode; 1237 node.sysctl_data = buf; 1238 1239 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1240 1241 if (err != 0 || newp == NULL) 1242 return err; 1243 1244 return 0; 1245 } 1246 1247
Indexes created Tue Sep 30 20:09:53 GMT 2025