acpi_cpu_md.c revision 1.9 1 /* $NetBSD: acpi_cpu_md.c,v 1.9 2010/08/09 15:46:17 jruoho Exp $ */
2
3 /*-
4 * Copyright (c) 2010 Jukka Ruohonen <jruohonen (at) iki.fi>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.9 2010/08/09 15:46:17 jruoho Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/kcore.h>
35 #include <sys/sysctl.h>
36 #include <sys/xcall.h>
37
38 #include <x86/cpu.h>
39 #include <x86/cpufunc.h>
40 #include <x86/cputypes.h>
41 #include <x86/cpuvar.h>
42 #include <x86/cpu_msr.h>
43 #include <x86/machdep.h>
44
45 #include <dev/acpi/acpica.h>
46 #include <dev/acpi/acpi_cpu.h>
47
48 static char native_idle_text[16];
49 void (*native_idle)(void) = NULL;
50 void (*native_cpu_freq_init)(int) = NULL;
51
52 static int acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO);
53 static int acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO);
54 static int acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO);
55
56 extern uint32_t cpus_running;
57 extern struct acpicpu_softc **acpicpu_sc;
58
59 uint32_t
60 acpicpu_md_cap(void)
61 {
62 struct cpu_info *ci = curcpu();
63 uint32_t val = 0;
64
65 if (cpu_vendor != CPUVENDOR_INTEL)
66 return val;
67
68 /*
69 * Basic SMP C-states (required for _CST).
70 */
71 val |= ACPICPU_PDC_C_C1PT | ACPICPU_PDC_C_C2C3;
72
73 /*
74 * If MONITOR/MWAIT is available, announce
75 * support for native instructions in all C-states.
76 */
77 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0)
78 val |= ACPICPU_PDC_C_C1_FFH | ACPICPU_PDC_C_C2C3_FFH;
79
80 /*
81 * Set native P-states if EST is available.
82 */
83 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0)
84 val |= ACPICPU_PDC_P_FFH;
85
86 return val;
87 }
88
89 uint32_t
90 acpicpu_md_quirks(void)
91 {
92 struct cpu_info *ci = curcpu();
93 uint32_t val = 0;
94
95 if (acpicpu_md_cpus_running() == 1)
96 val |= ACPICPU_FLAG_C_BM;
97
98 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0)
99 val |= ACPICPU_FLAG_C_FFH;
100
101 switch (cpu_vendor) {
102
103 case CPUVENDOR_INTEL:
104
105 val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB;
106
107 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0)
108 val |= ACPICPU_FLAG_P_FFH;
109
110 /*
111 * Bus master arbitration is not
112 * needed on some recent Intel CPUs.
113 */
114 if (CPUID2FAMILY(ci->ci_signature) > 15)
115 val &= ~ACPICPU_FLAG_C_ARB;
116
117 if (CPUID2FAMILY(ci->ci_signature) == 6 &&
118 CPUID2MODEL(ci->ci_signature) >= 15)
119 val &= ~ACPICPU_FLAG_C_ARB;
120
121 break;
122
123 case CPUVENDOR_AMD:
124
125 /*
126 * XXX: Deal with the AMD C1E extension here.
127 */
128 break;
129 }
130
131 return val;
132 }
133
134 uint32_t
135 acpicpu_md_cpus_running(void)
136 {
137
138 return popcount32(cpus_running);
139 }
140
141 int
142 acpicpu_md_idle_start(void)
143 {
144 const size_t size = sizeof(native_idle_text);
145
146 x86_disable_intr();
147 x86_cpu_idle_get(&native_idle, native_idle_text, size);
148 x86_cpu_idle_set(acpicpu_cstate_idle, "acpi");
149 x86_enable_intr();
150
151 return 0;
152 }
153
154 int
155 acpicpu_md_idle_stop(void)
156 {
157 uint64_t xc;
158
159 x86_disable_intr();
160 x86_cpu_idle_set(native_idle, native_idle_text);
161 x86_enable_intr();
162
163 /*
164 * Run a cross-call to ensure that all CPUs are
165 * out from the ACPI idle-loop before detachment.
166 */
167 xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL);
168 xc_wait(xc);
169
170 return 0;
171 }
172
173 /*
174 * The MD idle loop. Called with interrupts disabled.
175 */
176 void
177 acpicpu_md_idle_enter(int method, int state)
178 {
179 struct cpu_info *ci = curcpu();
180
181 switch (method) {
182
183 case ACPICPU_C_STATE_FFH:
184
185 x86_enable_intr();
186 x86_monitor(&ci->ci_want_resched, 0, 0);
187
188 if (__predict_false(ci->ci_want_resched) != 0)
189 return;
190
191 x86_mwait((state - 1) << 4, 0);
192 break;
193
194 case ACPICPU_C_STATE_HALT:
195
196 if (__predict_false(ci->ci_want_resched) != 0) {
197 x86_enable_intr();
198 return;
199 }
200
201 x86_stihlt();
202 break;
203 }
204 }
205
206 int
207 acpicpu_md_pstate_start(void)
208 {
209 const struct sysctlnode *fnode, *mnode, *rnode;
210 const char *str;
211 int rv;
212
213 switch (cpu_vendor) {
214
215 case CPUVENDOR_INTEL:
216 str = "est";
217 break;
218
219 default:
220 return ENODEV;
221 }
222
223 /*
224 * A kludge for backwards compatibility.
225 */
226 native_cpu_freq_init = cpu_freq_init;
227
228 if (cpu_freq_sysctllog != NULL) {
229 sysctl_teardown(&cpu_freq_sysctllog);
230 cpu_freq_sysctllog = NULL;
231 }
232
233 rv = sysctl_createv(&cpu_freq_sysctllog, 0, NULL, &rnode,
234 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL,
235 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL);
236
237 if (rv != 0)
238 goto fail;
239
240 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &rnode, &mnode,
241 0, CTLTYPE_NODE, str, NULL,
242 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL);
243
244 if (rv != 0)
245 goto fail;
246
247 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &mnode, &fnode,
248 0, CTLTYPE_NODE, "frequency", NULL,
249 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL);
250
251 if (rv != 0)
252 goto fail;
253
254 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &fnode, &rnode,
255 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL,
256 acpicpu_md_pstate_sysctl_set, 0, NULL, 0, CTL_CREATE, CTL_EOL);
257
258 if (rv != 0)
259 goto fail;
260
261 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &fnode, &rnode,
262 CTLFLAG_READONLY, CTLTYPE_INT, "current", NULL,
263 acpicpu_md_pstate_sysctl_get, 0, NULL, 0, CTL_CREATE, CTL_EOL);
264
265 if (rv != 0)
266 goto fail;
267
268 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &fnode, &rnode,
269 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL,
270 acpicpu_md_pstate_sysctl_all, 0, NULL, 0, CTL_CREATE, CTL_EOL);
271
272 if (rv != 0)
273 goto fail;
274
275 return 0;
276
277 fail:
278 if (cpu_freq_sysctllog != NULL) {
279 sysctl_teardown(&cpu_freq_sysctllog);
280 cpu_freq_sysctllog = NULL;
281 }
282
283 if (native_cpu_freq_init != NULL)
284 (*native_cpu_freq_init)(cpu_vendor);
285
286 return rv;
287 }
288
289 int
290 acpicpu_md_pstate_stop(void)
291 {
292
293 if (cpu_freq_sysctllog != NULL) {
294 sysctl_teardown(&cpu_freq_sysctllog);
295 cpu_freq_sysctllog = NULL;
296 }
297
298 if (native_cpu_freq_init != NULL)
299 (*native_cpu_freq_init)(cpu_vendor);
300
301 return 0;
302 }
303
304 static int
305 acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS)
306 {
307 struct cpu_info *ci = curcpu();
308 struct acpicpu_softc *sc;
309 struct sysctlnode node;
310 uint32_t freq;
311 int err;
312
313 /*
314 * We can use any ACPI CPU to manipulate the
315 * frequencies. In MP environments all CPUs
316 * are mandated to support the same number of
317 * P-states and each state must have identical
318 * parameters across processors.
319 */
320 sc = acpicpu_sc[ci->ci_acpiid];
321
322 if (sc == NULL)
323 return ENXIO;
324
325 err = acpicpu_pstate_get(sc, &freq);
326
327 if (err != 0)
328 return err;
329
330 node = *rnode;
331 node.sysctl_data = &freq;
332
333 err = sysctl_lookup(SYSCTLFN_CALL(&node));
334
335 if (err != 0 || newp == NULL)
336 return err;
337
338 return 0;
339 }
340
341 static int
342 acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS)
343 {
344 struct cpu_info *ci = curcpu();
345 struct acpicpu_softc *sc;
346 struct sysctlnode node;
347 uint32_t freq;
348 int err;
349
350 sc = acpicpu_sc[ci->ci_acpiid];
351
352 if (sc == NULL)
353 return ENXIO;
354
355 err = acpicpu_pstate_get(sc, &freq);
356
357 if (err != 0)
358 return err;
359
360 node = *rnode;
361 node.sysctl_data = &freq;
362
363 err = sysctl_lookup(SYSCTLFN_CALL(&node));
364
365 if (err != 0 || newp == NULL)
366 return err;
367
368 err = acpicpu_pstate_set(sc, freq);
369
370 if (err != 0)
371 return err;
372
373 return 0;
374 }
375
376 static int
377 acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS)
378 {
379 struct cpu_info *ci = curcpu();
380 struct acpicpu_softc *sc;
381 struct sysctlnode node;
382 char buf[1024];
383 size_t len;
384 uint32_t i;
385 int err;
386
387 sc = acpicpu_sc[ci->ci_acpiid];
388
389 if (sc == NULL)
390 return ENXIO;
391
392 (void)memset(&buf, 0, sizeof(buf));
393
394 mutex_enter(&sc->sc_mtx);
395
396 for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) {
397
398 if (sc->sc_pstate[i].ps_freq == 0)
399 continue;
400
401 len += snprintf(buf + len, sizeof(buf) - len, "%u%s",
402 sc->sc_pstate[i].ps_freq,
403 i < (sc->sc_pstate_count - 1) ? " " : "");
404 }
405
406 mutex_exit(&sc->sc_mtx);
407
408 node = *rnode;
409 node.sysctl_data = buf;
410
411 err = sysctl_lookup(SYSCTLFN_CALL(&node));
412
413 if (err != 0 || newp == NULL)
414 return err;
415
416 return 0;
417 }
418
419 int
420 acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq)
421 {
422 struct acpicpu_pstate *ps;
423 uint64_t val;
424 uint32_t i;
425
426 switch (cpu_vendor) {
427
428 case CPUVENDOR_INTEL:
429
430 val = rdmsr(MSR_PERF_STATUS);
431 val = val & 0xffff;
432
433 mutex_enter(&sc->sc_mtx);
434
435 for (i = 0; i < sc->sc_pstate_count; i++) {
436
437 ps = &sc->sc_pstate[i];
438
439 if (ps->ps_freq == 0)
440 continue;
441
442 if (val == ps->ps_status) {
443 mutex_exit(&sc->sc_mtx);
444 *freq = ps->ps_freq;
445 return 0;
446 }
447 }
448
449 mutex_exit(&sc->sc_mtx);
450
451 return EIO;
452
453 default:
454 return ENODEV;
455 }
456
457 return 0;
458 }
459
460 int
461 acpicpu_md_pstate_set(struct acpicpu_pstate *ps)
462 {
463 struct msr_rw_info msr;
464 uint64_t xc, val;
465 int i;
466
467 switch (cpu_vendor) {
468
469 case CPUVENDOR_INTEL:
470 msr.msr_read = true;
471 msr.msr_type = MSR_PERF_CTL;
472 msr.msr_value = ps->ps_control;
473 msr.msr_mask = 0xffffULL;
474 break;
475
476 default:
477 return ENODEV;
478 }
479
480 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL);
481 xc_wait(xc);
482
483 for (i = val = 0; i < ACPICPU_P_STATE_RETRY; i++) {
484
485 val = rdmsr(MSR_PERF_STATUS);
486 val = val & 0xffff;
487
488 if (val == ps->ps_status)
489 return 0;
490
491 DELAY(ps->ps_latency);
492 }
493
494 return EAGAIN;
495 }
496