cpu.h revision 1.117
1 /* $NetBSD: cpu.h,v 1.117 2020/01/15 13:22:03 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 35 */ 36 37 #ifndef _X86_CPU_H_ 38 #define _X86_CPU_H_ 39 40 #if defined(_KERNEL) || defined(_STANDALONE) 41 #include <sys/types.h> 42 #else 43 #include <stdint.h> 44 #include <stdbool.h> 45 #endif /* _KERNEL || _STANDALONE */ 46 47 #if defined(_KERNEL) || defined(_KMEMUSER) 48 #if defined(_KERNEL_OPT) 49 #include "opt_xen.h" 50 #include "opt_svs.h" 51 #ifdef i386 52 #include "opt_user_ldt.h" 53 #endif 54 #endif 55 56 /* 57 * Definitions unique to x86 cpu support. 58 */ 59 #include <machine/frame.h> 60 #include <machine/pte.h> 61 #include <machine/segments.h> 62 #include <machine/tss.h> 63 #include <machine/intrdefs.h> 64 65 #include <x86/cacheinfo.h> 66 67 #include <sys/cpu_data.h> 68 #include <sys/evcnt.h> 69 #include <sys/device_if.h> /* for device_t */ 70 71 #ifdef XEN 72 #include <xen/include/public/xen.h> 73 #include <xen/include/public/event_channel.h> 74 #include <sys/mutex.h> 75 #endif /* XEN */ 76 77 struct intrsource; 78 struct pmap; 79 struct kcpuset; 80 81 #ifdef __x86_64__ 82 #define i386tss x86_64_tss 83 #endif 84 85 #define NIOPORTS 1024 /* # of ports we allow to be mapped */ 86 #define IOMAPSIZE (NIOPORTS / 8) /* I/O bitmap size in bytes */ 87 88 struct cpu_tss { 89 #ifdef i386 90 struct i386tss dblflt_tss; 91 struct i386tss ddbipi_tss; 92 #endif 93 struct i386tss tss; 94 uint8_t iomap[IOMAPSIZE]; 95 } __packed; 96 97 /* 98 * Arguments to hardclock, softclock and statclock 99 * encapsulate the previous machine state in an opaque 100 * clockframe; for now, use generic intrframe. 101 */ 102 struct clockframe { 103 struct intrframe cf_if; 104 }; 105 106 /* 107 * a bunch of this belongs in cpuvar.h; move it later.. 108 */ 109 110 struct cpu_info { 111 struct cpu_data ci_data; /* MI per-cpu data */ 112 device_t ci_dev; /* pointer to our device */ 113 struct cpu_info *ci_self; /* self-pointer */ 114 #ifdef XEN 115 volatile struct vcpu_info *ci_vcpu; /* for XEN */ 116 #endif 117 118 /* 119 * Private members. 120 */ 121 struct pmap *ci_pmap; /* current pmap */ 122 int ci_want_pmapload; /* pmap_load() is needed */ 123 volatile int ci_tlbstate; /* one of TLBSTATE_ states. see below */ 124 #define TLBSTATE_VALID 0 /* all user tlbs are valid */ 125 #define TLBSTATE_LAZY 1 /* tlbs are valid but won't be kept uptodate */ 126 #define TLBSTATE_STALE 2 /* we might have stale user tlbs */ 127 int ci_curldt; /* current LDT descriptor */ 128 int ci_nintrhand; /* number of H/W interrupt handlers */ 129 uint64_t ci_scratch; 130 uintptr_t ci_pmap_data[128 / sizeof(uintptr_t)]; 131 struct kcpuset *ci_tlb_cpuset; 132 133 int ci_kfpu_spl; 134 135 #ifndef XENPV 136 struct intrsource *ci_isources[MAX_INTR_SOURCES]; 137 #endif 138 #if defined(XEN) 139 struct intrsource *ci_xsources[NIPL]; 140 uint32_t ci_xmask[NIPL]; 141 uint32_t ci_xunmask[NIPL]; 142 uint32_t ci_xpending; /* XEN doesn't use the cmpxchg8 path */ 143 #endif 144 145 volatile int ci_mtx_count; /* Negative count of spin mutexes */ 146 volatile int ci_mtx_oldspl; /* Old SPL at this ci_idepth */ 147 148 /* The following must be aligned for cmpxchg8b. */ 149 struct { 150 uint32_t ipending; 151 int ilevel; 152 uint32_t imasked; 153 } ci_istate __aligned(8); 154 #define ci_ipending ci_istate.ipending 155 #define ci_ilevel ci_istate.ilevel 156 #define ci_imasked ci_istate.imasked 157 int ci_idepth; 158 void * ci_intrstack; 159 uint32_t ci_imask[NIPL]; 160 uint32_t ci_iunmask[NIPL]; 161 162 uint32_t ci_signature; /* X86 cpuid type (cpuid.1.%eax) */ 163 uint32_t ci_vendor[4]; /* vendor string */ 164 uint32_t ci_max_cpuid; /* cpuid.0:%eax */ 165 uint32_t ci_max_ext_cpuid; /* cpuid.80000000:%eax */ 166 volatile uint32_t ci_lapic_counter; 167 168 uint32_t ci_feat_val[8]; /* X86 CPUID feature bits */ 169 /* [0] basic features cpuid.1:%edx 170 * [1] basic features cpuid.1:%ecx (CPUID2_xxx bits) 171 * [2] extended features cpuid:80000001:%edx 172 * [3] extended features cpuid:80000001:%ecx 173 * [4] VIA padlock features 174 * [5] structured extended features cpuid.7:%ebx 175 * [6] structured extended features cpuid.7:%ecx 176 * [7] structured extended features cpuid.7:%edx 177 */ 178 179 const struct cpu_functions *ci_func; /* start/stop functions */ 180 struct trapframe *ci_ddb_regs; 181 182 u_int ci_cflush_lsize; /* CLFLUSH insn line size */ 183 struct x86_cache_info ci_cinfo[CAI_COUNT]; 184 185 device_t ci_frequency; /* Frequency scaling technology */ 186 device_t ci_padlock; /* VIA PadLock private storage */ 187 device_t ci_temperature; /* Intel coretemp(4) or equivalent */ 188 device_t ci_vm; /* Virtual machine guest driver */ 189 190 /* 191 * Segmentation-related data. 192 */ 193 union descriptor *ci_gdt; 194 struct cpu_tss *ci_tss; /* Per-cpu TSSes; shared among LWPs */ 195 int ci_tss_sel; /* TSS selector of this cpu */ 196 197 /* 198 * The following two are actually region_descriptors, 199 * but that would pollute the namespace. 200 */ 201 uintptr_t ci_suspend_gdt; 202 uint16_t ci_suspend_gdt_padding; 203 uintptr_t ci_suspend_idt; 204 uint16_t ci_suspend_idt_padding; 205 206 uint16_t ci_suspend_tr; 207 uint16_t ci_suspend_ldt; 208 uintptr_t ci_suspend_fs; 209 uintptr_t ci_suspend_gs; 210 uintptr_t ci_suspend_kgs; 211 uintptr_t ci_suspend_efer; 212 uintptr_t ci_suspend_reg[12]; 213 uintptr_t ci_suspend_cr0; 214 uintptr_t ci_suspend_cr2; 215 uintptr_t ci_suspend_cr3; 216 uintptr_t ci_suspend_cr4; 217 uintptr_t ci_suspend_cr8; 218 219 /* 220 * The following must be in their own cache line, as they are 221 * stored to regularly by remote CPUs; when they were mixed with 222 * other fields we observed frequent cache misses. 223 */ 224 int ci_want_resched __aligned(64); 225 uint32_t ci_ipis; /* interprocessor interrupts pending */ 226 227 /* 228 * These are largely static, and will be frequently fetched by other 229 * CPUs. For that reason they get their own cache line, too. 230 */ 231 uint32_t ci_flags __aligned(64);/* general flags */ 232 uint32_t ci_acpiid; /* our ACPI/MADT ID */ 233 uint32_t ci_initapicid; /* our initial APIC ID */ 234 cpuid_t ci_cpuid; /* our CPU ID */ 235 struct cpu_info *ci_next; /* next cpu */ 236 237 /* 238 * This is stored frequently, and is fetched by remote CPUs. 239 */ 240 struct lwp *ci_curlwp __aligned(64);/* general flags */ 241 struct lwp *ci_onproc; /* current user LWP / kthread */ 242 243 /* Here ends the cachline-aligned sections. */ 244 int ci_padout __aligned(64); 245 246 #ifndef __HAVE_DIRECT_MAP 247 #define VPAGE_SRC 0 248 #define VPAGE_DST 1 249 #define VPAGE_ZER 2 250 #define VPAGE_PTP 3 251 #define VPAGE_MAX 4 252 vaddr_t vpage[VPAGE_MAX]; 253 pt_entry_t *vpage_pte[VPAGE_MAX]; 254 #endif 255 256 #ifdef PAE 257 uint32_t ci_pae_l3_pdirpa; /* PA of L3 PD */ 258 pd_entry_t * ci_pae_l3_pdir; /* VA pointer to L3 PD */ 259 #endif 260 261 #ifdef SVS 262 pd_entry_t * ci_svs_updir; 263 paddr_t ci_svs_updirpa; 264 int ci_svs_ldt_sel; 265 kmutex_t ci_svs_mtx; 266 pd_entry_t * ci_svs_rsp0_pte; 267 vaddr_t ci_svs_rsp0; 268 vaddr_t ci_svs_ursp0; 269 vaddr_t ci_svs_krsp0; 270 vaddr_t ci_svs_utls; 271 #endif 272 273 #ifdef XEN 274 u_long ci_evtmask[NR_EVENT_CHANNELS]; /* events allowed on this CPU */ 275 struct evcnt ci_ipi_events[XEN_NIPIS]; 276 evtchn_port_t ci_ipi_evtchn; 277 #if defined(XENPV) 278 #if defined(PAE) || defined(__x86_64__) 279 /* Currently active user PGD (can't use rcr3() with Xen) */ 280 pd_entry_t * ci_kpm_pdir; /* per-cpu PMD (va) */ 281 paddr_t ci_kpm_pdirpa; /* per-cpu PMD (pa) */ 282 kmutex_t ci_kpm_mtx; 283 #endif /* defined(PAE) || defined(__x86_64__) */ 284 285 #if defined(__x86_64__) 286 /* per-cpu version of normal_pdes */ 287 pd_entry_t * ci_normal_pdes[3]; /* Ok to hardcode. only for x86_64 && XENPV */ 288 paddr_t ci_xen_current_user_pgd; 289 #endif /* defined(__x86_64__) */ 290 291 size_t ci_xpq_idx; 292 #endif /* XENPV */ 293 294 /* Xen raw system time at which we last ran hardclock. */ 295 uint64_t ci_xen_hardclock_systime_ns; 296 297 /* 298 * Last TSC-adjusted local Xen system time we observed. Used 299 * to detect whether the Xen clock has gone backwards. 300 */ 301 uint64_t ci_xen_last_systime_ns; 302 303 /* 304 * Distance in nanoseconds from the local view of system time 305 * to the global view of system time, if the local time is 306 * behind the global time. 307 */ 308 uint64_t ci_xen_systime_ns_skew; 309 310 /* Xen periodic timer interrupt handle. */ 311 struct intrhand *ci_xen_timer_intrhand; 312 313 /* 314 * Clockframe for timer interrupt handler. 315 * Saved at entry via event callback. 316 */ 317 vaddr_t ci_xen_clockf_pc; /* RIP at last event interrupt */ 318 bool ci_xen_clockf_usermode; /* Was the guest in usermode ? */ 319 320 /* Event counters for various pathologies that might happen. */ 321 struct evcnt ci_xen_cpu_tsc_backwards_evcnt; 322 struct evcnt ci_xen_tsc_delta_negative_evcnt; 323 struct evcnt ci_xen_raw_systime_wraparound_evcnt; 324 struct evcnt ci_xen_raw_systime_backwards_evcnt; 325 struct evcnt ci_xen_systime_backwards_hardclock_evcnt; 326 struct evcnt ci_xen_missed_hardclock_evcnt; 327 #else /* XEN */ 328 struct evcnt ci_ipi_events[X86_NIPI]; 329 #endif /* XEN */ 330 331 }; 332 333 /* 334 * Macros to handle (some) trapframe registers for common x86 code. 335 */ 336 #ifdef __x86_64__ 337 #define X86_TF_RAX(tf) tf->tf_rax 338 #define X86_TF_RDX(tf) tf->tf_rdx 339 #define X86_TF_RSP(tf) tf->tf_rsp 340 #define X86_TF_RIP(tf) tf->tf_rip 341 #define X86_TF_RFLAGS(tf) tf->tf_rflags 342 #else 343 #define X86_TF_RAX(tf) tf->tf_eax 344 #define X86_TF_RDX(tf) tf->tf_edx 345 #define X86_TF_RSP(tf) tf->tf_esp 346 #define X86_TF_RIP(tf) tf->tf_eip 347 #define X86_TF_RFLAGS(tf) tf->tf_eflags 348 #endif 349 350 /* 351 * Processor flag notes: The "primary" CPU has certain MI-defined 352 * roles (mostly relating to hardclock handling); we distinguish 353 * between the processor which booted us, and the processor currently 354 * holding the "primary" role just to give us the flexibility later to 355 * change primaries should we be sufficiently twisted. 356 */ 357 358 #define CPUF_BSP 0x0001 /* CPU is the original BSP */ 359 #define CPUF_AP 0x0002 /* CPU is an AP */ 360 #define CPUF_SP 0x0004 /* CPU is only processor */ 361 #define CPUF_PRIMARY 0x0008 /* CPU is active primary processor */ 362 363 #define CPUF_SYNCTSC 0x0800 /* Synchronize TSC */ 364 #define CPUF_PRESENT 0x1000 /* CPU is present */ 365 #define CPUF_RUNNING 0x2000 /* CPU is running */ 366 #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ 367 #define CPUF_GO 0x8000 /* CPU should start running */ 368 369 #endif /* _KERNEL || __KMEMUSER */ 370 371 #ifdef _KERNEL 372 /* 373 * We statically allocate the CPU info for the primary CPU (or, 374 * the only CPU on uniprocessors), and the primary CPU is the 375 * first CPU on the CPU info list. 376 */ 377 extern struct cpu_info cpu_info_primary; 378 extern struct cpu_info *cpu_info_list; 379 380 #define CPU_INFO_ITERATOR int __unused 381 #define CPU_INFO_FOREACH(cii, ci) ci = cpu_info_list; \ 382 ci != NULL; ci = ci->ci_next 383 384 #define CPU_STARTUP(_ci, _target) ((_ci)->ci_func->start(_ci, _target)) 385 #define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci)) 386 #define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci)) 387 388 #if !defined(__GNUC__) || defined(_MODULE) 389 /* For non-GCC and modules */ 390 struct cpu_info *x86_curcpu(void); 391 # ifdef __GNUC__ 392 lwp_t *x86_curlwp(void) __attribute__ ((const)); 393 # else 394 lwp_t *x86_curlwp(void); 395 # endif 396 #endif 397 398 #define cpu_number() (cpu_index(curcpu())) 399 400 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 401 402 #define aston(l) ((l)->l_md.md_astpending = 1) 403 404 void cpu_boot_secondary_processors(void); 405 void cpu_init_idle_lwps(void); 406 void cpu_init_msrs(struct cpu_info *, bool); 407 void cpu_load_pmap(struct pmap *, struct pmap *); 408 void cpu_broadcast_halt(void); 409 void cpu_kick(struct cpu_info *); 410 411 void cpu_pcpuarea_init(struct cpu_info *); 412 void cpu_svs_init(struct cpu_info *); 413 void cpu_speculation_init(struct cpu_info *); 414 415 #define curcpu() x86_curcpu() 416 #define curlwp x86_curlwp() 417 #define curpcb ((struct pcb *)lwp_getpcb(curlwp)) 418 419 /* 420 * Give a profiling tick to the current process when the user profiling 421 * buffer pages are invalid. On the i386, request an ast to send us 422 * through trap(), marking the proc as needing a profiling tick. 423 */ 424 extern void cpu_need_proftick(struct lwp *l); 425 426 /* 427 * Notify the LWP l that it has a signal pending, process as soon as 428 * possible. 429 */ 430 extern void cpu_signotify(struct lwp *); 431 432 /* 433 * We need a machine-independent name for this. 434 */ 435 extern void (*delay_func)(unsigned int); 436 struct timeval; 437 438 #ifndef __HIDE_DELAY 439 #define DELAY(x) (*delay_func)(x) 440 #define delay(x) (*delay_func)(x) 441 #endif 442 443 extern int biosbasemem; 444 extern int biosextmem; 445 extern int cputype; 446 extern int cpuid_level; 447 extern int cpu_class; 448 extern char cpu_brand_string[]; 449 extern int use_pae; 450 451 #ifdef __i386__ 452 #define i386_fpu_present 1 453 int npx586bug1(int, int); 454 extern int i386_fpu_fdivbug; 455 extern int i386_use_fxsave; 456 extern int i386_has_sse; 457 extern int i386_has_sse2; 458 #else 459 #define i386_fpu_present 1 460 #define i386_fpu_fdivbug 0 461 #define i386_use_fxsave 1 462 #define i386_has_sse 1 463 #define i386_has_sse2 1 464 #endif 465 466 extern int x86_fpu_save; 467 #define FPU_SAVE_FSAVE 0 468 #define FPU_SAVE_FXSAVE 1 469 #define FPU_SAVE_XSAVE 2 470 #define FPU_SAVE_XSAVEOPT 3 471 extern unsigned int x86_fpu_save_size; 472 extern uint64_t x86_xsave_features; 473 extern size_t x86_xsave_offsets[]; 474 extern size_t x86_xsave_sizes[]; 475 extern uint32_t x86_fpu_mxcsr_mask; 476 477 extern void (*x86_cpu_idle)(void); 478 #define cpu_idle() (*x86_cpu_idle)() 479 480 /* machdep.c */ 481 #ifdef i386 482 void cpu_set_tss_gates(struct cpu_info *); 483 #endif 484 void cpu_reset(void); 485 486 /* longrun.c */ 487 u_int tmx86_get_longrun_mode(void); 488 void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 489 void tmx86_init_longrun(void); 490 491 /* identcpu.c */ 492 void cpu_probe(struct cpu_info *); 493 void cpu_identify(struct cpu_info *); 494 void identify_hypervisor(void); 495 496 typedef enum vm_guest { 497 VM_GUEST_NO = 0, 498 VM_GUEST_VM, 499 VM_GUEST_XEN, 500 VM_GUEST_XENPVHVM, 501 VM_GUEST_HV, 502 VM_GUEST_VMWARE, 503 VM_GUEST_KVM, 504 VM_LAST 505 } vm_guest_t; 506 extern vm_guest_t vm_guest; 507 508 /* cpu_topology.c */ 509 void x86_cpu_topology(struct cpu_info *); 510 511 /* locore.s */ 512 struct region_descriptor; 513 void lgdt(struct region_descriptor *); 514 #ifdef XENPV 515 void lgdt_finish(void); 516 #endif 517 518 struct pcb; 519 void savectx(struct pcb *); 520 void lwp_trampoline(void); 521 #ifdef XEN 522 void xen_startrtclock(void); 523 void xen_delay(unsigned int); 524 void xen_initclocks(void); 525 void xen_suspendclocks(struct cpu_info *); 526 void xen_resumeclocks(struct cpu_info *); 527 #endif /* XEN */ 528 /* clock.c */ 529 void initrtclock(u_long); 530 void startrtclock(void); 531 void i8254_delay(unsigned int); 532 void i8254_microtime(struct timeval *); 533 void i8254_initclocks(void); 534 unsigned int gettick(void); 535 extern void (*x86_delay)(unsigned int); 536 537 /* cpu.c */ 538 void cpu_probe_features(struct cpu_info *); 539 540 /* vm_machdep.c */ 541 void cpu_proc_fork(struct proc *, struct proc *); 542 paddr_t kvtop(void *); 543 544 #ifdef USER_LDT 545 /* sys_machdep.h */ 546 int x86_get_ldt(struct lwp *, void *, register_t *); 547 int x86_set_ldt(struct lwp *, void *, register_t *); 548 #endif 549 550 /* isa_machdep.c */ 551 void isa_defaultirq(void); 552 int isa_nmi(void); 553 554 /* consinit.c */ 555 void kgdb_port_init(void); 556 557 /* bus_machdep.c */ 558 void x86_bus_space_init(void); 559 void x86_bus_space_mallocok(void); 560 561 #endif /* _KERNEL */ 562 563 #if defined(_KERNEL) || defined(_KMEMUSER) 564 #include <machine/psl.h> /* Must be after struct cpu_info declaration */ 565 #endif /* _KERNEL || __KMEMUSER */ 566 567 /* 568 * CTL_MACHDEP definitions. 569 */ 570 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 571 #define CPU_BIOSBASEMEM 2 /* int: bios-reported base mem (K) */ 572 #define CPU_BIOSEXTMEM 3 /* int: bios-reported ext. mem (K) */ 573 /* CPU_NKPDE 4 obsolete: int: number of kernel PDEs */ 574 #define CPU_BOOTED_KERNEL 5 /* string: booted kernel name */ 575 #define CPU_DISKINFO 6 /* struct disklist *: 576 * disk geometry information */ 577 #define CPU_FPU_PRESENT 7 /* int: FPU is present */ 578 #define CPU_OSFXSR 8 /* int: OS uses FXSAVE/FXRSTOR */ 579 #define CPU_SSE 9 /* int: OS/CPU supports SSE */ 580 #define CPU_SSE2 10 /* int: OS/CPU supports SSE2 */ 581 #define CPU_TMLR_MODE 11 /* int: longrun mode 582 * 0: minimum frequency 583 * 1: economy 584 * 2: performance 585 * 3: maximum frequency 586 */ 587 #define CPU_TMLR_FREQUENCY 12 /* int: current frequency */ 588 #define CPU_TMLR_VOLTAGE 13 /* int: current voltage */ 589 #define CPU_TMLR_PERCENTAGE 14 /* int: current clock percentage */ 590 #define CPU_FPU_SAVE 15 /* int: FPU Instructions layout 591 * to use this, CPU_OSFXSR must be true 592 * 0: FSAVE 593 * 1: FXSAVE 594 * 2: XSAVE 595 * 3: XSAVEOPT 596 */ 597 #define CPU_FPU_SAVE_SIZE 16 /* int: FPU Instruction layout size */ 598 #define CPU_XSAVE_FEATURES 17 /* quad: XSAVE features */ 599 600 /* 601 * Structure for CPU_DISKINFO sysctl call. 602 * XXX this should be somewhere else. 603 */ 604 #define MAX_BIOSDISKS 16 605 606 struct disklist { 607 int dl_nbiosdisks; /* number of bios disks */ 608 int dl_unused; 609 struct biosdisk_info { 610 int bi_dev; /* BIOS device # (0x80 ..) */ 611 int bi_cyl; /* cylinders on disk */ 612 int bi_head; /* heads per track */ 613 int bi_sec; /* sectors per track */ 614 uint64_t bi_lbasecs; /* total sec. (iff ext13) */ 615 #define BIFLAG_INVALID 0x01 616 #define BIFLAG_EXTINT13 0x02 617 int bi_flags; 618 int bi_unused; 619 } dl_biosdisks[MAX_BIOSDISKS]; 620 621 int dl_nnativedisks; /* number of native disks */ 622 struct nativedisk_info { 623 char ni_devname[16]; /* native device name */ 624 int ni_nmatches; /* # of matches w/ BIOS */ 625 int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */ 626 } dl_nativedisks[1]; /* actually longer */ 627 }; 628 #endif /* !_X86_CPU_H_ */ 629
Indexes created Mon Sep 22 21:09:42 GMT 2025