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cpu.h revision 1.130
      1 /*	$NetBSD: cpu.h,v 1.130 2021/02/19 02:15:24 christos Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1990 The Regents of the University of California.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to Berkeley by
      8  * William Jolitz.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. Neither the name of the University nor the names of its contributors
     19  *    may be used to endorse or promote products derived from this software
     20  *    without specific prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  *
     34  *	@(#)cpu.h	5.4 (Berkeley) 5/9/91
     35  */
     36 
     37 #ifndef _X86_CPU_H_
     38 #define _X86_CPU_H_
     39 
     40 #if defined(_KERNEL) || defined(_STANDALONE)
     41 #include <sys/types.h>
     42 #else
     43 #include <stdint.h>
     44 #include <stdbool.h>
     45 #endif /* _KERNEL || _STANDALONE */
     46 
     47 #if defined(_KERNEL) || defined(_KMEMUSER)
     48 #if defined(_KERNEL_OPT)
     49 #include "opt_xen.h"
     50 #include "opt_svs.h"
     51 #endif
     52 
     53 /*
     54  * Definitions unique to x86 cpu support.
     55  */
     56 #include <machine/frame.h>
     57 #include <machine/pte.h>
     58 #include <machine/segments.h>
     59 #include <machine/tss.h>
     60 #include <machine/intrdefs.h>
     61 
     62 #include <x86/cacheinfo.h>
     63 
     64 #include <sys/cpu_data.h>
     65 #include <sys/evcnt.h>
     66 #include <sys/device_if.h> /* for device_t */
     67 
     68 #ifdef XEN
     69 #include <xen/include/public/xen.h>
     70 #include <xen/include/public/event_channel.h>
     71 #include <sys/mutex.h>
     72 #endif /* XEN */
     73 
     74 struct intrsource;
     75 struct pmap;
     76 struct kcpuset;
     77 
     78 #ifdef __x86_64__
     79 #define	i386tss	x86_64_tss
     80 #endif
     81 
     82 #define	NIOPORTS	1024		/* # of ports we allow to be mapped */
     83 #define	IOMAPSIZE	(NIOPORTS / 8)	/* I/O bitmap size in bytes */
     84 
     85 struct cpu_tss {
     86 #ifdef i386
     87 	struct i386tss dblflt_tss;
     88 	struct i386tss ddbipi_tss;
     89 #endif
     90 	struct i386tss tss;
     91 	uint8_t iomap[IOMAPSIZE];
     92 } __packed;
     93 
     94 /*
     95  * Arguments to hardclock, softclock and statclock
     96  * encapsulate the previous machine state in an opaque
     97  * clockframe; for now, use generic intrframe.
     98  */
     99 struct clockframe {
    100 	struct intrframe cf_if;
    101 };
    102 
    103 struct idt_vec {
    104 	void *iv_idt;
    105 	void *iv_idt_pentium;
    106 	char iv_allocmap[NIDT];
    107 };
    108 
    109 /*
    110  * a bunch of this belongs in cpuvar.h; move it later..
    111  */
    112 
    113 struct cpu_info {
    114 	struct cpu_data ci_data;	/* MI per-cpu data */
    115 	device_t ci_dev;		/* pointer to our device */
    116 	struct cpu_info *ci_self;	/* self-pointer */
    117 
    118 	/*
    119 	 * Private members.
    120 	 */
    121 	struct pmap *ci_pmap;		/* current pmap */
    122 	int ci_want_pmapload;		/* pmap_load() is needed */
    123 	volatile int ci_tlbstate;	/* one of TLBSTATE_ states. see below */
    124 #define	TLBSTATE_VALID	0	/* all user tlbs are valid */
    125 #define	TLBSTATE_LAZY	1	/* tlbs are valid but won't be kept uptodate */
    126 #define	TLBSTATE_STALE	2	/* we might have stale user tlbs */
    127 	int ci_curldt;		/* current LDT descriptor */
    128 	int ci_nintrhand;	/* number of H/W interrupt handlers */
    129 	uint64_t ci_scratch;
    130 	uintptr_t ci_pmap_data[128 / sizeof(uintptr_t)];
    131 	struct kcpuset *ci_tlb_cpuset;
    132 	struct idt_vec ci_idtvec;
    133 
    134 	int ci_kfpu_spl;
    135 
    136 	struct intrsource *ci_isources[MAX_INTR_SOURCES];
    137 
    138 	volatile int	ci_mtx_count;	/* Negative count of spin mutexes */
    139 	volatile int	ci_mtx_oldspl;	/* Old SPL at this ci_idepth */
    140 
    141 	/* The following must be aligned for cmpxchg8b. */
    142 	struct {
    143 		uint32_t	ipending;
    144 		int		ilevel;
    145 		uint32_t	imasked;
    146 	} ci_istate __aligned(8);
    147 #define ci_ipending	ci_istate.ipending
    148 #define	ci_ilevel	ci_istate.ilevel
    149 #define	ci_imasked	ci_istate.imasked
    150 	int		ci_idepth;
    151 	void *		ci_intrstack;
    152 	uint32_t	ci_imask[NIPL];
    153 	uint32_t	ci_iunmask[NIPL];
    154 
    155 	uint32_t	ci_signature;	/* X86 cpuid type (cpuid.1.%eax) */
    156 	uint32_t	ci_vendor[4];	/* vendor string */
    157 	uint32_t	ci_max_cpuid;	/* cpuid.0:%eax */
    158 	uint32_t	ci_max_ext_cpuid; /* cpuid.80000000:%eax */
    159 	volatile uint32_t	ci_lapic_counter;
    160 
    161 	uint32_t	ci_feat_val[8]; /* X86 CPUID feature bits */
    162 			/* [0] basic features cpuid.1:%edx
    163 			 * [1] basic features cpuid.1:%ecx (CPUID2_xxx bits)
    164 			 * [2] extended features cpuid:80000001:%edx
    165 			 * [3] extended features cpuid:80000001:%ecx
    166 			 * [4] VIA padlock features
    167 			 * [5] structured extended features cpuid.7:%ebx
    168 			 * [6] structured extended features cpuid.7:%ecx
    169 			 * [7] structured extended features cpuid.7:%edx
    170 			 */
    171 
    172 	const struct cpu_functions *ci_func;  /* start/stop functions */
    173 	struct trapframe *ci_ddb_regs;
    174 
    175 	u_int ci_cflush_lsize;	/* CLFLUSH insn line size */
    176 	struct x86_cache_info ci_cinfo[CAI_COUNT];
    177 
    178 	device_t	ci_frequency;	/* Frequency scaling technology */
    179 	device_t	ci_padlock;	/* VIA PadLock private storage */
    180 	device_t	ci_temperature;	/* Intel coretemp(4) or equivalent */
    181 	device_t	ci_vm;		/* Virtual machine guest driver */
    182 
    183 	/*
    184 	 * Segmentation-related data.
    185 	 */
    186 	union descriptor *ci_gdt;
    187 	struct cpu_tss	*ci_tss;	/* Per-cpu TSSes; shared among LWPs */
    188 	int ci_tss_sel;			/* TSS selector of this cpu */
    189 
    190 	/*
    191 	 * The following two are actually region_descriptors,
    192 	 * but that would pollute the namespace.
    193 	 */
    194 	uintptr_t	ci_suspend_gdt;
    195 	uint16_t	ci_suspend_gdt_padding;
    196 	uintptr_t	ci_suspend_idt;
    197 	uint16_t	ci_suspend_idt_padding;
    198 
    199 	uint16_t	ci_suspend_tr;
    200 	uint16_t	ci_suspend_ldt;
    201 	uintptr_t	ci_suspend_fs;
    202 	uintptr_t	ci_suspend_gs;
    203 	uintptr_t	ci_suspend_kgs;
    204 	uintptr_t	ci_suspend_efer;
    205 	uintptr_t	ci_suspend_reg[12];
    206 	uintptr_t	ci_suspend_cr0;
    207 	uintptr_t	ci_suspend_cr2;
    208 	uintptr_t	ci_suspend_cr3;
    209 	uintptr_t	ci_suspend_cr4;
    210 	uintptr_t	ci_suspend_cr8;
    211 
    212 	/*
    213 	 * The following must be in their own cache line, as they are
    214 	 * stored to regularly by remote CPUs; when they were mixed with
    215 	 * other fields we observed frequent cache misses.
    216 	 */
    217 	int		ci_want_resched __aligned(64);
    218 	uint32_t	ci_ipis; /* interprocessor interrupts pending */
    219 
    220 	/*
    221 	 * These are largely static, and will be frequently fetched by other
    222 	 * CPUs.  For that reason they get their own cache line, too.
    223 	 */
    224 	uint32_t 	ci_flags __aligned(64);/* general flags */
    225 	uint32_t 	ci_acpiid;	/* our ACPI/MADT ID */
    226 	uint32_t 	ci_initapicid;	/* our initial APIC ID */
    227 	uint32_t 	ci_vcpuid;	/* our CPU id for hypervisor */
    228 	cpuid_t		ci_cpuid;	/* our CPU ID */
    229 	struct cpu_info	*ci_next;	/* next cpu */
    230 
    231 	/*
    232 	 * This is stored frequently, and is fetched by remote CPUs.
    233 	 */
    234 	struct lwp	*ci_curlwp __aligned(64);/* general flags */
    235 	struct lwp	*ci_onproc;	/* current user LWP / kthread */
    236 
    237 	/* Here ends the cachline-aligned sections. */
    238 	int		ci_padout __aligned(64);
    239 
    240 #ifndef __HAVE_DIRECT_MAP
    241 #define VPAGE_SRC 0
    242 #define VPAGE_DST 1
    243 #define VPAGE_ZER 2
    244 #define VPAGE_PTP 3
    245 #define VPAGE_MAX 4
    246 	vaddr_t		vpage[VPAGE_MAX];
    247 	pt_entry_t	*vpage_pte[VPAGE_MAX];
    248 #endif
    249 
    250 #ifdef PAE
    251 	uint32_t	ci_pae_l3_pdirpa; /* PA of L3 PD */
    252 	pd_entry_t *	ci_pae_l3_pdir; /* VA pointer to L3 PD */
    253 #endif
    254 
    255 #ifdef SVS
    256 	pd_entry_t *	ci_svs_updir;
    257 	paddr_t		ci_svs_updirpa;
    258 	int		ci_svs_ldt_sel;
    259 	kmutex_t	ci_svs_mtx;
    260 	pd_entry_t *	ci_svs_rsp0_pte;
    261 	vaddr_t		ci_svs_rsp0;
    262 	vaddr_t		ci_svs_ursp0;
    263 	vaddr_t		ci_svs_krsp0;
    264 	vaddr_t		ci_svs_utls;
    265 #endif
    266 
    267 #ifndef XENPV
    268 	struct evcnt ci_ipi_events[X86_NIPI];
    269 #else
    270 	struct evcnt ci_ipi_events[XEN_NIPIS];
    271 #endif
    272 #ifdef XEN
    273 	volatile struct vcpu_info *ci_vcpu; /* for XEN */
    274 	u_long ci_evtmask[NR_EVENT_CHANNELS]; /* events allowed on this CPU */
    275 	evtchn_port_t ci_ipi_evtchn;
    276 #if defined(XENPV)
    277 #if defined(PAE) || defined(__x86_64__)
    278 	/* Currently active user PGD (can't use rcr3() with Xen) */
    279 	pd_entry_t *	ci_kpm_pdir;	/* per-cpu PMD (va) */
    280 	paddr_t		ci_kpm_pdirpa;  /* per-cpu PMD (pa) */
    281 	kmutex_t	ci_kpm_mtx;
    282 #endif /* defined(PAE) || defined(__x86_64__) */
    283 
    284 #if defined(__x86_64__)
    285 	/* per-cpu version of normal_pdes */
    286 	pd_entry_t *	ci_normal_pdes[3]; /* Ok to hardcode. only for x86_64 && XENPV */
    287 	paddr_t		ci_xen_current_user_pgd;
    288 #endif	/* defined(__x86_64__) */
    289 
    290 	size_t		ci_xpq_idx;
    291 #endif /* XENPV */
    292 
    293 	/* Xen raw system time at which we last ran hardclock.  */
    294 	uint64_t	ci_xen_hardclock_systime_ns;
    295 
    296 	/*
    297 	 * Last TSC-adjusted local Xen system time we observed.  Used
    298 	 * to detect whether the Xen clock has gone backwards.
    299 	 */
    300 	uint64_t	ci_xen_last_systime_ns;
    301 
    302 	/*
    303 	 * Distance in nanoseconds from the local view of system time
    304 	 * to the global view of system time, if the local time is
    305 	 * behind the global time.
    306 	 */
    307 	uint64_t	ci_xen_systime_ns_skew;
    308 
    309 	/*
    310 	 * Clockframe for timer interrupt handler.
    311 	 * Saved at entry via event callback.
    312 	 */
    313 	vaddr_t ci_xen_clockf_pc; /* RIP at last event interrupt */
    314 	bool ci_xen_clockf_usermode; /* Was the guest in usermode ? */
    315 
    316 	/* Event counters for various pathologies that might happen.  */
    317 	struct evcnt	ci_xen_cpu_tsc_backwards_evcnt;
    318 	struct evcnt	ci_xen_tsc_delta_negative_evcnt;
    319 	struct evcnt	ci_xen_raw_systime_wraparound_evcnt;
    320 	struct evcnt	ci_xen_raw_systime_backwards_evcnt;
    321 	struct evcnt	ci_xen_systime_backwards_hardclock_evcnt;
    322 	struct evcnt	ci_xen_missed_hardclock_evcnt;
    323 #endif	/* XEN */
    324 };
    325 
    326 #if defined(XEN) && !defined(XENPV)
    327 	__CTASSERT(XEN_NIPIS <= X86_NIPI);
    328 #endif
    329 
    330 /*
    331  * Macros to handle (some) trapframe registers for common x86 code.
    332  */
    333 #ifdef __x86_64__
    334 #define	X86_TF_RAX(tf)		tf->tf_rax
    335 #define	X86_TF_RDX(tf)		tf->tf_rdx
    336 #define	X86_TF_RSP(tf)		tf->tf_rsp
    337 #define	X86_TF_RIP(tf)		tf->tf_rip
    338 #define	X86_TF_RFLAGS(tf)	tf->tf_rflags
    339 #else
    340 #define	X86_TF_RAX(tf)		tf->tf_eax
    341 #define	X86_TF_RDX(tf)		tf->tf_edx
    342 #define	X86_TF_RSP(tf)		tf->tf_esp
    343 #define	X86_TF_RIP(tf)		tf->tf_eip
    344 #define	X86_TF_RFLAGS(tf)	tf->tf_eflags
    345 #endif
    346 
    347 /*
    348  * Processor flag notes: The "primary" CPU has certain MI-defined
    349  * roles (mostly relating to hardclock handling); we distinguish
    350  * between the processor which booted us, and the processor currently
    351  * holding the "primary" role just to give us the flexibility later to
    352  * change primaries should we be sufficiently twisted.
    353  */
    354 
    355 #define	CPUF_BSP	0x0001		/* CPU is the original BSP */
    356 #define	CPUF_AP		0x0002		/* CPU is an AP */
    357 #define	CPUF_SP		0x0004		/* CPU is only processor */
    358 #define	CPUF_PRIMARY	0x0008		/* CPU is active primary processor */
    359 
    360 #define	CPUF_SYNCTSC	0x0800		/* Synchronize TSC */
    361 #define	CPUF_PRESENT	0x1000		/* CPU is present */
    362 #define	CPUF_RUNNING	0x2000		/* CPU is running */
    363 #define	CPUF_PAUSE	0x4000		/* CPU is paused in DDB */
    364 #define	CPUF_GO		0x8000		/* CPU should start running */
    365 
    366 #endif /* _KERNEL || __KMEMUSER */
    367 
    368 #ifdef _KERNEL
    369 /*
    370  * We statically allocate the CPU info for the primary CPU (or,
    371  * the only CPU on uniprocessors), and the primary CPU is the
    372  * first CPU on the CPU info list.
    373  */
    374 extern struct cpu_info cpu_info_primary;
    375 extern struct cpu_info *cpu_info_list;
    376 
    377 #define	CPU_INFO_ITERATOR		int __unused
    378 #define	CPU_INFO_FOREACH(cii, ci)	ci = cpu_info_list; \
    379 					ci != NULL; ci = ci->ci_next
    380 
    381 #define CPU_STARTUP(_ci, _target)	((_ci)->ci_func->start(_ci, _target))
    382 #define CPU_STOP(_ci)	        	((_ci)->ci_func->stop(_ci))
    383 #define CPU_START_CLEANUP(_ci)		((_ci)->ci_func->cleanup(_ci))
    384 
    385 #if !defined(__GNUC__) || defined(_MODULE)
    386 /* For non-GCC and modules */
    387 struct cpu_info	*x86_curcpu(void);
    388 # ifdef __GNUC__
    389 lwp_t	*x86_curlwp(void) __attribute__ ((const));
    390 # else
    391 lwp_t   *x86_curlwp(void);
    392 # endif
    393 #endif
    394 
    395 #define cpu_number() 		(cpu_index(curcpu()))
    396 
    397 #define CPU_IS_PRIMARY(ci)	((ci)->ci_flags & CPUF_PRIMARY)
    398 
    399 #define aston(l)		((l)->l_md.md_astpending = 1)
    400 
    401 void cpu_boot_secondary_processors(void);
    402 void cpu_init_idle_lwps(void);
    403 void cpu_init_msrs(struct cpu_info *, bool);
    404 void cpu_load_pmap(struct pmap *, struct pmap *);
    405 void cpu_broadcast_halt(void);
    406 void cpu_kick(struct cpu_info *);
    407 
    408 void cpu_pcpuarea_init(struct cpu_info *);
    409 void cpu_svs_init(struct cpu_info *);
    410 void cpu_speculation_init(struct cpu_info *);
    411 
    412 #define	curcpu()		x86_curcpu()
    413 #define	curlwp			x86_curlwp()
    414 #define	curpcb			((struct pcb *)lwp_getpcb(curlwp))
    415 
    416 /*
    417  * Give a profiling tick to the current process when the user profiling
    418  * buffer pages are invalid.  On the i386, request an ast to send us
    419  * through trap(), marking the proc as needing a profiling tick.
    420  */
    421 extern void	cpu_need_proftick(struct lwp *l);
    422 
    423 /*
    424  * Notify the LWP l that it has a signal pending, process as soon as
    425  * possible.
    426  */
    427 extern void	cpu_signotify(struct lwp *);
    428 
    429 /*
    430  * We need a machine-independent name for this.
    431  */
    432 extern void (*delay_func)(unsigned int);
    433 struct timeval;
    434 
    435 #ifndef __HIDE_DELAY
    436 #define	DELAY(x)		(*delay_func)(x)
    437 #define delay(x)		(*delay_func)(x)
    438 #endif
    439 
    440 extern int biosbasemem;
    441 extern int biosextmem;
    442 extern int cputype;
    443 extern int cpuid_level;
    444 extern int cpu_class;
    445 extern char cpu_brand_string[];
    446 extern int use_pae;
    447 
    448 #ifdef __i386__
    449 #define	i386_fpu_present	1
    450 int npx586bug1(int, int);
    451 extern int i386_fpu_fdivbug;
    452 extern int i386_use_fxsave;
    453 extern int i386_has_sse;
    454 extern int i386_has_sse2;
    455 #else
    456 #define	i386_fpu_present	1
    457 #define	i386_fpu_fdivbug	0
    458 #define	i386_use_fxsave		1
    459 #define	i386_has_sse		1
    460 #define	i386_has_sse2		1
    461 #endif
    462 
    463 extern int x86_fpu_save;
    464 #define	FPU_SAVE_FSAVE		0
    465 #define	FPU_SAVE_FXSAVE		1
    466 #define	FPU_SAVE_XSAVE		2
    467 #define	FPU_SAVE_XSAVEOPT	3
    468 extern unsigned int x86_fpu_save_size;
    469 extern uint64_t x86_xsave_features;
    470 extern size_t x86_xsave_offsets[];
    471 extern size_t x86_xsave_sizes[];
    472 extern uint32_t x86_fpu_mxcsr_mask;
    473 
    474 extern void (*x86_cpu_idle)(void);
    475 #define	cpu_idle() (*x86_cpu_idle)()
    476 
    477 /* machdep.c */
    478 #ifdef i386
    479 void	cpu_set_tss_gates(struct cpu_info *);
    480 #endif
    481 void	cpu_reset(void);
    482 
    483 /* longrun.c */
    484 u_int 	tmx86_get_longrun_mode(void);
    485 void 	tmx86_get_longrun_status(u_int *, u_int *, u_int *);
    486 void 	tmx86_init_longrun(void);
    487 
    488 /* identcpu.c */
    489 void 	cpu_probe(struct cpu_info *);
    490 void	cpu_identify(struct cpu_info *);
    491 void	identify_hypervisor(void);
    492 
    493 /* identcpu_subr.c */
    494 uint64_t cpu_tsc_freq_cpuid(struct cpu_info *);
    495 
    496 typedef enum vm_guest {
    497 	VM_GUEST_NO = 0,
    498 	VM_GUEST_VM,
    499 	VM_GUEST_XENPV,
    500 	VM_GUEST_XENPVH,
    501 	VM_GUEST_XENHVM,
    502 	VM_GUEST_XENPVHVM,
    503 	VM_GUEST_HV,
    504 	VM_GUEST_VMWARE,
    505 	VM_GUEST_KVM,
    506 	VM_GUEST_VIRTUALBOX,
    507 	VM_LAST
    508 } vm_guest_t;
    509 extern vm_guest_t vm_guest;
    510 
    511 static __inline bool __unused
    512 vm_guest_is_xenpv(void)
    513 {
    514 	switch(vm_guest) {
    515 	case VM_GUEST_XENPV:
    516 	case VM_GUEST_XENPVH:
    517 	case VM_GUEST_XENPVHVM:
    518 		return true;
    519 	default:
    520 		return false;
    521 	}
    522 }
    523 
    524 static __inline bool __unused
    525 vm_guest_is_xenpvh_or_pvhvm(void)
    526 {
    527 	switch(vm_guest) {
    528 	case VM_GUEST_XENPVH:
    529 	case VM_GUEST_XENPVHVM:
    530 		return true;
    531 	default:
    532 		return false;
    533 	}
    534 }
    535 
    536 /* cpu_topology.c */
    537 void	x86_cpu_topology(struct cpu_info *);
    538 
    539 /* locore.s */
    540 struct region_descriptor;
    541 void	lgdt(struct region_descriptor *);
    542 #ifdef XENPV
    543 void	lgdt_finish(void);
    544 #endif
    545 
    546 struct pcb;
    547 void	savectx(struct pcb *);
    548 void	lwp_trampoline(void);
    549 #ifdef XEN
    550 void	xen_startrtclock(void);
    551 void	xen_delay(unsigned int);
    552 void	xen_initclocks(void);
    553 void	xen_cpu_initclocks(void);
    554 void	xen_suspendclocks(struct cpu_info *);
    555 void	xen_resumeclocks(struct cpu_info *);
    556 #endif /* XEN */
    557 /* clock.c */
    558 void	initrtclock(u_long);
    559 void	startrtclock(void);
    560 void	i8254_delay(unsigned int);
    561 void	i8254_microtime(struct timeval *);
    562 void	i8254_initclocks(void);
    563 unsigned int gettick(void);
    564 extern void (*x86_delay)(unsigned int);
    565 
    566 /* cpu.c */
    567 void	cpu_probe_features(struct cpu_info *);
    568 int	x86_cpu_is_lcall(const void *);
    569 
    570 /* vm_machdep.c */
    571 void	cpu_proc_fork(struct proc *, struct proc *);
    572 paddr_t	kvtop(void *);
    573 
    574 /* isa_machdep.c */
    575 void	isa_defaultirq(void);
    576 int	isa_nmi(void);
    577 
    578 /* consinit.c */
    579 void kgdb_port_init(void);
    580 
    581 /* bus_machdep.c */
    582 void x86_bus_space_init(void);
    583 void x86_bus_space_mallocok(void);
    584 
    585 #endif /* _KERNEL */
    586 
    587 #if defined(_KERNEL) || defined(_KMEMUSER)
    588 #include <machine/psl.h>	/* Must be after struct cpu_info declaration */
    589 #endif /* _KERNEL || __KMEMUSER */
    590 
    591 /*
    592  * CTL_MACHDEP definitions.
    593  */
    594 #define	CPU_CONSDEV		1	/* dev_t: console terminal device */
    595 #define	CPU_BIOSBASEMEM		2	/* int: bios-reported base mem (K) */
    596 #define	CPU_BIOSEXTMEM		3	/* int: bios-reported ext. mem (K) */
    597 /* 	CPU_NKPDE		4	obsolete: int: number of kernel PDEs */
    598 #define	CPU_BOOTED_KERNEL	5	/* string: booted kernel name */
    599 #define CPU_DISKINFO		6	/* struct disklist *:
    600 					 * disk geometry information */
    601 #define CPU_FPU_PRESENT		7	/* int: FPU is present */
    602 #define	CPU_OSFXSR		8	/* int: OS uses FXSAVE/FXRSTOR */
    603 #define	CPU_SSE			9	/* int: OS/CPU supports SSE */
    604 #define	CPU_SSE2		10	/* int: OS/CPU supports SSE2 */
    605 #define	CPU_TMLR_MODE		11	/* int: longrun mode
    606 					 * 0: minimum frequency
    607 					 * 1: economy
    608 					 * 2: performance
    609 					 * 3: maximum frequency
    610 					 */
    611 #define	CPU_TMLR_FREQUENCY	12	/* int: current frequency */
    612 #define	CPU_TMLR_VOLTAGE	13	/* int: current voltage */
    613 #define	CPU_TMLR_PERCENTAGE	14	/* int: current clock percentage */
    614 #define	CPU_FPU_SAVE		15	/* int: FPU Instructions layout
    615 					 * to use this, CPU_OSFXSR must be true
    616 					 * 0: FSAVE
    617 					 * 1: FXSAVE
    618 					 * 2: XSAVE
    619 					 * 3: XSAVEOPT
    620 					 */
    621 #define	CPU_FPU_SAVE_SIZE	16	/* int: FPU Instruction layout size */
    622 #define	CPU_XSAVE_FEATURES	17	/* quad: XSAVE features */
    623 
    624 /*
    625  * Structure for CPU_DISKINFO sysctl call.
    626  * XXX this should be somewhere else.
    627  */
    628 #define MAX_BIOSDISKS	16
    629 
    630 struct disklist {
    631 	int dl_nbiosdisks;			   /* number of bios disks */
    632 	int dl_unused;
    633 	struct biosdisk_info {
    634 		int bi_dev;			   /* BIOS device # (0x80 ..) */
    635 		int bi_cyl;			   /* cylinders on disk */
    636 		int bi_head;			   /* heads per track */
    637 		int bi_sec;			   /* sectors per track */
    638 		uint64_t bi_lbasecs;		   /* total sec. (iff ext13) */
    639 #define BIFLAG_INVALID		0x01
    640 #define BIFLAG_EXTINT13		0x02
    641 		int bi_flags;
    642 		int bi_unused;
    643 	} dl_biosdisks[MAX_BIOSDISKS];
    644 
    645 	int dl_nnativedisks;			   /* number of native disks */
    646 	struct nativedisk_info {
    647 		char ni_devname[16];		   /* native device name */
    648 		int ni_nmatches; 		   /* # of matches w/ BIOS */
    649 		int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */
    650 	} dl_nativedisks[1];			   /* actually longer */
    651 };
    652 #endif /* !_X86_CPU_H_ */
    653