cpu.h revision 1.15
1 /* $NetBSD: cpu.h,v 1.15 2009/04/16 15:34:23 rmind Exp $ */ 2 3 /*- 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 35 */ 36 37 #ifndef _X86_CPU_H_ 38 #define _X86_CPU_H_ 39 40 #if defined(_KERNEL) || defined(_KMEMUSER) 41 #if defined(_KERNEL_OPT) 42 #include "opt_xen.h" 43 #ifdef i386 44 #include "opt_user_ldt.h" 45 #include "opt_vm86.h" 46 #endif 47 #endif 48 49 /* 50 * Definitions unique to x86 cpu support. 51 */ 52 #include <machine/frame.h> 53 #include <machine/segments.h> 54 #include <machine/tss.h> 55 #include <machine/intrdefs.h> 56 57 #include <x86/cacheinfo.h> 58 #include <x86/via_padlock.h> 59 60 #include <sys/cpu_data.h> 61 #include <sys/evcnt.h> 62 63 struct intrsource; 64 struct pmap; 65 struct device; 66 67 #ifdef __x86_64__ 68 #define i386tss x86_64_tss 69 #endif 70 71 #define NIOPORTS 1024 /* # of ports we allow to be mapped */ 72 #define IOMAPSIZE (NIOPORTS / 8) /* I/O bitmap size in bytes */ 73 74 /* 75 * a bunch of this belongs in cpuvar.h; move it later.. 76 */ 77 78 struct cpu_info { 79 struct device *ci_dev; /* pointer to our device */ 80 struct cpu_info *ci_self; /* self-pointer */ 81 volatile struct vcpu_info *ci_vcpu; /* for XEN */ 82 void *ci_tlog_base; /* Trap log base */ 83 int32_t ci_tlog_offset; /* Trap log current offset */ 84 85 /* 86 * Will be accessed by other CPUs. 87 */ 88 struct cpu_info *ci_next; /* next cpu */ 89 struct lwp *ci_curlwp; /* current owner of the processor */ 90 struct pmap_cpu *ci_pmap_cpu; /* per-CPU pmap data */ 91 struct lwp *ci_fpcurlwp; /* current owner of the FPU */ 92 int ci_fpsaving; /* save in progress */ 93 int ci_fpused; /* XEN: FPU was used by curlwp */ 94 cpuid_t ci_cpuid; /* our CPU ID */ 95 int ci_cpumask; /* (1 << CPU ID) */ 96 uint8_t ci_initapicid; /* our intitial APIC ID */ 97 uint8_t ci_packageid; 98 uint8_t ci_coreid; 99 uint8_t ci_smtid; 100 struct cpu_data ci_data; /* MI per-cpu data */ 101 102 /* 103 * Private members. 104 */ 105 struct evcnt ci_tlb_evcnt; /* tlb shootdown counter */ 106 struct pmap *ci_pmap; /* current pmap */ 107 int ci_need_tlbwait; /* need to wait for TLB invalidations */ 108 int ci_want_pmapload; /* pmap_load() is needed */ 109 volatile int ci_tlbstate; /* one of TLBSTATE_ states. see below */ 110 #define TLBSTATE_VALID 0 /* all user tlbs are valid */ 111 #define TLBSTATE_LAZY 1 /* tlbs are valid but won't be kept uptodate */ 112 #define TLBSTATE_STALE 2 /* we might have stale user tlbs */ 113 int ci_curldt; /* current LDT descriptor */ 114 uint64_t ci_scratch; 115 116 #ifdef XEN 117 struct iplsource *ci_isources[NIPL]; 118 #else 119 struct intrsource *ci_isources[MAX_INTR_SOURCES]; 120 #endif 121 volatile int ci_mtx_count; /* Negative count of spin mutexes */ 122 volatile int ci_mtx_oldspl; /* Old SPL at this ci_idepth */ 123 124 /* The following must be aligned for cmpxchg8b. */ 125 struct { 126 uint32_t ipending; 127 int ilevel; 128 } ci_istate __aligned(8); 129 #define ci_ipending ci_istate.ipending 130 #define ci_ilevel ci_istate.ilevel 131 132 int ci_idepth; 133 void * ci_intrstack; 134 uint32_t ci_imask[NIPL]; 135 uint32_t ci_iunmask[NIPL]; 136 137 uint32_t ci_flags; /* flags; see below */ 138 uint32_t ci_ipis; /* interprocessor interrupts pending */ 139 int sc_apic_version; /* local APIC version */ 140 141 uint32_t ci_signature; /* X86 cpuid type */ 142 uint32_t ci_feature_flags;/* X86 %edx CPUID feature bits */ 143 uint32_t ci_feature2_flags;/* X86 %ecx CPUID feature bits */ 144 uint32_t ci_feature3_flags;/* X86 extended %edx feature bits */ 145 uint32_t ci_feature4_flags;/* X86 extended %ecx feature bits */ 146 uint32_t ci_padlock_flags;/* VIA PadLock feature bits */ 147 uint32_t ci_vendor[4]; /* vendor string */ 148 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 149 volatile uint32_t ci_lapic_counter; 150 151 const struct cpu_functions *ci_func; /* start/stop functions */ 152 struct trapframe *ci_ddb_regs; 153 154 u_int ci_cflush_lsize; /* CFLUSH insn line size */ 155 struct x86_cache_info ci_cinfo[CAI_COUNT]; 156 157 union descriptor *ci_gdt; 158 159 #ifdef i386 160 struct i386tss ci_doubleflt_tss; 161 struct i386tss ci_ddbipi_tss; 162 #endif 163 char *ci_doubleflt_stack; 164 char *ci_ddbipi_stack; 165 166 struct evcnt ci_ipi_events[X86_NIPI]; 167 168 struct via_padlock ci_vp; /* VIA PadLock private storage */ 169 170 struct i386tss ci_tss; /* Per-cpu TSS; shared among LWPs */ 171 char ci_iomap[IOMAPSIZE]; /* I/O Bitmap */ 172 int ci_tss_sel; /* TSS selector of this cpu */ 173 174 /* 175 * The following two are actually region_descriptors, 176 * but that would pollute the namespace. 177 */ 178 uintptr_t ci_suspend_gdt; 179 uint16_t ci_suspend_gdt_padding; 180 uintptr_t ci_suspend_idt; 181 uint16_t ci_suspend_idt_padding; 182 183 uint16_t ci_suspend_tr; 184 uint16_t ci_suspend_ldt; 185 uintptr_t ci_suspend_fs; 186 uintptr_t ci_suspend_gs; 187 uintptr_t ci_suspend_kgs; 188 uintptr_t ci_suspend_efer; 189 uintptr_t ci_suspend_reg[12]; 190 uintptr_t ci_suspend_cr0; 191 uintptr_t ci_suspend_cr2; 192 uintptr_t ci_suspend_cr3; 193 uintptr_t ci_suspend_cr4; 194 uintptr_t ci_suspend_cr8; 195 196 /* The following must be in a single cache line. */ 197 int ci_want_resched __aligned(64); 198 int ci_padout __aligned(64); 199 }; 200 201 /* 202 * Macros to handle (some) trapframe registers for common x86 code. 203 */ 204 #ifdef __x86_64__ 205 #define X86_TF_RAX(tf) tf->tf_rax 206 #define X86_TF_RDX(tf) tf->tf_rdx 207 #define X86_TF_RSP(tf) tf->tf_rsp 208 #define X86_TF_RIP(tf) tf->tf_rip 209 #define X86_TF_RFLAGS(tf) tf->tf_rflags 210 #else 211 #define X86_TF_RAX(tf) tf->tf_eax 212 #define X86_TF_RDX(tf) tf->tf_edx 213 #define X86_TF_RSP(tf) tf->tf_esp 214 #define X86_TF_RIP(tf) tf->tf_eip 215 #define X86_TF_RFLAGS(tf) tf->tf_eflags 216 #endif 217 218 /* 219 * Processor flag notes: The "primary" CPU has certain MI-defined 220 * roles (mostly relating to hardclock handling); we distinguish 221 * betwen the processor which booted us, and the processor currently 222 * holding the "primary" role just to give us the flexibility later to 223 * change primaries should we be sufficiently twisted. 224 */ 225 226 #define CPUF_BSP 0x0001 /* CPU is the original BSP */ 227 #define CPUF_AP 0x0002 /* CPU is an AP */ 228 #define CPUF_SP 0x0004 /* CPU is only processor */ 229 #define CPUF_PRIMARY 0x0008 /* CPU is active primary processor */ 230 231 #define CPUF_SYNCTSC 0x0800 /* Synchronize TSC */ 232 #define CPUF_PRESENT 0x1000 /* CPU is present */ 233 #define CPUF_RUNNING 0x2000 /* CPU is running */ 234 #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ 235 #define CPUF_GO 0x8000 /* CPU should start running */ 236 237 /* 238 * We statically allocate the CPU info for the primary CPU (or, 239 * the only CPU on uniprocessors), and the primary CPU is the 240 * first CPU on the CPU info list. 241 */ 242 extern struct cpu_info cpu_info_primary; 243 extern struct cpu_info *cpu_info_list; 244 245 #define CPU_INFO_ITERATOR int 246 #define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = cpu_info_list; \ 247 ci != NULL; ci = ci->ci_next 248 249 #define CPU_STARTUP(_ci, _target) ((_ci)->ci_func->start(_ci, _target)) 250 #define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci)) 251 #define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci)) 252 253 #if !defined(__GNUC__) || defined(_MODULE) 254 /* For non-GCC and modules */ 255 struct cpu_info *x86_curcpu(void); 256 void cpu_set_curpri(int); 257 # ifdef __GNUC__ 258 lwp_t *x86_curlwp(void) __attribute__ ((const)); 259 # else 260 lwp_t *x86_curlwp(void); 261 # endif 262 #endif 263 264 #define cpu_number() (cpu_index(curcpu())) 265 266 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 267 268 #define X86_AST_GENERIC 0x01 269 #define X86_AST_PREEMPT 0x02 270 271 #define aston(l, why) ((l)->l_md.md_astpending |= (why)) 272 #define cpu_did_resched(l) ((l)->l_md.md_astpending &= ~X86_AST_PREEMPT) 273 274 void cpu_boot_secondary_processors(void); 275 void cpu_init_idle_lwps(void); 276 void cpu_init_msrs(struct cpu_info *, bool); 277 278 extern uint32_t cpus_attached; 279 #ifndef XEN 280 #define curcpu() x86_curcpu() 281 #define curlwp x86_curlwp() 282 #else 283 /* XXX initgdt() calls pmap_kenter_pa() which calls splvm() before %fs is set */ 284 #define curcpu() (&cpu_info_primary) 285 #define curlwp curcpu()->ci_curlwp 286 #endif 287 #define curpcb (&curlwp->l_addr->u_pcb) 288 289 /* 290 * Arguments to hardclock, softclock and statclock 291 * encapsulate the previous machine state in an opaque 292 * clockframe; for now, use generic intrframe. 293 */ 294 struct clockframe { 295 struct intrframe cf_if; 296 }; 297 298 /* 299 * Give a profiling tick to the current process when the user profiling 300 * buffer pages are invalid. On the i386, request an ast to send us 301 * through trap(), marking the proc as needing a profiling tick. 302 */ 303 extern void cpu_need_proftick(struct lwp *l); 304 305 /* 306 * Notify the LWP l that it has a signal pending, process as soon as 307 * possible. 308 */ 309 extern void cpu_signotify(struct lwp *); 310 311 /* 312 * We need a machine-independent name for this. 313 */ 314 extern void (*delay_func)(unsigned int); 315 struct timeval; 316 317 #define DELAY(x) (*delay_func)(x) 318 #define delay(x) (*delay_func)(x) 319 320 extern int biosbasemem; 321 extern int biosextmem; 322 extern unsigned int cpu_feature; 323 extern unsigned int cpu_feature2; 324 extern unsigned int cpu_feature_padlock; 325 extern int cpu; 326 extern int cpuid_level; 327 extern int cpu_class; 328 extern char cpu_brand_string[]; 329 330 extern int i386_use_fxsave; 331 extern int i386_has_sse; 332 extern int i386_has_sse2; 333 334 extern void (*x86_cpu_idle)(void); 335 #define cpu_idle() (*x86_cpu_idle)() 336 337 /* machdep.c */ 338 void dumpconf(void); 339 void cpu_reset(void); 340 void i386_proc0_tss_ldt_init(void); 341 void dumpconf(void); 342 void cpu_reset(void); 343 void x86_64_proc0_tss_ldt_init(void); 344 void x86_64_init_pcb_tss_ldt(struct cpu_info *); 345 346 /* longrun.c */ 347 u_int tmx86_get_longrun_mode(void); 348 void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 349 void tmx86_init_longrun(void); 350 351 /* identcpu.c */ 352 void cpu_probe(struct cpu_info *); 353 void cpu_identify(struct cpu_info *); 354 355 /* vm_machdep.c */ 356 void cpu_proc_fork(struct proc *, struct proc *); 357 358 /* locore.s */ 359 struct region_descriptor; 360 void lgdt(struct region_descriptor *); 361 #ifdef XEN 362 void lgdt_finish(void); 363 void i386_switch_context(lwp_t *); 364 #endif 365 366 struct pcb; 367 void savectx(struct pcb *); 368 void lwp_trampoline(void); 369 void child_trampoline(void); 370 #ifdef XEN 371 void startrtclock(void); 372 void xen_delay(unsigned int); 373 void xen_initclocks(void); 374 #else 375 /* clock.c */ 376 void initrtclock(u_long); 377 void startrtclock(void); 378 void i8254_delay(unsigned int); 379 void i8254_microtime(struct timeval *); 380 void i8254_initclocks(void); 381 #endif 382 383 /* cpu.c */ 384 385 void cpu_probe_features(struct cpu_info *); 386 387 /* npx.c */ 388 void npxsave_lwp(struct lwp *, bool); 389 void npxsave_cpu(bool); 390 391 /* vm_machdep.c */ 392 paddr_t kvtop(void *); 393 394 #ifdef USER_LDT 395 /* sys_machdep.h */ 396 int x86_get_ldt(struct lwp *, void *, register_t *); 397 int x86_set_ldt(struct lwp *, void *, register_t *); 398 #endif 399 400 /* isa_machdep.c */ 401 void isa_defaultirq(void); 402 int isa_nmi(void); 403 404 #ifdef VM86 405 /* vm86.c */ 406 void vm86_gpfault(struct lwp *, int); 407 #endif /* VM86 */ 408 409 /* consinit.c */ 410 void kgdb_port_init(void); 411 412 /* bus_machdep.c */ 413 void x86_bus_space_init(void); 414 void x86_bus_space_mallocok(void); 415 416 #include <machine/psl.h> /* Must be after struct cpu_info declaration */ 417 418 #endif /* _KERNEL || __KMEMUSER */ 419 420 #if defined(_KERNEL) || defined(_STANDALONE) 421 #include <sys/types.h> 422 #else 423 #include <stdbool.h> 424 #endif /* _KERNEL || _STANDALONE */ 425 426 /* 427 * CTL_MACHDEP definitions. 428 */ 429 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 430 #define CPU_BIOSBASEMEM 2 /* int: bios-reported base mem (K) */ 431 #define CPU_BIOSEXTMEM 3 /* int: bios-reported ext. mem (K) */ 432 /* CPU_NKPDE 4 obsolete: int: number of kernel PDEs */ 433 #define CPU_BOOTED_KERNEL 5 /* string: booted kernel name */ 434 #define CPU_DISKINFO 6 /* struct disklist *: 435 * disk geometry information */ 436 #define CPU_FPU_PRESENT 7 /* int: FPU is present */ 437 #define CPU_OSFXSR 8 /* int: OS uses FXSAVE/FXRSTOR */ 438 #define CPU_SSE 9 /* int: OS/CPU supports SSE */ 439 #define CPU_SSE2 10 /* int: OS/CPU supports SSE2 */ 440 #define CPU_TMLR_MODE 11 /* int: longrun mode 441 * 0: minimum frequency 442 * 1: economy 443 * 2: performance 444 * 3: maximum frequency 445 */ 446 #define CPU_TMLR_FREQUENCY 12 /* int: current frequency */ 447 #define CPU_TMLR_VOLTAGE 13 /* int: curret voltage */ 448 #define CPU_TMLR_PERCENTAGE 14 /* int: current clock percentage */ 449 #define CPU_MAXID 15 /* number of valid machdep ids */ 450 451 /* 452 * Structure for CPU_DISKINFO sysctl call. 453 * XXX this should be somewhere else. 454 */ 455 #define MAX_BIOSDISKS 16 456 457 struct disklist { 458 int dl_nbiosdisks; /* number of bios disks */ 459 struct biosdisk_info { 460 int bi_dev; /* BIOS device # (0x80 ..) */ 461 int bi_cyl; /* cylinders on disk */ 462 int bi_head; /* heads per track */ 463 int bi_sec; /* sectors per track */ 464 uint64_t bi_lbasecs; /* total sec. (iff ext13) */ 465 #define BIFLAG_INVALID 0x01 466 #define BIFLAG_EXTINT13 0x02 467 int bi_flags; 468 } dl_biosdisks[MAX_BIOSDISKS]; 469 470 int dl_nnativedisks; /* number of native disks */ 471 struct nativedisk_info { 472 char ni_devname[16]; /* native device name */ 473 int ni_nmatches; /* # of matches w/ BIOS */ 474 int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */ 475 } dl_nativedisks[1]; /* actually longer */ 476 }; 477 #endif /* !_X86_CPU_H_ */ 478
Indexes created Wed Sep 24 22:09:59 GMT 2025