cpu.h revision 1.21
1 /* $NetBSD: cpu.h,v 1.21 2010/04/18 23:47:51 jym Exp $ */ 2 3 /*- 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 35 */ 36 37 #ifndef _X86_CPU_H_ 38 #define _X86_CPU_H_ 39 40 #if defined(_KERNEL) || defined(_KMEMUSER) 41 #if defined(_KERNEL_OPT) 42 #include "opt_xen.h" 43 #ifdef i386 44 #include "opt_user_ldt.h" 45 #include "opt_vm86.h" 46 #endif 47 #endif 48 49 /* 50 * Definitions unique to x86 cpu support. 51 */ 52 #include <machine/frame.h> 53 #include <machine/segments.h> 54 #include <machine/tss.h> 55 #include <machine/intrdefs.h> 56 57 #include <x86/cacheinfo.h> 58 #include <x86/via_padlock.h> 59 60 #include <sys/cpu_data.h> 61 #include <sys/evcnt.h> 62 #include <sys/device_if.h> /* for device_t */ 63 64 struct intrsource; 65 struct pmap; 66 struct device; 67 68 #ifdef __x86_64__ 69 #define i386tss x86_64_tss 70 #endif 71 72 #define NIOPORTS 1024 /* # of ports we allow to be mapped */ 73 #define IOMAPSIZE (NIOPORTS / 8) /* I/O bitmap size in bytes */ 74 75 /* 76 * a bunch of this belongs in cpuvar.h; move it later.. 77 */ 78 79 struct cpu_info { 80 device_t ci_dev; /* pointer to our device */ 81 struct cpu_info *ci_self; /* self-pointer */ 82 volatile struct vcpu_info *ci_vcpu; /* for XEN */ 83 void *ci_tlog_base; /* Trap log base */ 84 int32_t ci_tlog_offset; /* Trap log current offset */ 85 86 /* 87 * Will be accessed by other CPUs. 88 */ 89 struct cpu_info *ci_next; /* next cpu */ 90 struct lwp *ci_curlwp; /* current owner of the processor */ 91 struct pmap_cpu *ci_pmap_cpu; /* per-CPU pmap data */ 92 struct lwp *ci_fpcurlwp; /* current owner of the FPU */ 93 int ci_fpsaving; /* save in progress */ 94 int ci_fpused; /* XEN: FPU was used by curlwp */ 95 cpuid_t ci_cpuid; /* our CPU ID */ 96 int ci_cpumask; /* (1 << CPU ID) */ 97 uint32_t ci_initapicid; /* our intitial APIC ID */ 98 uint8_t ci_packageid; 99 uint8_t ci_coreid; 100 uint8_t ci_smtid; 101 struct cpu_data ci_data; /* MI per-cpu data */ 102 103 /* 104 * Private members. 105 */ 106 struct evcnt ci_tlb_evcnt; /* tlb shootdown counter */ 107 struct pmap *ci_pmap; /* current pmap */ 108 int ci_need_tlbwait; /* need to wait for TLB invalidations */ 109 int ci_want_pmapload; /* pmap_load() is needed */ 110 volatile int ci_tlbstate; /* one of TLBSTATE_ states. see below */ 111 #define TLBSTATE_VALID 0 /* all user tlbs are valid */ 112 #define TLBSTATE_LAZY 1 /* tlbs are valid but won't be kept uptodate */ 113 #define TLBSTATE_STALE 2 /* we might have stale user tlbs */ 114 int ci_curldt; /* current LDT descriptor */ 115 int ci_nintrhand; /* number of H/W interrupt handlers */ 116 uint64_t ci_scratch; 117 118 #ifdef XEN 119 struct iplsource *ci_isources[NIPL]; 120 #else 121 struct intrsource *ci_isources[MAX_INTR_SOURCES]; 122 #endif 123 volatile int ci_mtx_count; /* Negative count of spin mutexes */ 124 volatile int ci_mtx_oldspl; /* Old SPL at this ci_idepth */ 125 126 /* The following must be aligned for cmpxchg8b. */ 127 struct { 128 uint32_t ipending; 129 int ilevel; 130 } ci_istate __aligned(8); 131 #define ci_ipending ci_istate.ipending 132 #define ci_ilevel ci_istate.ilevel 133 134 int ci_idepth; 135 void * ci_intrstack; 136 uint32_t ci_imask[NIPL]; 137 uint32_t ci_iunmask[NIPL]; 138 139 uint32_t ci_flags; /* flags; see below */ 140 uint32_t ci_ipis; /* interprocessor interrupts pending */ 141 uint32_t sc_apic_version; /* local APIC version */ 142 143 uint32_t ci_signature; /* X86 cpuid type */ 144 uint32_t ci_vendor[4]; /* vendor string */ 145 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 146 volatile uint32_t ci_lapic_counter; 147 148 uint32_t ci_feat_val[5]; /* X86 CPUID feature bits 149 * [0] basic features %edx 150 * [1] basic features %ecx 151 * [2] extended features %edx 152 * [3] extended features %ecx 153 * [4] VIA padlock features 154 */ 155 156 const struct cpu_functions *ci_func; /* start/stop functions */ 157 struct trapframe *ci_ddb_regs; 158 159 u_int ci_cflush_lsize; /* CFLUSH insn line size */ 160 struct x86_cache_info ci_cinfo[CAI_COUNT]; 161 162 union descriptor *ci_gdt; 163 164 #ifdef i386 165 struct i386tss ci_doubleflt_tss; 166 struct i386tss ci_ddbipi_tss; 167 #endif 168 char *ci_doubleflt_stack; 169 char *ci_ddbipi_stack; 170 171 struct evcnt ci_ipi_events[X86_NIPI]; 172 173 struct via_padlock ci_vp; /* VIA PadLock private storage */ 174 175 struct i386tss ci_tss; /* Per-cpu TSS; shared among LWPs */ 176 char ci_iomap[IOMAPSIZE]; /* I/O Bitmap */ 177 int ci_tss_sel; /* TSS selector of this cpu */ 178 179 /* 180 * The following two are actually region_descriptors, 181 * but that would pollute the namespace. 182 */ 183 uintptr_t ci_suspend_gdt; 184 uint16_t ci_suspend_gdt_padding; 185 uintptr_t ci_suspend_idt; 186 uint16_t ci_suspend_idt_padding; 187 188 uint16_t ci_suspend_tr; 189 uint16_t ci_suspend_ldt; 190 uintptr_t ci_suspend_fs; 191 uintptr_t ci_suspend_gs; 192 uintptr_t ci_suspend_kgs; 193 uintptr_t ci_suspend_efer; 194 uintptr_t ci_suspend_reg[12]; 195 uintptr_t ci_suspend_cr0; 196 uintptr_t ci_suspend_cr2; 197 uintptr_t ci_suspend_cr3; 198 uintptr_t ci_suspend_cr4; 199 uintptr_t ci_suspend_cr8; 200 201 /* The following must be in a single cache line. */ 202 int ci_want_resched __aligned(64); 203 int ci_padout __aligned(64); 204 }; 205 206 /* 207 * Macros to handle (some) trapframe registers for common x86 code. 208 */ 209 #ifdef __x86_64__ 210 #define X86_TF_RAX(tf) tf->tf_rax 211 #define X86_TF_RDX(tf) tf->tf_rdx 212 #define X86_TF_RSP(tf) tf->tf_rsp 213 #define X86_TF_RIP(tf) tf->tf_rip 214 #define X86_TF_RFLAGS(tf) tf->tf_rflags 215 #else 216 #define X86_TF_RAX(tf) tf->tf_eax 217 #define X86_TF_RDX(tf) tf->tf_edx 218 #define X86_TF_RSP(tf) tf->tf_esp 219 #define X86_TF_RIP(tf) tf->tf_eip 220 #define X86_TF_RFLAGS(tf) tf->tf_eflags 221 #endif 222 223 /* 224 * Processor flag notes: The "primary" CPU has certain MI-defined 225 * roles (mostly relating to hardclock handling); we distinguish 226 * betwen the processor which booted us, and the processor currently 227 * holding the "primary" role just to give us the flexibility later to 228 * change primaries should we be sufficiently twisted. 229 */ 230 231 #define CPUF_BSP 0x0001 /* CPU is the original BSP */ 232 #define CPUF_AP 0x0002 /* CPU is an AP */ 233 #define CPUF_SP 0x0004 /* CPU is only processor */ 234 #define CPUF_PRIMARY 0x0008 /* CPU is active primary processor */ 235 236 #define CPUF_SYNCTSC 0x0800 /* Synchronize TSC */ 237 #define CPUF_PRESENT 0x1000 /* CPU is present */ 238 #define CPUF_RUNNING 0x2000 /* CPU is running */ 239 #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ 240 #define CPUF_GO 0x8000 /* CPU should start running */ 241 242 /* 243 * We statically allocate the CPU info for the primary CPU (or, 244 * the only CPU on uniprocessors), and the primary CPU is the 245 * first CPU on the CPU info list. 246 */ 247 extern struct cpu_info cpu_info_primary; 248 extern struct cpu_info *cpu_info_list; 249 250 #define CPU_INFO_ITERATOR int 251 #define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = cpu_info_list; \ 252 ci != NULL; ci = ci->ci_next 253 254 #define CPU_STARTUP(_ci, _target) ((_ci)->ci_func->start(_ci, _target)) 255 #define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci)) 256 #define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci)) 257 258 #if !defined(__GNUC__) || defined(_MODULE) 259 /* For non-GCC and modules */ 260 struct cpu_info *x86_curcpu(void); 261 void cpu_set_curpri(int); 262 # ifdef __GNUC__ 263 lwp_t *x86_curlwp(void) __attribute__ ((const)); 264 # else 265 lwp_t *x86_curlwp(void); 266 # endif 267 #endif 268 269 #define cpu_number() (cpu_index(curcpu())) 270 271 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 272 273 #define X86_AST_GENERIC 0x01 274 #define X86_AST_PREEMPT 0x02 275 276 #define aston(l, why) ((l)->l_md.md_astpending |= (why)) 277 #define cpu_did_resched(l) ((l)->l_md.md_astpending &= ~X86_AST_PREEMPT) 278 279 void cpu_boot_secondary_processors(void); 280 void cpu_init_idle_lwps(void); 281 void cpu_init_msrs(struct cpu_info *, bool); 282 283 extern uint32_t cpus_attached; 284 #ifndef XEN 285 #define curcpu() x86_curcpu() 286 #define curlwp x86_curlwp() 287 #else 288 /* XXX initgdt() calls pmap_kenter_pa() which calls splvm() before %fs is set */ 289 #define curcpu() (&cpu_info_primary) 290 #define curlwp curcpu()->ci_curlwp 291 #endif 292 #define curpcb ((struct pcb *)lwp_getpcb(curlwp)) 293 294 /* 295 * Arguments to hardclock, softclock and statclock 296 * encapsulate the previous machine state in an opaque 297 * clockframe; for now, use generic intrframe. 298 */ 299 struct clockframe { 300 struct intrframe cf_if; 301 }; 302 303 /* 304 * Give a profiling tick to the current process when the user profiling 305 * buffer pages are invalid. On the i386, request an ast to send us 306 * through trap(), marking the proc as needing a profiling tick. 307 */ 308 extern void cpu_need_proftick(struct lwp *l); 309 310 /* 311 * Notify the LWP l that it has a signal pending, process as soon as 312 * possible. 313 */ 314 extern void cpu_signotify(struct lwp *); 315 316 /* 317 * We need a machine-independent name for this. 318 */ 319 extern void (*delay_func)(unsigned int); 320 struct timeval; 321 322 #define DELAY(x) (*delay_func)(x) 323 #define delay(x) (*delay_func)(x) 324 325 extern int biosbasemem; 326 extern int biosextmem; 327 extern int cpu; 328 extern int cpuid_level; 329 extern int cpu_class; 330 extern char cpu_brand_string[]; 331 332 extern int i386_use_fxsave; 333 extern int i386_has_sse; 334 extern int i386_has_sse2; 335 336 extern void (*x86_cpu_idle)(void); 337 #define cpu_idle() (*x86_cpu_idle)() 338 339 /* machdep.c */ 340 void dumpconf(void); 341 void cpu_reset(void); 342 void i386_proc0_tss_ldt_init(void); 343 void dumpconf(void); 344 void cpu_reset(void); 345 void x86_64_proc0_tss_ldt_init(void); 346 void x86_64_init_pcb_tss_ldt(struct cpu_info *); 347 348 /* longrun.c */ 349 u_int tmx86_get_longrun_mode(void); 350 void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 351 void tmx86_init_longrun(void); 352 353 /* identcpu.c */ 354 void cpu_probe(struct cpu_info *); 355 void cpu_identify(struct cpu_info *); 356 357 /* cpu_topology.c */ 358 void x86_cpu_topology(struct cpu_info *); 359 360 /* vm_machdep.c */ 361 void cpu_proc_fork(struct proc *, struct proc *); 362 363 /* locore.s */ 364 struct region_descriptor; 365 void lgdt(struct region_descriptor *); 366 #ifdef XEN 367 void lgdt_finish(void); 368 void i386_switch_context(lwp_t *); 369 #endif 370 371 struct pcb; 372 void savectx(struct pcb *); 373 void lwp_trampoline(void); 374 void child_trampoline(void); 375 #ifdef XEN 376 void startrtclock(void); 377 void xen_delay(unsigned int); 378 void xen_initclocks(void); 379 #else 380 /* clock.c */ 381 void initrtclock(u_long); 382 void startrtclock(void); 383 void i8254_delay(unsigned int); 384 void i8254_microtime(struct timeval *); 385 void i8254_initclocks(void); 386 #endif 387 388 /* cpu.c */ 389 390 void cpu_probe_features(struct cpu_info *); 391 392 /* npx.c */ 393 void npxsave_lwp(struct lwp *, bool); 394 void npxsave_cpu(bool); 395 396 /* vm_machdep.c */ 397 paddr_t kvtop(void *); 398 399 #ifdef USER_LDT 400 /* sys_machdep.h */ 401 int x86_get_ldt(struct lwp *, void *, register_t *); 402 int x86_set_ldt(struct lwp *, void *, register_t *); 403 #endif 404 405 /* isa_machdep.c */ 406 void isa_defaultirq(void); 407 int isa_nmi(void); 408 409 #ifdef VM86 410 /* vm86.c */ 411 void vm86_gpfault(struct lwp *, int); 412 #endif /* VM86 */ 413 414 /* consinit.c */ 415 void kgdb_port_init(void); 416 417 /* bus_machdep.c */ 418 void x86_bus_space_init(void); 419 void x86_bus_space_mallocok(void); 420 421 #include <machine/psl.h> /* Must be after struct cpu_info declaration */ 422 423 #endif /* _KERNEL || __KMEMUSER */ 424 425 #if defined(_KERNEL) || defined(_STANDALONE) 426 #include <sys/types.h> 427 #else 428 #include <stdbool.h> 429 #endif /* _KERNEL || _STANDALONE */ 430 431 /* 432 * CTL_MACHDEP definitions. 433 */ 434 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 435 #define CPU_BIOSBASEMEM 2 /* int: bios-reported base mem (K) */ 436 #define CPU_BIOSEXTMEM 3 /* int: bios-reported ext. mem (K) */ 437 /* CPU_NKPDE 4 obsolete: int: number of kernel PDEs */ 438 #define CPU_BOOTED_KERNEL 5 /* string: booted kernel name */ 439 #define CPU_DISKINFO 6 /* struct disklist *: 440 * disk geometry information */ 441 #define CPU_FPU_PRESENT 7 /* int: FPU is present */ 442 #define CPU_OSFXSR 8 /* int: OS uses FXSAVE/FXRSTOR */ 443 #define CPU_SSE 9 /* int: OS/CPU supports SSE */ 444 #define CPU_SSE2 10 /* int: OS/CPU supports SSE2 */ 445 #define CPU_TMLR_MODE 11 /* int: longrun mode 446 * 0: minimum frequency 447 * 1: economy 448 * 2: performance 449 * 3: maximum frequency 450 */ 451 #define CPU_TMLR_FREQUENCY 12 /* int: current frequency */ 452 #define CPU_TMLR_VOLTAGE 13 /* int: curret voltage */ 453 #define CPU_TMLR_PERCENTAGE 14 /* int: current clock percentage */ 454 #define CPU_MAXID 15 /* number of valid machdep ids */ 455 456 /* 457 * Structure for CPU_DISKINFO sysctl call. 458 * XXX this should be somewhere else. 459 */ 460 #define MAX_BIOSDISKS 16 461 462 struct disklist { 463 int dl_nbiosdisks; /* number of bios disks */ 464 struct biosdisk_info { 465 int bi_dev; /* BIOS device # (0x80 ..) */ 466 int bi_cyl; /* cylinders on disk */ 467 int bi_head; /* heads per track */ 468 int bi_sec; /* sectors per track */ 469 uint64_t bi_lbasecs; /* total sec. (iff ext13) */ 470 #define BIFLAG_INVALID 0x01 471 #define BIFLAG_EXTINT13 0x02 472 int bi_flags; 473 } dl_biosdisks[MAX_BIOSDISKS]; 474 475 int dl_nnativedisks; /* number of native disks */ 476 struct nativedisk_info { 477 char ni_devname[16]; /* native device name */ 478 int ni_nmatches; /* # of matches w/ BIOS */ 479 int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */ 480 } dl_nativedisks[1]; /* actually longer */ 481 }; 482 #endif /* !_X86_CPU_H_ */ 483
Indexes created Tue Sep 23 02:09:52 GMT 2025