cpu.h revision 1.23
1 /* $NetBSD: cpu.h,v 1.23 2010/07/24 00:45:56 jym Exp $ */ 2 3 /*- 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 35 */ 36 37 #ifndef _X86_CPU_H_ 38 #define _X86_CPU_H_ 39 40 #if defined(_KERNEL) || defined(_KMEMUSER) 41 #if defined(_KERNEL_OPT) 42 #include "opt_xen.h" 43 #ifdef i386 44 #include "opt_user_ldt.h" 45 #include "opt_vm86.h" 46 #endif 47 #endif 48 49 /* 50 * Definitions unique to x86 cpu support. 51 */ 52 #include <machine/frame.h> 53 #include <machine/pte.h> 54 #include <machine/segments.h> 55 #include <machine/tss.h> 56 #include <machine/intrdefs.h> 57 58 #include <x86/cacheinfo.h> 59 #include <x86/via_padlock.h> 60 61 #include <sys/cpu_data.h> 62 #include <sys/evcnt.h> 63 #include <sys/device_if.h> /* for device_t */ 64 65 struct intrsource; 66 struct pmap; 67 struct device; 68 69 #ifdef __x86_64__ 70 #define i386tss x86_64_tss 71 #endif 72 73 #define NIOPORTS 1024 /* # of ports we allow to be mapped */ 74 #define IOMAPSIZE (NIOPORTS / 8) /* I/O bitmap size in bytes */ 75 76 /* 77 * a bunch of this belongs in cpuvar.h; move it later.. 78 */ 79 80 struct cpu_info { 81 device_t ci_dev; /* pointer to our device */ 82 struct cpu_info *ci_self; /* self-pointer */ 83 volatile struct vcpu_info *ci_vcpu; /* for XEN */ 84 void *ci_tlog_base; /* Trap log base */ 85 int32_t ci_tlog_offset; /* Trap log current offset */ 86 87 /* 88 * Will be accessed by other CPUs. 89 */ 90 struct cpu_info *ci_next; /* next cpu */ 91 struct lwp *ci_curlwp; /* current owner of the processor */ 92 struct pmap_cpu *ci_pmap_cpu; /* per-CPU pmap data */ 93 struct lwp *ci_fpcurlwp; /* current owner of the FPU */ 94 int ci_fpsaving; /* save in progress */ 95 int ci_fpused; /* XEN: FPU was used by curlwp */ 96 cpuid_t ci_cpuid; /* our CPU ID */ 97 int ci_cpumask; /* (1 << CPU ID) */ 98 uint32_t ci_initapicid; /* our intitial APIC ID */ 99 struct cpu_data ci_data; /* MI per-cpu data */ 100 101 /* 102 * Private members. 103 */ 104 struct evcnt ci_tlb_evcnt; /* tlb shootdown counter */ 105 struct pmap *ci_pmap; /* current pmap */ 106 int ci_need_tlbwait; /* need to wait for TLB invalidations */ 107 int ci_want_pmapload; /* pmap_load() is needed */ 108 volatile int ci_tlbstate; /* one of TLBSTATE_ states. see below */ 109 #define TLBSTATE_VALID 0 /* all user tlbs are valid */ 110 #define TLBSTATE_LAZY 1 /* tlbs are valid but won't be kept uptodate */ 111 #define TLBSTATE_STALE 2 /* we might have stale user tlbs */ 112 int ci_curldt; /* current LDT descriptor */ 113 int ci_nintrhand; /* number of H/W interrupt handlers */ 114 uint64_t ci_scratch; 115 116 #ifdef XEN 117 struct iplsource *ci_isources[NIPL]; 118 #else 119 struct intrsource *ci_isources[MAX_INTR_SOURCES]; 120 #endif 121 volatile int ci_mtx_count; /* Negative count of spin mutexes */ 122 volatile int ci_mtx_oldspl; /* Old SPL at this ci_idepth */ 123 124 /* The following must be aligned for cmpxchg8b. */ 125 struct { 126 uint32_t ipending; 127 int ilevel; 128 } ci_istate __aligned(8); 129 #define ci_ipending ci_istate.ipending 130 #define ci_ilevel ci_istate.ilevel 131 132 int ci_idepth; 133 void * ci_intrstack; 134 uint32_t ci_imask[NIPL]; 135 uint32_t ci_iunmask[NIPL]; 136 137 uint32_t ci_flags; /* flags; see below */ 138 uint32_t ci_ipis; /* interprocessor interrupts pending */ 139 uint32_t sc_apic_version; /* local APIC version */ 140 141 uint32_t ci_signature; /* X86 cpuid type */ 142 uint32_t ci_vendor[4]; /* vendor string */ 143 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 144 volatile uint32_t ci_lapic_counter; 145 146 uint32_t ci_feat_val[5]; /* X86 CPUID feature bits 147 * [0] basic features %edx 148 * [1] basic features %ecx 149 * [2] extended features %edx 150 * [3] extended features %ecx 151 * [4] VIA padlock features 152 */ 153 154 const struct cpu_functions *ci_func; /* start/stop functions */ 155 struct trapframe *ci_ddb_regs; 156 157 u_int ci_cflush_lsize; /* CFLUSH insn line size */ 158 struct x86_cache_info ci_cinfo[CAI_COUNT]; 159 160 union descriptor *ci_gdt; 161 162 #ifdef i386 163 struct i386tss ci_doubleflt_tss; 164 struct i386tss ci_ddbipi_tss; 165 #endif 166 167 #ifdef PAE 168 uint32_t ci_pae_l3_pdirpa; /* PA of L3 PD */ 169 pd_entry_t * ci_pae_l3_pdir; /* VA pointer to L3 PD */ 170 #endif 171 172 #if defined(XEN) && defined(__x86_64__) 173 /* Currently active user PGD (can't use rcr3() with Xen) */ 174 paddr_t ci_xen_current_user_pgd; 175 #endif 176 177 char *ci_doubleflt_stack; 178 char *ci_ddbipi_stack; 179 180 struct evcnt ci_ipi_events[X86_NIPI]; 181 182 struct via_padlock ci_vp; /* VIA PadLock private storage */ 183 184 struct i386tss ci_tss; /* Per-cpu TSS; shared among LWPs */ 185 char ci_iomap[IOMAPSIZE]; /* I/O Bitmap */ 186 int ci_tss_sel; /* TSS selector of this cpu */ 187 188 /* 189 * The following two are actually region_descriptors, 190 * but that would pollute the namespace. 191 */ 192 uintptr_t ci_suspend_gdt; 193 uint16_t ci_suspend_gdt_padding; 194 uintptr_t ci_suspend_idt; 195 uint16_t ci_suspend_idt_padding; 196 197 uint16_t ci_suspend_tr; 198 uint16_t ci_suspend_ldt; 199 uintptr_t ci_suspend_fs; 200 uintptr_t ci_suspend_gs; 201 uintptr_t ci_suspend_kgs; 202 uintptr_t ci_suspend_efer; 203 uintptr_t ci_suspend_reg[12]; 204 uintptr_t ci_suspend_cr0; 205 uintptr_t ci_suspend_cr2; 206 uintptr_t ci_suspend_cr3; 207 uintptr_t ci_suspend_cr4; 208 uintptr_t ci_suspend_cr8; 209 210 /* The following must be in a single cache line. */ 211 int ci_want_resched __aligned(64); 212 int ci_padout __aligned(64); 213 }; 214 215 /* 216 * Macros to handle (some) trapframe registers for common x86 code. 217 */ 218 #ifdef __x86_64__ 219 #define X86_TF_RAX(tf) tf->tf_rax 220 #define X86_TF_RDX(tf) tf->tf_rdx 221 #define X86_TF_RSP(tf) tf->tf_rsp 222 #define X86_TF_RIP(tf) tf->tf_rip 223 #define X86_TF_RFLAGS(tf) tf->tf_rflags 224 #else 225 #define X86_TF_RAX(tf) tf->tf_eax 226 #define X86_TF_RDX(tf) tf->tf_edx 227 #define X86_TF_RSP(tf) tf->tf_esp 228 #define X86_TF_RIP(tf) tf->tf_eip 229 #define X86_TF_RFLAGS(tf) tf->tf_eflags 230 #endif 231 232 /* 233 * Processor flag notes: The "primary" CPU has certain MI-defined 234 * roles (mostly relating to hardclock handling); we distinguish 235 * betwen the processor which booted us, and the processor currently 236 * holding the "primary" role just to give us the flexibility later to 237 * change primaries should we be sufficiently twisted. 238 */ 239 240 #define CPUF_BSP 0x0001 /* CPU is the original BSP */ 241 #define CPUF_AP 0x0002 /* CPU is an AP */ 242 #define CPUF_SP 0x0004 /* CPU is only processor */ 243 #define CPUF_PRIMARY 0x0008 /* CPU is active primary processor */ 244 245 #define CPUF_SYNCTSC 0x0800 /* Synchronize TSC */ 246 #define CPUF_PRESENT 0x1000 /* CPU is present */ 247 #define CPUF_RUNNING 0x2000 /* CPU is running */ 248 #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ 249 #define CPUF_GO 0x8000 /* CPU should start running */ 250 251 /* 252 * We statically allocate the CPU info for the primary CPU (or, 253 * the only CPU on uniprocessors), and the primary CPU is the 254 * first CPU on the CPU info list. 255 */ 256 extern struct cpu_info cpu_info_primary; 257 extern struct cpu_info *cpu_info_list; 258 259 #define CPU_INFO_ITERATOR int 260 #define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = cpu_info_list; \ 261 ci != NULL; ci = ci->ci_next 262 263 #define CPU_STARTUP(_ci, _target) ((_ci)->ci_func->start(_ci, _target)) 264 #define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci)) 265 #define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci)) 266 267 #if !defined(__GNUC__) || defined(_MODULE) 268 /* For non-GCC and modules */ 269 struct cpu_info *x86_curcpu(void); 270 void cpu_set_curpri(int); 271 # ifdef __GNUC__ 272 lwp_t *x86_curlwp(void) __attribute__ ((const)); 273 # else 274 lwp_t *x86_curlwp(void); 275 # endif 276 #endif 277 278 #define cpu_number() (cpu_index(curcpu())) 279 280 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 281 282 #define X86_AST_GENERIC 0x01 283 #define X86_AST_PREEMPT 0x02 284 285 #define aston(l, why) ((l)->l_md.md_astpending |= (why)) 286 #define cpu_did_resched(l) ((l)->l_md.md_astpending &= ~X86_AST_PREEMPT) 287 288 void cpu_boot_secondary_processors(void); 289 void cpu_init_idle_lwps(void); 290 void cpu_init_msrs(struct cpu_info *, bool); 291 void cpu_load_pmap(struct pmap *); 292 293 extern uint32_t cpus_attached; 294 #ifndef XEN 295 #define curcpu() x86_curcpu() 296 #define curlwp x86_curlwp() 297 #else 298 /* XXX initgdt() calls pmap_kenter_pa() which calls splvm() before %fs is set */ 299 #define curcpu() (&cpu_info_primary) 300 #define curlwp curcpu()->ci_curlwp 301 #endif 302 #define curpcb ((struct pcb *)lwp_getpcb(curlwp)) 303 304 /* 305 * Arguments to hardclock, softclock and statclock 306 * encapsulate the previous machine state in an opaque 307 * clockframe; for now, use generic intrframe. 308 */ 309 struct clockframe { 310 struct intrframe cf_if; 311 }; 312 313 /* 314 * Give a profiling tick to the current process when the user profiling 315 * buffer pages are invalid. On the i386, request an ast to send us 316 * through trap(), marking the proc as needing a profiling tick. 317 */ 318 extern void cpu_need_proftick(struct lwp *l); 319 320 /* 321 * Notify the LWP l that it has a signal pending, process as soon as 322 * possible. 323 */ 324 extern void cpu_signotify(struct lwp *); 325 326 /* 327 * We need a machine-independent name for this. 328 */ 329 extern void (*delay_func)(unsigned int); 330 struct timeval; 331 332 #define DELAY(x) (*delay_func)(x) 333 #define delay(x) (*delay_func)(x) 334 335 extern int biosbasemem; 336 extern int biosextmem; 337 extern int cpu; 338 extern int cpuid_level; 339 extern int cpu_class; 340 extern char cpu_brand_string[]; 341 342 extern int i386_use_fxsave; 343 extern int i386_has_sse; 344 extern int i386_has_sse2; 345 346 extern void (*x86_cpu_idle)(void); 347 #define cpu_idle() (*x86_cpu_idle)() 348 349 /* machdep.c */ 350 void dumpconf(void); 351 void cpu_reset(void); 352 void i386_proc0_tss_ldt_init(void); 353 void dumpconf(void); 354 void cpu_reset(void); 355 void x86_64_proc0_tss_ldt_init(void); 356 void x86_64_init_pcb_tss_ldt(struct cpu_info *); 357 358 /* longrun.c */ 359 u_int tmx86_get_longrun_mode(void); 360 void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 361 void tmx86_init_longrun(void); 362 363 /* identcpu.c */ 364 void cpu_probe(struct cpu_info *); 365 void cpu_identify(struct cpu_info *); 366 367 /* cpu_topology.c */ 368 void x86_cpu_topology(struct cpu_info *); 369 370 /* vm_machdep.c */ 371 void cpu_proc_fork(struct proc *, struct proc *); 372 373 /* locore.s */ 374 struct region_descriptor; 375 void lgdt(struct region_descriptor *); 376 #ifdef XEN 377 void lgdt_finish(void); 378 void i386_switch_context(lwp_t *); 379 #endif 380 381 struct pcb; 382 void savectx(struct pcb *); 383 void lwp_trampoline(void); 384 void child_trampoline(void); 385 #ifdef XEN 386 void startrtclock(void); 387 void xen_delay(unsigned int); 388 void xen_initclocks(void); 389 #else 390 /* clock.c */ 391 void initrtclock(u_long); 392 void startrtclock(void); 393 void i8254_delay(unsigned int); 394 void i8254_microtime(struct timeval *); 395 void i8254_initclocks(void); 396 #endif 397 398 /* cpu.c */ 399 400 void cpu_probe_features(struct cpu_info *); 401 402 /* npx.c */ 403 void npxsave_lwp(struct lwp *, bool); 404 void npxsave_cpu(bool); 405 406 /* vm_machdep.c */ 407 paddr_t kvtop(void *); 408 409 #ifdef USER_LDT 410 /* sys_machdep.h */ 411 int x86_get_ldt(struct lwp *, void *, register_t *); 412 int x86_set_ldt(struct lwp *, void *, register_t *); 413 #endif 414 415 /* isa_machdep.c */ 416 void isa_defaultirq(void); 417 int isa_nmi(void); 418 419 #ifdef VM86 420 /* vm86.c */ 421 void vm86_gpfault(struct lwp *, int); 422 #endif /* VM86 */ 423 424 /* consinit.c */ 425 void kgdb_port_init(void); 426 427 /* bus_machdep.c */ 428 void x86_bus_space_init(void); 429 void x86_bus_space_mallocok(void); 430 431 #include <machine/psl.h> /* Must be after struct cpu_info declaration */ 432 433 #endif /* _KERNEL || __KMEMUSER */ 434 435 #if defined(_KERNEL) || defined(_STANDALONE) 436 #include <sys/types.h> 437 #else 438 #include <stdbool.h> 439 #endif /* _KERNEL || _STANDALONE */ 440 441 /* 442 * CTL_MACHDEP definitions. 443 */ 444 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 445 #define CPU_BIOSBASEMEM 2 /* int: bios-reported base mem (K) */ 446 #define CPU_BIOSEXTMEM 3 /* int: bios-reported ext. mem (K) */ 447 /* CPU_NKPDE 4 obsolete: int: number of kernel PDEs */ 448 #define CPU_BOOTED_KERNEL 5 /* string: booted kernel name */ 449 #define CPU_DISKINFO 6 /* struct disklist *: 450 * disk geometry information */ 451 #define CPU_FPU_PRESENT 7 /* int: FPU is present */ 452 #define CPU_OSFXSR 8 /* int: OS uses FXSAVE/FXRSTOR */ 453 #define CPU_SSE 9 /* int: OS/CPU supports SSE */ 454 #define CPU_SSE2 10 /* int: OS/CPU supports SSE2 */ 455 #define CPU_TMLR_MODE 11 /* int: longrun mode 456 * 0: minimum frequency 457 * 1: economy 458 * 2: performance 459 * 3: maximum frequency 460 */ 461 #define CPU_TMLR_FREQUENCY 12 /* int: current frequency */ 462 #define CPU_TMLR_VOLTAGE 13 /* int: curret voltage */ 463 #define CPU_TMLR_PERCENTAGE 14 /* int: current clock percentage */ 464 #define CPU_MAXID 15 /* number of valid machdep ids */ 465 466 /* 467 * Structure for CPU_DISKINFO sysctl call. 468 * XXX this should be somewhere else. 469 */ 470 #define MAX_BIOSDISKS 16 471 472 struct disklist { 473 int dl_nbiosdisks; /* number of bios disks */ 474 struct biosdisk_info { 475 int bi_dev; /* BIOS device # (0x80 ..) */ 476 int bi_cyl; /* cylinders on disk */ 477 int bi_head; /* heads per track */ 478 int bi_sec; /* sectors per track */ 479 uint64_t bi_lbasecs; /* total sec. (iff ext13) */ 480 #define BIFLAG_INVALID 0x01 481 #define BIFLAG_EXTINT13 0x02 482 int bi_flags; 483 } dl_biosdisks[MAX_BIOSDISKS]; 484 485 int dl_nnativedisks; /* number of native disks */ 486 struct nativedisk_info { 487 char ni_devname[16]; /* native device name */ 488 int ni_nmatches; /* # of matches w/ BIOS */ 489 int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */ 490 } dl_nativedisks[1]; /* actually longer */ 491 }; 492 #endif /* !_X86_CPU_H_ */ 493
Indexes created Mon Sep 22 21:09:42 GMT 2025