cpu.h revision 1.35
1 /* $NetBSD: cpu.h,v 1.35 2011/06/12 03:35:50 rmind Exp $ */ 2 3 /*- 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 35 */ 36 37 #ifndef _X86_CPU_H_ 38 #define _X86_CPU_H_ 39 40 #if defined(_KERNEL) || defined(_STANDALONE) 41 #include <sys/types.h> 42 #else 43 #include <stdbool.h> 44 #endif /* _KERNEL || _STANDALONE */ 45 46 #if defined(_KERNEL) || defined(_KMEMUSER) 47 #if defined(_KERNEL_OPT) 48 #include "opt_xen.h" 49 #ifdef i386 50 #include "opt_user_ldt.h" 51 #include "opt_vm86.h" 52 #endif 53 #endif 54 55 /* 56 * Definitions unique to x86 cpu support. 57 */ 58 #include <machine/frame.h> 59 #include <machine/pte.h> 60 #include <machine/segments.h> 61 #include <machine/tss.h> 62 #include <machine/intrdefs.h> 63 64 #include <x86/cacheinfo.h> 65 66 #include <sys/cpu_data.h> 67 #include <sys/evcnt.h> 68 #include <sys/device_if.h> /* for device_t */ 69 70 struct intrsource; 71 struct pmap; 72 struct device; 73 74 #ifdef __x86_64__ 75 #define i386tss x86_64_tss 76 #endif 77 78 #define NIOPORTS 1024 /* # of ports we allow to be mapped */ 79 #define IOMAPSIZE (NIOPORTS / 8) /* I/O bitmap size in bytes */ 80 81 /* 82 * a bunch of this belongs in cpuvar.h; move it later.. 83 */ 84 85 struct cpu_info { 86 struct cpu_data ci_data; /* MI per-cpu data */ 87 device_t ci_dev; /* pointer to our device */ 88 struct cpu_info *ci_self; /* self-pointer */ 89 volatile struct vcpu_info *ci_vcpu; /* for XEN */ 90 void *ci_tlog_base; /* Trap log base */ 91 int32_t ci_tlog_offset; /* Trap log current offset */ 92 93 /* 94 * Will be accessed by other CPUs. 95 */ 96 struct cpu_info *ci_next; /* next cpu */ 97 struct lwp *ci_curlwp; /* current owner of the processor */ 98 struct lwp *ci_fpcurlwp; /* current owner of the FPU */ 99 int ci_fpsaving; /* save in progress */ 100 int ci_fpused; /* XEN: FPU was used by curlwp */ 101 cpuid_t ci_cpuid; /* our CPU ID */ 102 int ci_cpumask; /* (1 << CPU ID) */ 103 uint32_t ci_acpiid; /* our ACPI/MADT ID */ 104 uint32_t ci_initapicid; /* our intitial APIC ID */ 105 106 /* 107 * Private members. 108 */ 109 struct evcnt ci_tlb_evcnt; /* tlb shootdown counter */ 110 struct pmap *ci_pmap; /* current pmap */ 111 int ci_need_tlbwait; /* need to wait for TLB invalidations */ 112 int ci_want_pmapload; /* pmap_load() is needed */ 113 volatile int ci_tlbstate; /* one of TLBSTATE_ states. see below */ 114 #define TLBSTATE_VALID 0 /* all user tlbs are valid */ 115 #define TLBSTATE_LAZY 1 /* tlbs are valid but won't be kept uptodate */ 116 #define TLBSTATE_STALE 2 /* we might have stale user tlbs */ 117 int ci_curldt; /* current LDT descriptor */ 118 int ci_nintrhand; /* number of H/W interrupt handlers */ 119 uint64_t ci_scratch; 120 uintptr_t ci_pmap_data[128 / sizeof(uintptr_t)]; 121 122 #ifdef XEN 123 struct iplsource *ci_isources[NIPL]; 124 #else 125 struct intrsource *ci_isources[MAX_INTR_SOURCES]; 126 #endif 127 volatile int ci_mtx_count; /* Negative count of spin mutexes */ 128 volatile int ci_mtx_oldspl; /* Old SPL at this ci_idepth */ 129 130 /* The following must be aligned for cmpxchg8b. */ 131 struct { 132 uint32_t ipending; 133 int ilevel; 134 } ci_istate __aligned(8); 135 #define ci_ipending ci_istate.ipending 136 #define ci_ilevel ci_istate.ilevel 137 138 int ci_idepth; 139 void * ci_intrstack; 140 uint32_t ci_imask[NIPL]; 141 uint32_t ci_iunmask[NIPL]; 142 143 uint32_t ci_flags; /* flags; see below */ 144 uint32_t ci_ipis; /* interprocessor interrupts pending */ 145 uint32_t sc_apic_version; /* local APIC version */ 146 147 uint32_t ci_signature; /* X86 cpuid type */ 148 uint32_t ci_vendor[4]; /* vendor string */ 149 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 150 volatile uint32_t ci_lapic_counter; 151 152 uint32_t ci_feat_val[5]; /* X86 CPUID feature bits 153 * [0] basic features %edx 154 * [1] basic features %ecx 155 * [2] extended features %edx 156 * [3] extended features %ecx 157 * [4] VIA padlock features 158 */ 159 160 const struct cpu_functions *ci_func; /* start/stop functions */ 161 struct trapframe *ci_ddb_regs; 162 163 u_int ci_cflush_lsize; /* CFLUSH insn line size */ 164 struct x86_cache_info ci_cinfo[CAI_COUNT]; 165 166 union descriptor *ci_gdt; 167 168 #ifdef i386 169 struct i386tss ci_doubleflt_tss; 170 struct i386tss ci_ddbipi_tss; 171 #endif 172 173 #ifdef PAE 174 uint32_t ci_pae_l3_pdirpa; /* PA of L3 PD */ 175 pd_entry_t * ci_pae_l3_pdir; /* VA pointer to L3 PD */ 176 #endif 177 178 #if defined(XEN) && defined(__x86_64__) 179 /* Currently active user PGD (can't use rcr3() with Xen) */ 180 paddr_t ci_xen_current_user_pgd; 181 #endif 182 183 char *ci_doubleflt_stack; 184 char *ci_ddbipi_stack; 185 186 struct evcnt ci_ipi_events[X86_NIPI]; 187 188 device_t ci_frequency; /* Frequency scaling technology */ 189 device_t ci_padlock; /* VIA PadLock private storage */ 190 device_t ci_temperature; /* Intel coretemp(4) or equivalent */ 191 192 struct i386tss ci_tss; /* Per-cpu TSS; shared among LWPs */ 193 char ci_iomap[IOMAPSIZE]; /* I/O Bitmap */ 194 int ci_tss_sel; /* TSS selector of this cpu */ 195 196 /* 197 * The following two are actually region_descriptors, 198 * but that would pollute the namespace. 199 */ 200 uintptr_t ci_suspend_gdt; 201 uint16_t ci_suspend_gdt_padding; 202 uintptr_t ci_suspend_idt; 203 uint16_t ci_suspend_idt_padding; 204 205 uint16_t ci_suspend_tr; 206 uint16_t ci_suspend_ldt; 207 uintptr_t ci_suspend_fs; 208 uintptr_t ci_suspend_gs; 209 uintptr_t ci_suspend_kgs; 210 uintptr_t ci_suspend_efer; 211 uintptr_t ci_suspend_reg[12]; 212 uintptr_t ci_suspend_cr0; 213 uintptr_t ci_suspend_cr2; 214 uintptr_t ci_suspend_cr3; 215 uintptr_t ci_suspend_cr4; 216 uintptr_t ci_suspend_cr8; 217 218 /* The following must be in a single cache line. */ 219 int ci_want_resched __aligned(64); 220 int ci_padout __aligned(64); 221 }; 222 223 /* 224 * Macros to handle (some) trapframe registers for common x86 code. 225 */ 226 #ifdef __x86_64__ 227 #define X86_TF_RAX(tf) tf->tf_rax 228 #define X86_TF_RDX(tf) tf->tf_rdx 229 #define X86_TF_RSP(tf) tf->tf_rsp 230 #define X86_TF_RIP(tf) tf->tf_rip 231 #define X86_TF_RFLAGS(tf) tf->tf_rflags 232 #else 233 #define X86_TF_RAX(tf) tf->tf_eax 234 #define X86_TF_RDX(tf) tf->tf_edx 235 #define X86_TF_RSP(tf) tf->tf_esp 236 #define X86_TF_RIP(tf) tf->tf_eip 237 #define X86_TF_RFLAGS(tf) tf->tf_eflags 238 #endif 239 240 /* 241 * Processor flag notes: The "primary" CPU has certain MI-defined 242 * roles (mostly relating to hardclock handling); we distinguish 243 * betwen the processor which booted us, and the processor currently 244 * holding the "primary" role just to give us the flexibility later to 245 * change primaries should we be sufficiently twisted. 246 */ 247 248 #define CPUF_BSP 0x0001 /* CPU is the original BSP */ 249 #define CPUF_AP 0x0002 /* CPU is an AP */ 250 #define CPUF_SP 0x0004 /* CPU is only processor */ 251 #define CPUF_PRIMARY 0x0008 /* CPU is active primary processor */ 252 253 #define CPUF_SYNCTSC 0x0800 /* Synchronize TSC */ 254 #define CPUF_PRESENT 0x1000 /* CPU is present */ 255 #define CPUF_RUNNING 0x2000 /* CPU is running */ 256 #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ 257 #define CPUF_GO 0x8000 /* CPU should start running */ 258 259 /* 260 * We statically allocate the CPU info for the primary CPU (or, 261 * the only CPU on uniprocessors), and the primary CPU is the 262 * first CPU on the CPU info list. 263 */ 264 extern struct cpu_info cpu_info_primary; 265 extern struct cpu_info *cpu_info_list; 266 267 #define CPU_INFO_ITERATOR int 268 #define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = cpu_info_list; \ 269 ci != NULL; ci = ci->ci_next 270 271 #define CPU_STARTUP(_ci, _target) ((_ci)->ci_func->start(_ci, _target)) 272 #define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci)) 273 #define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci)) 274 275 #if !defined(__GNUC__) || defined(_MODULE) 276 /* For non-GCC and modules */ 277 struct cpu_info *x86_curcpu(void); 278 void cpu_set_curpri(int); 279 # ifdef __GNUC__ 280 lwp_t *x86_curlwp(void) __attribute__ ((const)); 281 # else 282 lwp_t *x86_curlwp(void); 283 # endif 284 #endif 285 286 #define cpu_number() (cpu_index(curcpu())) 287 288 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 289 290 #define X86_AST_GENERIC 0x01 291 #define X86_AST_PREEMPT 0x02 292 293 #define aston(l, why) ((l)->l_md.md_astpending |= (why)) 294 #define cpu_did_resched(l) ((l)->l_md.md_astpending &= ~X86_AST_PREEMPT) 295 296 void cpu_boot_secondary_processors(void); 297 void cpu_init_idle_lwps(void); 298 void cpu_init_msrs(struct cpu_info *, bool); 299 void cpu_load_pmap(struct pmap *); 300 301 extern uint32_t cpus_attached; 302 #ifndef XEN 303 #define curcpu() x86_curcpu() 304 #define curlwp x86_curlwp() 305 #else 306 /* XXX initgdt() calls pmap_kenter_pa() which calls splvm() before %fs is set */ 307 #define curcpu() (&cpu_info_primary) 308 #define curlwp curcpu()->ci_curlwp 309 #endif 310 #define curpcb ((struct pcb *)lwp_getpcb(curlwp)) 311 312 /* 313 * Arguments to hardclock, softclock and statclock 314 * encapsulate the previous machine state in an opaque 315 * clockframe; for now, use generic intrframe. 316 */ 317 struct clockframe { 318 struct intrframe cf_if; 319 }; 320 321 /* 322 * Give a profiling tick to the current process when the user profiling 323 * buffer pages are invalid. On the i386, request an ast to send us 324 * through trap(), marking the proc as needing a profiling tick. 325 */ 326 extern void cpu_need_proftick(struct lwp *l); 327 328 /* 329 * Notify the LWP l that it has a signal pending, process as soon as 330 * possible. 331 */ 332 extern void cpu_signotify(struct lwp *); 333 334 /* 335 * We need a machine-independent name for this. 336 */ 337 extern void (*delay_func)(unsigned int); 338 struct timeval; 339 340 #define DELAY(x) (*delay_func)(x) 341 #define delay(x) (*delay_func)(x) 342 343 extern int biosbasemem; 344 extern int biosextmem; 345 extern int cpu; 346 extern int cpuid_level; 347 extern int cpu_class; 348 extern char cpu_brand_string[]; 349 350 extern int i386_use_fxsave; 351 extern int i386_use_pae; 352 extern int i386_has_sse; 353 extern int i386_has_sse2; 354 355 extern void (*x86_cpu_idle)(void); 356 #define cpu_idle() (*x86_cpu_idle)() 357 358 /* machdep.c */ 359 void dumpconf(void); 360 void cpu_reset(void); 361 void i386_proc0_tss_ldt_init(void); 362 void dumpconf(void); 363 void cpu_reset(void); 364 void x86_64_proc0_tss_ldt_init(void); 365 void x86_64_init_pcb_tss_ldt(struct cpu_info *); 366 367 /* longrun.c */ 368 u_int tmx86_get_longrun_mode(void); 369 void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 370 void tmx86_init_longrun(void); 371 372 /* identcpu.c */ 373 void cpu_probe(struct cpu_info *); 374 void cpu_identify(struct cpu_info *); 375 376 /* cpu_topology.c */ 377 void x86_cpu_topology(struct cpu_info *); 378 379 /* vm_machdep.c */ 380 void cpu_proc_fork(struct proc *, struct proc *); 381 382 /* locore.s */ 383 struct region_descriptor; 384 void lgdt(struct region_descriptor *); 385 #ifdef XEN 386 void lgdt_finish(void); 387 void i386_switch_context(lwp_t *); 388 #endif 389 390 struct pcb; 391 void savectx(struct pcb *); 392 void lwp_trampoline(void); 393 void child_trampoline(void); 394 #ifdef XEN 395 void startrtclock(void); 396 void xen_delay(unsigned int); 397 void xen_initclocks(void); 398 #else 399 /* clock.c */ 400 void initrtclock(u_long); 401 void startrtclock(void); 402 void i8254_delay(unsigned int); 403 void i8254_microtime(struct timeval *); 404 void i8254_initclocks(void); 405 #endif 406 407 /* cpu.c */ 408 409 void cpu_probe_features(struct cpu_info *); 410 411 /* npx.c */ 412 void npxsave_lwp(struct lwp *, bool); 413 void npxsave_cpu(bool); 414 415 /* vm_machdep.c */ 416 paddr_t kvtop(void *); 417 418 #ifdef USER_LDT 419 /* sys_machdep.h */ 420 int x86_get_ldt(struct lwp *, void *, register_t *); 421 int x86_set_ldt(struct lwp *, void *, register_t *); 422 #endif 423 424 /* isa_machdep.c */ 425 void isa_defaultirq(void); 426 int isa_nmi(void); 427 428 #ifdef VM86 429 /* vm86.c */ 430 void vm86_gpfault(struct lwp *, int); 431 #endif /* VM86 */ 432 433 /* consinit.c */ 434 void kgdb_port_init(void); 435 436 /* bus_machdep.c */ 437 void x86_bus_space_init(void); 438 void x86_bus_space_mallocok(void); 439 440 #include <machine/psl.h> /* Must be after struct cpu_info declaration */ 441 442 #endif /* _KERNEL || __KMEMUSER */ 443 444 /* 445 * CTL_MACHDEP definitions. 446 */ 447 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 448 #define CPU_BIOSBASEMEM 2 /* int: bios-reported base mem (K) */ 449 #define CPU_BIOSEXTMEM 3 /* int: bios-reported ext. mem (K) */ 450 /* CPU_NKPDE 4 obsolete: int: number of kernel PDEs */ 451 #define CPU_BOOTED_KERNEL 5 /* string: booted kernel name */ 452 #define CPU_DISKINFO 6 /* struct disklist *: 453 * disk geometry information */ 454 #define CPU_FPU_PRESENT 7 /* int: FPU is present */ 455 #define CPU_OSFXSR 8 /* int: OS uses FXSAVE/FXRSTOR */ 456 #define CPU_SSE 9 /* int: OS/CPU supports SSE */ 457 #define CPU_SSE2 10 /* int: OS/CPU supports SSE2 */ 458 #define CPU_TMLR_MODE 11 /* int: longrun mode 459 * 0: minimum frequency 460 * 1: economy 461 * 2: performance 462 * 3: maximum frequency 463 */ 464 #define CPU_TMLR_FREQUENCY 12 /* int: current frequency */ 465 #define CPU_TMLR_VOLTAGE 13 /* int: curret voltage */ 466 #define CPU_TMLR_PERCENTAGE 14 /* int: current clock percentage */ 467 #define CPU_MAXID 15 /* number of valid machdep ids */ 468 469 /* 470 * Structure for CPU_DISKINFO sysctl call. 471 * XXX this should be somewhere else. 472 */ 473 #define MAX_BIOSDISKS 16 474 475 struct disklist { 476 int dl_nbiosdisks; /* number of bios disks */ 477 struct biosdisk_info { 478 int bi_dev; /* BIOS device # (0x80 ..) */ 479 int bi_cyl; /* cylinders on disk */ 480 int bi_head; /* heads per track */ 481 int bi_sec; /* sectors per track */ 482 uint64_t bi_lbasecs; /* total sec. (iff ext13) */ 483 #define BIFLAG_INVALID 0x01 484 #define BIFLAG_EXTINT13 0x02 485 int bi_flags; 486 } dl_biosdisks[MAX_BIOSDISKS]; 487 488 int dl_nnativedisks; /* number of native disks */ 489 struct nativedisk_info { 490 char ni_devname[16]; /* native device name */ 491 int ni_nmatches; /* # of matches w/ BIOS */ 492 int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */ 493 } dl_nativedisks[1]; /* actually longer */ 494 }; 495 #endif /* !_X86_CPU_H_ */ 496
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