cpu.h revision 1.78
1 /* $NetBSD: cpu.h,v 1.78 2017/08/27 09:32:13 maxv Exp $ */ 2 3 /*- 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 35 */ 36 37 #ifndef _X86_CPU_H_ 38 #define _X86_CPU_H_ 39 40 #if defined(_KERNEL) || defined(_STANDALONE) 41 #include <sys/types.h> 42 #else 43 #include <stdint.h> 44 #include <stdbool.h> 45 #endif /* _KERNEL || _STANDALONE */ 46 47 #if defined(_KERNEL) || defined(_KMEMUSER) 48 #if defined(_KERNEL_OPT) 49 #include "opt_xen.h" 50 #ifdef i386 51 #include "opt_user_ldt.h" 52 #endif 53 #endif 54 55 /* 56 * Definitions unique to x86 cpu support. 57 */ 58 #include <machine/frame.h> 59 #include <machine/pte.h> 60 #include <machine/segments.h> 61 #include <machine/tss.h> 62 #include <machine/intrdefs.h> 63 64 #include <x86/cacheinfo.h> 65 66 #include <sys/cpu_data.h> 67 #include <sys/evcnt.h> 68 #include <sys/device_if.h> /* for device_t */ 69 70 #ifdef XEN 71 #include <xen/xen-public/xen.h> 72 #include <xen/xen-public/event_channel.h> 73 #include <sys/mutex.h> 74 #endif /* XEN */ 75 76 struct intrsource; 77 struct pmap; 78 79 #ifdef __x86_64__ 80 #define i386tss x86_64_tss 81 #endif 82 83 #define NIOPORTS 1024 /* # of ports we allow to be mapped */ 84 #define IOMAPSIZE (NIOPORTS / 8) /* I/O bitmap size in bytes */ 85 86 /* 87 * a bunch of this belongs in cpuvar.h; move it later.. 88 */ 89 90 struct cpu_info { 91 struct cpu_data ci_data; /* MI per-cpu data */ 92 device_t ci_dev; /* pointer to our device */ 93 struct cpu_info *ci_self; /* self-pointer */ 94 volatile struct vcpu_info *ci_vcpu; /* for XEN */ 95 void *ci_tlog_base; /* Trap log base */ 96 int32_t ci_tlog_offset; /* Trap log current offset */ 97 98 /* 99 * Will be accessed by other CPUs. 100 */ 101 struct cpu_info *ci_next; /* next cpu */ 102 struct lwp *ci_curlwp; /* current owner of the processor */ 103 struct lwp *ci_fpcurlwp; /* current owner of the FPU */ 104 int _unused1[2]; 105 cpuid_t ci_cpuid; /* our CPU ID */ 106 int _unused; 107 uint32_t ci_acpiid; /* our ACPI/MADT ID */ 108 uint32_t ci_initapicid; /* our intitial APIC ID */ 109 110 /* 111 * Private members. 112 */ 113 struct evcnt ci_tlb_evcnt; /* tlb shootdown counter */ 114 struct pmap *ci_pmap; /* current pmap */ 115 int ci_need_tlbwait; /* need to wait for TLB invalidations */ 116 int ci_want_pmapload; /* pmap_load() is needed */ 117 volatile int ci_tlbstate; /* one of TLBSTATE_ states. see below */ 118 #define TLBSTATE_VALID 0 /* all user tlbs are valid */ 119 #define TLBSTATE_LAZY 1 /* tlbs are valid but won't be kept uptodate */ 120 #define TLBSTATE_STALE 2 /* we might have stale user tlbs */ 121 int ci_curldt; /* current LDT descriptor */ 122 int ci_nintrhand; /* number of H/W interrupt handlers */ 123 uint64_t ci_scratch; 124 uintptr_t ci_pmap_data[128 / sizeof(uintptr_t)]; 125 126 #ifdef XEN 127 u_long ci_evtmask[NR_EVENT_CHANNELS]; /* events allowed on this CPU */ 128 #endif 129 struct intrsource *ci_isources[MAX_INTR_SOURCES]; 130 131 volatile int ci_mtx_count; /* Negative count of spin mutexes */ 132 volatile int ci_mtx_oldspl; /* Old SPL at this ci_idepth */ 133 134 #ifndef __HAVE_DIRECT_MAP 135 #define VPAGE_SRC 0 136 #define VPAGE_DST 1 137 #define VPAGE_ZER 2 138 #define VPAGE_PTP 3 139 #define VPAGE_MAX 4 140 vaddr_t vpage[VPAGE_MAX]; 141 pt_entry_t *vpage_pte[VPAGE_MAX]; 142 #endif 143 144 /* The following must be aligned for cmpxchg8b. */ 145 struct { 146 uint32_t ipending; 147 int ilevel; 148 } ci_istate __aligned(8); 149 #define ci_ipending ci_istate.ipending 150 #define ci_ilevel ci_istate.ilevel 151 152 int ci_idepth; 153 void * ci_intrstack; 154 uint32_t ci_imask[NIPL]; 155 uint32_t ci_iunmask[NIPL]; 156 157 uint32_t ci_flags; /* flags; see below */ 158 uint32_t ci_ipis; /* interprocessor interrupts pending */ 159 uint32_t sc_apic_version; /* local APIC version */ 160 161 uint32_t ci_signature; /* X86 cpuid type (cpuid.1.%eax) */ 162 uint32_t ci_vendor[4]; /* vendor string */ 163 uint32_t _unused2; 164 uint32_t ci_max_cpuid; /* cpuid.0:%eax */ 165 uint32_t ci_max_ext_cpuid; /* cpuid.80000000:%eax */ 166 volatile uint32_t ci_lapic_counter; 167 168 uint32_t ci_feat_val[7]; /* X86 CPUID feature bits */ 169 /* [0] basic features cpuid.1:%edx 170 * [1] basic features cpuid.1:%ecx (CPUID2_xxx bits) 171 * [2] extended features cpuid:80000001:%edx 172 * [3] extended features cpuid:80000001:%ecx 173 * [4] VIA padlock features 174 * [5] structured extended features cpuid.7:%ebx 175 * [6] structured extended features cpuid.7:%ecx 176 */ 177 178 const struct cpu_functions *ci_func; /* start/stop functions */ 179 struct trapframe *ci_ddb_regs; 180 181 u_int ci_cflush_lsize; /* CLFLUSH insn line size */ 182 struct x86_cache_info ci_cinfo[CAI_COUNT]; 183 184 union descriptor *ci_gdt; 185 186 #ifdef i386 187 struct i386tss ci_doubleflt_tss; 188 struct i386tss ci_ddbipi_tss; 189 #endif 190 191 #ifdef PAE 192 uint32_t ci_pae_l3_pdirpa; /* PA of L3 PD */ 193 pd_entry_t * ci_pae_l3_pdir; /* VA pointer to L3 PD */ 194 #endif 195 196 #if defined(XEN) && (defined(PAE) || defined(__x86_64__)) 197 /* Currently active user PGD (can't use rcr3() with Xen) */ 198 pd_entry_t * ci_kpm_pdir; /* per-cpu PMD (va) */ 199 paddr_t ci_kpm_pdirpa; /* per-cpu PMD (pa) */ 200 kmutex_t ci_kpm_mtx; 201 #if defined(__x86_64__) 202 /* per-cpu version of normal_pdes */ 203 pd_entry_t * ci_normal_pdes[3]; /* Ok to hardcode. only for x86_64 && XEN */ 204 paddr_t ci_xen_current_user_pgd; 205 #endif /* __x86_64__ */ 206 #endif /* XEN et.al */ 207 208 #ifndef XEN 209 struct evcnt ci_ipi_events[X86_NIPI]; 210 #else /* XEN */ 211 struct evcnt ci_ipi_events[XEN_NIPIS]; 212 evtchn_port_t ci_ipi_evtchn; 213 #endif /* XEN */ 214 215 device_t ci_frequency; /* Frequency scaling technology */ 216 device_t ci_padlock; /* VIA PadLock private storage */ 217 device_t ci_temperature; /* Intel coretemp(4) or equivalent */ 218 device_t ci_vm; /* Virtual machine guest driver */ 219 220 struct i386tss ci_tss; /* Per-cpu TSS; shared among LWPs */ 221 char ci_iomap[IOMAPSIZE]; /* I/O Bitmap */ 222 int ci_tss_sel; /* TSS selector of this cpu */ 223 224 /* 225 * The following two are actually region_descriptors, 226 * but that would pollute the namespace. 227 */ 228 uintptr_t ci_suspend_gdt; 229 uint16_t ci_suspend_gdt_padding; 230 uintptr_t ci_suspend_idt; 231 uint16_t ci_suspend_idt_padding; 232 233 uint16_t ci_suspend_tr; 234 uint16_t ci_suspend_ldt; 235 uintptr_t ci_suspend_fs; 236 uintptr_t ci_suspend_gs; 237 uintptr_t ci_suspend_kgs; 238 uintptr_t ci_suspend_efer; 239 uintptr_t ci_suspend_reg[12]; 240 uintptr_t ci_suspend_cr0; 241 uintptr_t ci_suspend_cr2; 242 uintptr_t ci_suspend_cr3; 243 uintptr_t ci_suspend_cr4; 244 uintptr_t ci_suspend_cr8; 245 246 /* The following must be in a single cache line. */ 247 int ci_want_resched __aligned(64); 248 int ci_padout __aligned(64); 249 }; 250 251 /* 252 * Macros to handle (some) trapframe registers for common x86 code. 253 */ 254 #ifdef __x86_64__ 255 #define X86_TF_RAX(tf) tf->tf_rax 256 #define X86_TF_RDX(tf) tf->tf_rdx 257 #define X86_TF_RSP(tf) tf->tf_rsp 258 #define X86_TF_RIP(tf) tf->tf_rip 259 #define X86_TF_RFLAGS(tf) tf->tf_rflags 260 #else 261 #define X86_TF_RAX(tf) tf->tf_eax 262 #define X86_TF_RDX(tf) tf->tf_edx 263 #define X86_TF_RSP(tf) tf->tf_esp 264 #define X86_TF_RIP(tf) tf->tf_eip 265 #define X86_TF_RFLAGS(tf) tf->tf_eflags 266 #endif 267 268 /* 269 * Processor flag notes: The "primary" CPU has certain MI-defined 270 * roles (mostly relating to hardclock handling); we distinguish 271 * betwen the processor which booted us, and the processor currently 272 * holding the "primary" role just to give us the flexibility later to 273 * change primaries should we be sufficiently twisted. 274 */ 275 276 #define CPUF_BSP 0x0001 /* CPU is the original BSP */ 277 #define CPUF_AP 0x0002 /* CPU is an AP */ 278 #define CPUF_SP 0x0004 /* CPU is only processor */ 279 #define CPUF_PRIMARY 0x0008 /* CPU is active primary processor */ 280 281 #define CPUF_SYNCTSC 0x0800 /* Synchronize TSC */ 282 #define CPUF_PRESENT 0x1000 /* CPU is present */ 283 #define CPUF_RUNNING 0x2000 /* CPU is running */ 284 #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ 285 #define CPUF_GO 0x8000 /* CPU should start running */ 286 287 #endif /* _KERNEL || __KMEMUSER */ 288 289 #ifdef _KERNEL 290 /* 291 * We statically allocate the CPU info for the primary CPU (or, 292 * the only CPU on uniprocessors), and the primary CPU is the 293 * first CPU on the CPU info list. 294 */ 295 extern struct cpu_info cpu_info_primary; 296 extern struct cpu_info *cpu_info_list; 297 298 #define CPU_INFO_ITERATOR int __unused 299 #define CPU_INFO_FOREACH(cii, ci) ci = cpu_info_list; \ 300 ci != NULL; ci = ci->ci_next 301 302 #define CPU_STARTUP(_ci, _target) ((_ci)->ci_func->start(_ci, _target)) 303 #define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci)) 304 #define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci)) 305 306 #if !defined(__GNUC__) || defined(_MODULE) 307 /* For non-GCC and modules */ 308 struct cpu_info *x86_curcpu(void); 309 void cpu_set_curpri(int); 310 # ifdef __GNUC__ 311 lwp_t *x86_curlwp(void) __attribute__ ((const)); 312 # else 313 lwp_t *x86_curlwp(void); 314 # endif 315 #endif 316 317 #define cpu_number() (cpu_index(curcpu())) 318 319 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 320 321 #define X86_AST_GENERIC 0x01 322 #define X86_AST_PREEMPT 0x02 323 324 #define aston(l, why) ((l)->l_md.md_astpending |= (why)) 325 #define cpu_did_resched(l) ((l)->l_md.md_astpending &= ~X86_AST_PREEMPT) 326 327 void cpu_boot_secondary_processors(void); 328 void cpu_init_idle_lwps(void); 329 void cpu_init_msrs(struct cpu_info *, bool); 330 void cpu_load_pmap(struct pmap *, struct pmap *); 331 void cpu_broadcast_halt(void); 332 void cpu_kick(struct cpu_info *); 333 334 #define curcpu() x86_curcpu() 335 #define curlwp x86_curlwp() 336 #define curpcb ((struct pcb *)lwp_getpcb(curlwp)) 337 338 /* 339 * Arguments to hardclock, softclock and statclock 340 * encapsulate the previous machine state in an opaque 341 * clockframe; for now, use generic intrframe. 342 */ 343 struct clockframe { 344 struct intrframe cf_if; 345 }; 346 347 /* 348 * Give a profiling tick to the current process when the user profiling 349 * buffer pages are invalid. On the i386, request an ast to send us 350 * through trap(), marking the proc as needing a profiling tick. 351 */ 352 extern void cpu_need_proftick(struct lwp *l); 353 354 /* 355 * Notify the LWP l that it has a signal pending, process as soon as 356 * possible. 357 */ 358 extern void cpu_signotify(struct lwp *); 359 360 /* 361 * We need a machine-independent name for this. 362 */ 363 extern void (*delay_func)(unsigned int); 364 struct timeval; 365 366 #ifndef __HIDE_DELAY 367 #define DELAY(x) (*delay_func)(x) 368 #define delay(x) (*delay_func)(x) 369 #endif 370 371 extern int biosbasemem; 372 extern int biosextmem; 373 extern int cputype; 374 extern int cpuid_level; 375 extern int cpu_class; 376 extern char cpu_brand_string[]; 377 extern int use_pae; 378 379 #ifdef __i386__ 380 extern int i386_fpu_present; 381 int npx586bug1(int, int); 382 extern int i386_fpu_fdivbug; 383 extern int i386_use_fxsave; 384 extern int i386_has_sse; 385 extern int i386_has_sse2; 386 #else 387 #define i386_fpu_present 1 388 #define i386_fpu_fdivbug 0 389 #define i386_use_fxsave 1 390 #define i386_has_sse 1 391 #define i386_has_sse2 1 392 #endif 393 394 extern int x86_fpu_save; 395 #define FPU_SAVE_FSAVE 0 396 #define FPU_SAVE_FXSAVE 1 397 #define FPU_SAVE_XSAVE 2 398 #define FPU_SAVE_XSAVEOPT 3 399 extern unsigned int x86_fpu_save_size; 400 extern uint64_t x86_xsave_features; 401 402 extern void (*x86_cpu_idle)(void); 403 #define cpu_idle() (*x86_cpu_idle)() 404 405 /* machdep.c */ 406 #ifdef i386 407 void cpu_set_tss_gates(struct cpu_info *); 408 #endif 409 void cpu_reset(void); 410 411 /* longrun.c */ 412 u_int tmx86_get_longrun_mode(void); 413 void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 414 void tmx86_init_longrun(void); 415 416 /* identcpu.c */ 417 void cpu_probe(struct cpu_info *); 418 void cpu_identify(struct cpu_info *); 419 void identify_hypervisor(void); 420 421 typedef enum vm_guest { 422 VM_GUEST_NO = 0, 423 VM_GUEST_VM, 424 VM_GUEST_XEN, 425 VM_GUEST_HV, 426 VM_GUEST_VMWARE, 427 VM_GUEST_KVM, 428 VM_LAST 429 } vm_guest_t; 430 extern vm_guest_t vm_guest; 431 432 /* cpu_topology.c */ 433 void x86_cpu_topology(struct cpu_info *); 434 435 /* locore.s */ 436 struct region_descriptor; 437 void lgdt(struct region_descriptor *); 438 #ifdef XEN 439 void lgdt_finish(void); 440 #endif 441 442 struct pcb; 443 void savectx(struct pcb *); 444 void lwp_trampoline(void); 445 #ifdef XEN 446 void startrtclock(void); 447 void xen_delay(unsigned int); 448 void xen_initclocks(void); 449 void xen_suspendclocks(struct cpu_info *); 450 void xen_resumeclocks(struct cpu_info *); 451 #else 452 /* clock.c */ 453 void initrtclock(u_long); 454 void startrtclock(void); 455 void i8254_delay(unsigned int); 456 void i8254_microtime(struct timeval *); 457 void i8254_initclocks(void); 458 #endif 459 460 /* cpu.c */ 461 void cpu_probe_features(struct cpu_info *); 462 463 /* vm_machdep.c */ 464 void cpu_proc_fork(struct proc *, struct proc *); 465 paddr_t kvtop(void *); 466 467 #ifdef USER_LDT 468 /* sys_machdep.h */ 469 int x86_get_ldt(struct lwp *, void *, register_t *); 470 int x86_set_ldt(struct lwp *, void *, register_t *); 471 #endif 472 473 /* isa_machdep.c */ 474 void isa_defaultirq(void); 475 int isa_nmi(void); 476 477 /* consinit.c */ 478 void kgdb_port_init(void); 479 480 /* bus_machdep.c */ 481 void x86_bus_space_init(void); 482 void x86_bus_space_mallocok(void); 483 484 #endif /* _KERNEL */ 485 486 #if defined(_KERNEL) || defined(_KMEMUSER) 487 #include <machine/psl.h> /* Must be after struct cpu_info declaration */ 488 #endif /* _KERNEL || __KMEMUSER */ 489 490 /* 491 * CTL_MACHDEP definitions. 492 */ 493 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 494 #define CPU_BIOSBASEMEM 2 /* int: bios-reported base mem (K) */ 495 #define CPU_BIOSEXTMEM 3 /* int: bios-reported ext. mem (K) */ 496 /* CPU_NKPDE 4 obsolete: int: number of kernel PDEs */ 497 #define CPU_BOOTED_KERNEL 5 /* string: booted kernel name */ 498 #define CPU_DISKINFO 6 /* struct disklist *: 499 * disk geometry information */ 500 #define CPU_FPU_PRESENT 7 /* int: FPU is present */ 501 #define CPU_OSFXSR 8 /* int: OS uses FXSAVE/FXRSTOR */ 502 #define CPU_SSE 9 /* int: OS/CPU supports SSE */ 503 #define CPU_SSE2 10 /* int: OS/CPU supports SSE2 */ 504 #define CPU_TMLR_MODE 11 /* int: longrun mode 505 * 0: minimum frequency 506 * 1: economy 507 * 2: performance 508 * 3: maximum frequency 509 */ 510 #define CPU_TMLR_FREQUENCY 12 /* int: current frequency */ 511 #define CPU_TMLR_VOLTAGE 13 /* int: curret voltage */ 512 #define CPU_TMLR_PERCENTAGE 14 /* int: current clock percentage */ 513 #define CPU_FPU_SAVE 15 /* int: FPU Instructions layout 514 * to use this, CPU_OSFXSR must be true 515 * 0: FSAVE 516 * 1: FXSAVE 517 * 2: XSAVE 518 * 3: XSAVEOPT 519 */ 520 #define CPU_FPU_SAVE_SIZE 16 /* int: FPU Instruction layout size */ 521 #define CPU_XSAVE_FEATURES 17 /* quad: XSAVE features */ 522 523 #define CPU_MAXID 18 /* number of valid machdep ids */ 524 525 /* 526 * Structure for CPU_DISKINFO sysctl call. 527 * XXX this should be somewhere else. 528 */ 529 #define MAX_BIOSDISKS 16 530 531 struct disklist { 532 int dl_nbiosdisks; /* number of bios disks */ 533 struct biosdisk_info { 534 int bi_dev; /* BIOS device # (0x80 ..) */ 535 int bi_cyl; /* cylinders on disk */ 536 int bi_head; /* heads per track */ 537 int bi_sec; /* sectors per track */ 538 uint64_t bi_lbasecs; /* total sec. (iff ext13) */ 539 #define BIFLAG_INVALID 0x01 540 #define BIFLAG_EXTINT13 0x02 541 int bi_flags; 542 } dl_biosdisks[MAX_BIOSDISKS]; 543 544 int dl_nnativedisks; /* number of native disks */ 545 struct nativedisk_info { 546 char ni_devname[16]; /* native device name */ 547 int ni_nmatches; /* # of matches w/ BIOS */ 548 int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */ 549 } dl_nativedisks[1]; /* actually longer */ 550 }; 551 #endif /* !_X86_CPU_H_ */ 552
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