cpu.h revision 1.89
1 /* $NetBSD: cpu.h,v 1.89 2018/01/18 07:25:34 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 35 */ 36 37 #ifndef _X86_CPU_H_ 38 #define _X86_CPU_H_ 39 40 #if defined(_KERNEL) || defined(_STANDALONE) 41 #include <sys/types.h> 42 #else 43 #include <stdint.h> 44 #include <stdbool.h> 45 #endif /* _KERNEL || _STANDALONE */ 46 47 #if defined(_KERNEL) || defined(_KMEMUSER) 48 #if defined(_KERNEL_OPT) 49 #include "opt_xen.h" 50 #include "opt_svs.h" 51 #ifdef i386 52 #include "opt_user_ldt.h" 53 #endif 54 #endif 55 56 /* 57 * Definitions unique to x86 cpu support. 58 */ 59 #include <machine/frame.h> 60 #include <machine/pte.h> 61 #include <machine/segments.h> 62 #include <machine/tss.h> 63 #include <machine/intrdefs.h> 64 65 #include <x86/cacheinfo.h> 66 67 #include <sys/cpu_data.h> 68 #include <sys/evcnt.h> 69 #include <sys/device_if.h> /* for device_t */ 70 71 #ifdef XEN 72 #include <xen/xen-public/xen.h> 73 #include <xen/xen-public/event_channel.h> 74 #include <sys/mutex.h> 75 #endif /* XEN */ 76 77 struct intrsource; 78 struct pmap; 79 80 #ifdef __x86_64__ 81 #define i386tss x86_64_tss 82 #endif 83 84 #define NIOPORTS 1024 /* # of ports we allow to be mapped */ 85 #define IOMAPSIZE (NIOPORTS / 8) /* I/O bitmap size in bytes */ 86 87 struct cpu_tss { 88 #ifdef i386 89 struct i386tss dblflt_tss; 90 struct i386tss ddbipi_tss; 91 #endif 92 struct i386tss tss; 93 uint8_t iomap[IOMAPSIZE]; 94 } __packed; 95 96 /* 97 * a bunch of this belongs in cpuvar.h; move it later.. 98 */ 99 100 struct cpu_info { 101 struct cpu_data ci_data; /* MI per-cpu data */ 102 device_t ci_dev; /* pointer to our device */ 103 struct cpu_info *ci_self; /* self-pointer */ 104 volatile struct vcpu_info *ci_vcpu; /* for XEN */ 105 106 /* 107 * Will be accessed by other CPUs. 108 */ 109 struct cpu_info *ci_next; /* next cpu */ 110 struct lwp *ci_curlwp; /* current owner of the processor */ 111 struct lwp *ci_fpcurlwp; /* current owner of the FPU */ 112 cpuid_t ci_cpuid; /* our CPU ID */ 113 uint32_t ci_acpiid; /* our ACPI/MADT ID */ 114 uint32_t ci_initapicid; /* our initial APIC ID */ 115 116 /* 117 * Private members. 118 */ 119 struct pmap *ci_pmap; /* current pmap */ 120 int ci_want_pmapload; /* pmap_load() is needed */ 121 volatile int ci_tlbstate; /* one of TLBSTATE_ states. see below */ 122 #define TLBSTATE_VALID 0 /* all user tlbs are valid */ 123 #define TLBSTATE_LAZY 1 /* tlbs are valid but won't be kept uptodate */ 124 #define TLBSTATE_STALE 2 /* we might have stale user tlbs */ 125 int ci_curldt; /* current LDT descriptor */ 126 int ci_nintrhand; /* number of H/W interrupt handlers */ 127 uint64_t ci_scratch; 128 uintptr_t ci_pmap_data[128 / sizeof(uintptr_t)]; 129 130 #ifdef XEN 131 u_long ci_evtmask[NR_EVENT_CHANNELS]; /* events allowed on this CPU */ 132 #endif 133 struct intrsource *ci_isources[MAX_INTR_SOURCES]; 134 135 volatile int ci_mtx_count; /* Negative count of spin mutexes */ 136 volatile int ci_mtx_oldspl; /* Old SPL at this ci_idepth */ 137 138 #ifndef __HAVE_DIRECT_MAP 139 #define VPAGE_SRC 0 140 #define VPAGE_DST 1 141 #define VPAGE_ZER 2 142 #define VPAGE_PTP 3 143 #define VPAGE_MAX 4 144 vaddr_t vpage[VPAGE_MAX]; 145 pt_entry_t *vpage_pte[VPAGE_MAX]; 146 #endif 147 148 /* The following must be aligned for cmpxchg8b. */ 149 struct { 150 uint32_t ipending; 151 int ilevel; 152 } ci_istate __aligned(8); 153 #define ci_ipending ci_istate.ipending 154 #define ci_ilevel ci_istate.ilevel 155 156 int ci_idepth; 157 void * ci_intrstack; 158 uint32_t ci_imask[NIPL]; 159 uint32_t ci_iunmask[NIPL]; 160 161 uint32_t ci_flags; /* flags; see below */ 162 uint32_t ci_ipis; /* interprocessor interrupts pending */ 163 164 uint32_t ci_signature; /* X86 cpuid type (cpuid.1.%eax) */ 165 uint32_t ci_vendor[4]; /* vendor string */ 166 uint32_t ci_max_cpuid; /* cpuid.0:%eax */ 167 uint32_t ci_max_ext_cpuid; /* cpuid.80000000:%eax */ 168 volatile uint32_t ci_lapic_counter; 169 170 uint32_t ci_feat_val[7]; /* X86 CPUID feature bits */ 171 /* [0] basic features cpuid.1:%edx 172 * [1] basic features cpuid.1:%ecx (CPUID2_xxx bits) 173 * [2] extended features cpuid:80000001:%edx 174 * [3] extended features cpuid:80000001:%ecx 175 * [4] VIA padlock features 176 * [5] structured extended features cpuid.7:%ebx 177 * [6] structured extended features cpuid.7:%ecx 178 */ 179 180 const struct cpu_functions *ci_func; /* start/stop functions */ 181 struct trapframe *ci_ddb_regs; 182 183 u_int ci_cflush_lsize; /* CLFLUSH insn line size */ 184 struct x86_cache_info ci_cinfo[CAI_COUNT]; 185 186 #ifdef PAE 187 uint32_t ci_pae_l3_pdirpa; /* PA of L3 PD */ 188 pd_entry_t * ci_pae_l3_pdir; /* VA pointer to L3 PD */ 189 #endif 190 191 #ifdef SVS 192 pd_entry_t * ci_svs_updir; 193 paddr_t ci_svs_updirpa; 194 paddr_t ci_svs_kpdirpa; 195 kmutex_t ci_svs_mtx; 196 pd_entry_t * ci_svs_rsp0_pte; 197 vaddr_t ci_svs_rsp0; 198 vaddr_t ci_svs_ursp0; 199 vaddr_t ci_svs_krsp0; 200 vaddr_t ci_svs_utls; 201 #endif 202 203 #if defined(XEN) && (defined(PAE) || defined(__x86_64__)) 204 /* Currently active user PGD (can't use rcr3() with Xen) */ 205 pd_entry_t * ci_kpm_pdir; /* per-cpu PMD (va) */ 206 paddr_t ci_kpm_pdirpa; /* per-cpu PMD (pa) */ 207 kmutex_t ci_kpm_mtx; 208 #if defined(__x86_64__) 209 /* per-cpu version of normal_pdes */ 210 pd_entry_t * ci_normal_pdes[3]; /* Ok to hardcode. only for x86_64 && XEN */ 211 paddr_t ci_xen_current_user_pgd; 212 #endif /* __x86_64__ */ 213 #endif /* XEN et.al */ 214 215 #ifdef XEN 216 size_t ci_xpq_idx; 217 #endif 218 219 #ifndef XEN 220 struct evcnt ci_ipi_events[X86_NIPI]; 221 #else /* XEN */ 222 struct evcnt ci_ipi_events[XEN_NIPIS]; 223 evtchn_port_t ci_ipi_evtchn; 224 #endif /* XEN */ 225 226 device_t ci_frequency; /* Frequency scaling technology */ 227 device_t ci_padlock; /* VIA PadLock private storage */ 228 device_t ci_temperature; /* Intel coretemp(4) or equivalent */ 229 device_t ci_vm; /* Virtual machine guest driver */ 230 231 /* 232 * Segmentation-related data. 233 */ 234 union descriptor *ci_gdt; 235 struct cpu_tss *ci_tss; /* Per-cpu TSSes; shared among LWPs */ 236 int ci_tss_sel; /* TSS selector of this cpu */ 237 238 /* 239 * The following two are actually region_descriptors, 240 * but that would pollute the namespace. 241 */ 242 uintptr_t ci_suspend_gdt; 243 uint16_t ci_suspend_gdt_padding; 244 uintptr_t ci_suspend_idt; 245 uint16_t ci_suspend_idt_padding; 246 247 uint16_t ci_suspend_tr; 248 uint16_t ci_suspend_ldt; 249 uintptr_t ci_suspend_fs; 250 uintptr_t ci_suspend_gs; 251 uintptr_t ci_suspend_kgs; 252 uintptr_t ci_suspend_efer; 253 uintptr_t ci_suspend_reg[12]; 254 uintptr_t ci_suspend_cr0; 255 uintptr_t ci_suspend_cr2; 256 uintptr_t ci_suspend_cr3; 257 uintptr_t ci_suspend_cr4; 258 uintptr_t ci_suspend_cr8; 259 260 /* The following must be in a single cache line. */ 261 int ci_want_resched __aligned(64); 262 int ci_padout __aligned(64); 263 }; 264 265 /* 266 * Macros to handle (some) trapframe registers for common x86 code. 267 */ 268 #ifdef __x86_64__ 269 #define X86_TF_RAX(tf) tf->tf_rax 270 #define X86_TF_RDX(tf) tf->tf_rdx 271 #define X86_TF_RSP(tf) tf->tf_rsp 272 #define X86_TF_RIP(tf) tf->tf_rip 273 #define X86_TF_RFLAGS(tf) tf->tf_rflags 274 #else 275 #define X86_TF_RAX(tf) tf->tf_eax 276 #define X86_TF_RDX(tf) tf->tf_edx 277 #define X86_TF_RSP(tf) tf->tf_esp 278 #define X86_TF_RIP(tf) tf->tf_eip 279 #define X86_TF_RFLAGS(tf) tf->tf_eflags 280 #endif 281 282 /* 283 * Processor flag notes: The "primary" CPU has certain MI-defined 284 * roles (mostly relating to hardclock handling); we distinguish 285 * between the processor which booted us, and the processor currently 286 * holding the "primary" role just to give us the flexibility later to 287 * change primaries should we be sufficiently twisted. 288 */ 289 290 #define CPUF_BSP 0x0001 /* CPU is the original BSP */ 291 #define CPUF_AP 0x0002 /* CPU is an AP */ 292 #define CPUF_SP 0x0004 /* CPU is only processor */ 293 #define CPUF_PRIMARY 0x0008 /* CPU is active primary processor */ 294 295 #define CPUF_SYNCTSC 0x0800 /* Synchronize TSC */ 296 #define CPUF_PRESENT 0x1000 /* CPU is present */ 297 #define CPUF_RUNNING 0x2000 /* CPU is running */ 298 #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ 299 #define CPUF_GO 0x8000 /* CPU should start running */ 300 301 #endif /* _KERNEL || __KMEMUSER */ 302 303 #ifdef _KERNEL 304 /* 305 * We statically allocate the CPU info for the primary CPU (or, 306 * the only CPU on uniprocessors), and the primary CPU is the 307 * first CPU on the CPU info list. 308 */ 309 extern struct cpu_info cpu_info_primary; 310 extern struct cpu_info *cpu_info_list; 311 312 #define CPU_INFO_ITERATOR int __unused 313 #define CPU_INFO_FOREACH(cii, ci) ci = cpu_info_list; \ 314 ci != NULL; ci = ci->ci_next 315 316 #define CPU_STARTUP(_ci, _target) ((_ci)->ci_func->start(_ci, _target)) 317 #define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci)) 318 #define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci)) 319 320 #if !defined(__GNUC__) || defined(_MODULE) 321 /* For non-GCC and modules */ 322 struct cpu_info *x86_curcpu(void); 323 void cpu_set_curpri(int); 324 # ifdef __GNUC__ 325 lwp_t *x86_curlwp(void) __attribute__ ((const)); 326 # else 327 lwp_t *x86_curlwp(void); 328 # endif 329 #endif 330 331 #define cpu_number() (cpu_index(curcpu())) 332 333 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 334 335 #define X86_AST_GENERIC 0x01 336 #define X86_AST_PREEMPT 0x02 337 338 #define aston(l, why) ((l)->l_md.md_astpending |= (why)) 339 #define cpu_did_resched(l) ((l)->l_md.md_astpending &= ~X86_AST_PREEMPT) 340 341 void cpu_boot_secondary_processors(void); 342 void cpu_init_idle_lwps(void); 343 void cpu_init_msrs(struct cpu_info *, bool); 344 void cpu_load_pmap(struct pmap *, struct pmap *); 345 void cpu_broadcast_halt(void); 346 void cpu_kick(struct cpu_info *); 347 348 void cpu_pcpuarea_init(struct cpu_info *); 349 void cpu_svs_init(struct cpu_info *); 350 351 #define curcpu() x86_curcpu() 352 #define curlwp x86_curlwp() 353 #define curpcb ((struct pcb *)lwp_getpcb(curlwp)) 354 355 /* 356 * Arguments to hardclock, softclock and statclock 357 * encapsulate the previous machine state in an opaque 358 * clockframe; for now, use generic intrframe. 359 */ 360 struct clockframe { 361 struct intrframe cf_if; 362 }; 363 364 /* 365 * Give a profiling tick to the current process when the user profiling 366 * buffer pages are invalid. On the i386, request an ast to send us 367 * through trap(), marking the proc as needing a profiling tick. 368 */ 369 extern void cpu_need_proftick(struct lwp *l); 370 371 /* 372 * Notify the LWP l that it has a signal pending, process as soon as 373 * possible. 374 */ 375 extern void cpu_signotify(struct lwp *); 376 377 /* 378 * We need a machine-independent name for this. 379 */ 380 extern void (*delay_func)(unsigned int); 381 struct timeval; 382 383 #ifndef __HIDE_DELAY 384 #define DELAY(x) (*delay_func)(x) 385 #define delay(x) (*delay_func)(x) 386 #endif 387 388 extern int biosbasemem; 389 extern int biosextmem; 390 extern int cputype; 391 extern int cpuid_level; 392 extern int cpu_class; 393 extern char cpu_brand_string[]; 394 extern int use_pae; 395 396 #ifdef __i386__ 397 #define i386_fpu_present 1 398 int npx586bug1(int, int); 399 extern int i386_fpu_fdivbug; 400 extern int i386_use_fxsave; 401 extern int i386_has_sse; 402 extern int i386_has_sse2; 403 #else 404 #define i386_fpu_present 1 405 #define i386_fpu_fdivbug 0 406 #define i386_use_fxsave 1 407 #define i386_has_sse 1 408 #define i386_has_sse2 1 409 #endif 410 411 extern int x86_fpu_save; 412 #define FPU_SAVE_FSAVE 0 413 #define FPU_SAVE_FXSAVE 1 414 #define FPU_SAVE_XSAVE 2 415 #define FPU_SAVE_XSAVEOPT 3 416 extern unsigned int x86_fpu_save_size; 417 extern uint64_t x86_xsave_features; 418 419 extern void (*x86_cpu_idle)(void); 420 #define cpu_idle() (*x86_cpu_idle)() 421 422 /* machdep.c */ 423 #ifdef i386 424 void cpu_set_tss_gates(struct cpu_info *); 425 #endif 426 void cpu_reset(void); 427 428 /* longrun.c */ 429 u_int tmx86_get_longrun_mode(void); 430 void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 431 void tmx86_init_longrun(void); 432 433 /* identcpu.c */ 434 void cpu_probe(struct cpu_info *); 435 void cpu_identify(struct cpu_info *); 436 void identify_hypervisor(void); 437 438 typedef enum vm_guest { 439 VM_GUEST_NO = 0, 440 VM_GUEST_VM, 441 VM_GUEST_XEN, 442 VM_GUEST_HV, 443 VM_GUEST_VMWARE, 444 VM_GUEST_KVM, 445 VM_LAST 446 } vm_guest_t; 447 extern vm_guest_t vm_guest; 448 449 /* cpu_topology.c */ 450 void x86_cpu_topology(struct cpu_info *); 451 452 /* locore.s */ 453 struct region_descriptor; 454 void lgdt(struct region_descriptor *); 455 #ifdef XEN 456 void lgdt_finish(void); 457 #endif 458 459 struct pcb; 460 void savectx(struct pcb *); 461 void lwp_trampoline(void); 462 #ifdef XEN 463 void startrtclock(void); 464 void xen_delay(unsigned int); 465 void xen_initclocks(void); 466 void xen_suspendclocks(struct cpu_info *); 467 void xen_resumeclocks(struct cpu_info *); 468 #else 469 /* clock.c */ 470 void initrtclock(u_long); 471 void startrtclock(void); 472 void i8254_delay(unsigned int); 473 void i8254_microtime(struct timeval *); 474 void i8254_initclocks(void); 475 #endif 476 477 /* cpu.c */ 478 void cpu_probe_features(struct cpu_info *); 479 480 /* vm_machdep.c */ 481 void cpu_proc_fork(struct proc *, struct proc *); 482 paddr_t kvtop(void *); 483 484 #ifdef USER_LDT 485 /* sys_machdep.h */ 486 int x86_get_ldt(struct lwp *, void *, register_t *); 487 int x86_set_ldt(struct lwp *, void *, register_t *); 488 #endif 489 490 /* isa_machdep.c */ 491 void isa_defaultirq(void); 492 int isa_nmi(void); 493 494 /* consinit.c */ 495 void kgdb_port_init(void); 496 497 /* bus_machdep.c */ 498 void x86_bus_space_init(void); 499 void x86_bus_space_mallocok(void); 500 501 #endif /* _KERNEL */ 502 503 #if defined(_KERNEL) || defined(_KMEMUSER) 504 #include <machine/psl.h> /* Must be after struct cpu_info declaration */ 505 #endif /* _KERNEL || __KMEMUSER */ 506 507 /* 508 * CTL_MACHDEP definitions. 509 */ 510 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 511 #define CPU_BIOSBASEMEM 2 /* int: bios-reported base mem (K) */ 512 #define CPU_BIOSEXTMEM 3 /* int: bios-reported ext. mem (K) */ 513 /* CPU_NKPDE 4 obsolete: int: number of kernel PDEs */ 514 #define CPU_BOOTED_KERNEL 5 /* string: booted kernel name */ 515 #define CPU_DISKINFO 6 /* struct disklist *: 516 * disk geometry information */ 517 #define CPU_FPU_PRESENT 7 /* int: FPU is present */ 518 #define CPU_OSFXSR 8 /* int: OS uses FXSAVE/FXRSTOR */ 519 #define CPU_SSE 9 /* int: OS/CPU supports SSE */ 520 #define CPU_SSE2 10 /* int: OS/CPU supports SSE2 */ 521 #define CPU_TMLR_MODE 11 /* int: longrun mode 522 * 0: minimum frequency 523 * 1: economy 524 * 2: performance 525 * 3: maximum frequency 526 */ 527 #define CPU_TMLR_FREQUENCY 12 /* int: current frequency */ 528 #define CPU_TMLR_VOLTAGE 13 /* int: current voltage */ 529 #define CPU_TMLR_PERCENTAGE 14 /* int: current clock percentage */ 530 #define CPU_FPU_SAVE 15 /* int: FPU Instructions layout 531 * to use this, CPU_OSFXSR must be true 532 * 0: FSAVE 533 * 1: FXSAVE 534 * 2: XSAVE 535 * 3: XSAVEOPT 536 */ 537 #define CPU_FPU_SAVE_SIZE 16 /* int: FPU Instruction layout size */ 538 #define CPU_XSAVE_FEATURES 17 /* quad: XSAVE features */ 539 540 #define CPU_MAXID 18 /* number of valid machdep ids */ 541 542 /* 543 * Structure for CPU_DISKINFO sysctl call. 544 * XXX this should be somewhere else. 545 */ 546 #define MAX_BIOSDISKS 16 547 548 struct disklist { 549 int dl_nbiosdisks; /* number of bios disks */ 550 int dl_unused; 551 struct biosdisk_info { 552 int bi_dev; /* BIOS device # (0x80 ..) */ 553 int bi_cyl; /* cylinders on disk */ 554 int bi_head; /* heads per track */ 555 int bi_sec; /* sectors per track */ 556 uint64_t bi_lbasecs; /* total sec. (iff ext13) */ 557 #define BIFLAG_INVALID 0x01 558 #define BIFLAG_EXTINT13 0x02 559 int bi_flags; 560 int bi_unused; 561 } dl_biosdisks[MAX_BIOSDISKS]; 562 563 int dl_nnativedisks; /* number of native disks */ 564 struct nativedisk_info { 565 char ni_devname[16]; /* native device name */ 566 int ni_nmatches; /* # of matches w/ BIOS */ 567 int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */ 568 } dl_nativedisks[1]; /* actually longer */ 569 }; 570 #endif /* !_X86_CPU_H_ */ 571
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