cpu.h revision 1.91
1 /* $NetBSD: cpu.h,v 1.91 2018/04/04 12:59:49 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 35 */ 36 37 #ifndef _X86_CPU_H_ 38 #define _X86_CPU_H_ 39 40 #if defined(_KERNEL) || defined(_STANDALONE) 41 #include <sys/types.h> 42 #else 43 #include <stdint.h> 44 #include <stdbool.h> 45 #endif /* _KERNEL || _STANDALONE */ 46 47 #if defined(_KERNEL) || defined(_KMEMUSER) 48 #if defined(_KERNEL_OPT) 49 #include "opt_xen.h" 50 #include "opt_svs.h" 51 #ifdef i386 52 #include "opt_user_ldt.h" 53 #endif 54 #endif 55 56 /* 57 * Definitions unique to x86 cpu support. 58 */ 59 #include <machine/frame.h> 60 #include <machine/pte.h> 61 #include <machine/segments.h> 62 #include <machine/tss.h> 63 #include <machine/intrdefs.h> 64 65 #include <x86/cacheinfo.h> 66 67 #include <sys/cpu_data.h> 68 #include <sys/evcnt.h> 69 #include <sys/device_if.h> /* for device_t */ 70 71 #ifdef XEN 72 #include <xen/xen-public/xen.h> 73 #include <xen/xen-public/event_channel.h> 74 #include <sys/mutex.h> 75 #endif /* XEN */ 76 77 struct intrsource; 78 struct pmap; 79 80 #ifdef __x86_64__ 81 #define i386tss x86_64_tss 82 #endif 83 84 #define NIOPORTS 1024 /* # of ports we allow to be mapped */ 85 #define IOMAPSIZE (NIOPORTS / 8) /* I/O bitmap size in bytes */ 86 87 struct cpu_tss { 88 #ifdef i386 89 struct i386tss dblflt_tss; 90 struct i386tss ddbipi_tss; 91 #endif 92 struct i386tss tss; 93 uint8_t iomap[IOMAPSIZE]; 94 } __packed; 95 96 /* 97 * a bunch of this belongs in cpuvar.h; move it later.. 98 */ 99 100 struct cpu_info { 101 struct cpu_data ci_data; /* MI per-cpu data */ 102 device_t ci_dev; /* pointer to our device */ 103 struct cpu_info *ci_self; /* self-pointer */ 104 volatile struct vcpu_info *ci_vcpu; /* for XEN */ 105 106 /* 107 * Will be accessed by other CPUs. 108 */ 109 struct cpu_info *ci_next; /* next cpu */ 110 struct lwp *ci_curlwp; /* current owner of the processor */ 111 struct lwp *ci_fpcurlwp; /* current owner of the FPU */ 112 cpuid_t ci_cpuid; /* our CPU ID */ 113 uint32_t ci_acpiid; /* our ACPI/MADT ID */ 114 uint32_t ci_initapicid; /* our initial APIC ID */ 115 116 /* 117 * Private members. 118 */ 119 struct pmap *ci_pmap; /* current pmap */ 120 int ci_want_pmapload; /* pmap_load() is needed */ 121 volatile int ci_tlbstate; /* one of TLBSTATE_ states. see below */ 122 #define TLBSTATE_VALID 0 /* all user tlbs are valid */ 123 #define TLBSTATE_LAZY 1 /* tlbs are valid but won't be kept uptodate */ 124 #define TLBSTATE_STALE 2 /* we might have stale user tlbs */ 125 int ci_curldt; /* current LDT descriptor */ 126 int ci_nintrhand; /* number of H/W interrupt handlers */ 127 uint64_t ci_scratch; 128 uintptr_t ci_pmap_data[128 / sizeof(uintptr_t)]; 129 130 #ifdef XEN 131 u_long ci_evtmask[NR_EVENT_CHANNELS]; /* events allowed on this CPU */ 132 #endif 133 struct intrsource *ci_isources[MAX_INTR_SOURCES]; 134 135 volatile int ci_mtx_count; /* Negative count of spin mutexes */ 136 volatile int ci_mtx_oldspl; /* Old SPL at this ci_idepth */ 137 138 #ifndef __HAVE_DIRECT_MAP 139 #define VPAGE_SRC 0 140 #define VPAGE_DST 1 141 #define VPAGE_ZER 2 142 #define VPAGE_PTP 3 143 #define VPAGE_MAX 4 144 vaddr_t vpage[VPAGE_MAX]; 145 pt_entry_t *vpage_pte[VPAGE_MAX]; 146 #endif 147 148 /* The following must be aligned for cmpxchg8b. */ 149 struct { 150 uint32_t ipending; 151 int ilevel; 152 } ci_istate __aligned(8); 153 #define ci_ipending ci_istate.ipending 154 #define ci_ilevel ci_istate.ilevel 155 156 int ci_idepth; 157 void * ci_intrstack; 158 uint32_t ci_imask[NIPL]; 159 uint32_t ci_iunmask[NIPL]; 160 161 uint32_t ci_flags; /* flags; see below */ 162 uint32_t ci_ipis; /* interprocessor interrupts pending */ 163 164 uint32_t ci_signature; /* X86 cpuid type (cpuid.1.%eax) */ 165 uint32_t ci_vendor[4]; /* vendor string */ 166 uint32_t ci_max_cpuid; /* cpuid.0:%eax */ 167 uint32_t ci_max_ext_cpuid; /* cpuid.80000000:%eax */ 168 volatile uint32_t ci_lapic_counter; 169 170 uint32_t ci_feat_val[8]; /* X86 CPUID feature bits */ 171 /* [0] basic features cpuid.1:%edx 172 * [1] basic features cpuid.1:%ecx (CPUID2_xxx bits) 173 * [2] extended features cpuid:80000001:%edx 174 * [3] extended features cpuid:80000001:%ecx 175 * [4] VIA padlock features 176 * [5] structured extended features cpuid.7:%ebx 177 * [6] structured extended features cpuid.7:%ecx 178 * [7] structured extended features cpuid.7:%edx 179 */ 180 181 const struct cpu_functions *ci_func; /* start/stop functions */ 182 struct trapframe *ci_ddb_regs; 183 184 u_int ci_cflush_lsize; /* CLFLUSH insn line size */ 185 struct x86_cache_info ci_cinfo[CAI_COUNT]; 186 187 #ifdef PAE 188 uint32_t ci_pae_l3_pdirpa; /* PA of L3 PD */ 189 pd_entry_t * ci_pae_l3_pdir; /* VA pointer to L3 PD */ 190 #endif 191 192 #ifdef SVS 193 pd_entry_t * ci_svs_updir; 194 paddr_t ci_svs_updirpa; 195 paddr_t ci_svs_kpdirpa; 196 kmutex_t ci_svs_mtx; 197 pd_entry_t * ci_svs_rsp0_pte; 198 vaddr_t ci_svs_rsp0; 199 vaddr_t ci_svs_ursp0; 200 vaddr_t ci_svs_krsp0; 201 vaddr_t ci_svs_utls; 202 #endif 203 204 #if defined(XEN) && (defined(PAE) || defined(__x86_64__)) 205 /* Currently active user PGD (can't use rcr3() with Xen) */ 206 pd_entry_t * ci_kpm_pdir; /* per-cpu PMD (va) */ 207 paddr_t ci_kpm_pdirpa; /* per-cpu PMD (pa) */ 208 kmutex_t ci_kpm_mtx; 209 #if defined(__x86_64__) 210 /* per-cpu version of normal_pdes */ 211 pd_entry_t * ci_normal_pdes[3]; /* Ok to hardcode. only for x86_64 && XEN */ 212 paddr_t ci_xen_current_user_pgd; 213 #endif /* __x86_64__ */ 214 #endif /* XEN et.al */ 215 216 #ifdef XEN 217 size_t ci_xpq_idx; 218 #endif 219 220 #ifndef XEN 221 struct evcnt ci_ipi_events[X86_NIPI]; 222 #else /* XEN */ 223 struct evcnt ci_ipi_events[XEN_NIPIS]; 224 evtchn_port_t ci_ipi_evtchn; 225 #endif /* XEN */ 226 227 device_t ci_frequency; /* Frequency scaling technology */ 228 device_t ci_padlock; /* VIA PadLock private storage */ 229 device_t ci_temperature; /* Intel coretemp(4) or equivalent */ 230 device_t ci_vm; /* Virtual machine guest driver */ 231 232 /* 233 * Segmentation-related data. 234 */ 235 union descriptor *ci_gdt; 236 struct cpu_tss *ci_tss; /* Per-cpu TSSes; shared among LWPs */ 237 int ci_tss_sel; /* TSS selector of this cpu */ 238 239 /* 240 * The following two are actually region_descriptors, 241 * but that would pollute the namespace. 242 */ 243 uintptr_t ci_suspend_gdt; 244 uint16_t ci_suspend_gdt_padding; 245 uintptr_t ci_suspend_idt; 246 uint16_t ci_suspend_idt_padding; 247 248 uint16_t ci_suspend_tr; 249 uint16_t ci_suspend_ldt; 250 uintptr_t ci_suspend_fs; 251 uintptr_t ci_suspend_gs; 252 uintptr_t ci_suspend_kgs; 253 uintptr_t ci_suspend_efer; 254 uintptr_t ci_suspend_reg[12]; 255 uintptr_t ci_suspend_cr0; 256 uintptr_t ci_suspend_cr2; 257 uintptr_t ci_suspend_cr3; 258 uintptr_t ci_suspend_cr4; 259 uintptr_t ci_suspend_cr8; 260 261 /* The following must be in a single cache line. */ 262 int ci_want_resched __aligned(64); 263 int ci_padout __aligned(64); 264 }; 265 266 /* 267 * Macros to handle (some) trapframe registers for common x86 code. 268 */ 269 #ifdef __x86_64__ 270 #define X86_TF_RAX(tf) tf->tf_rax 271 #define X86_TF_RDX(tf) tf->tf_rdx 272 #define X86_TF_RSP(tf) tf->tf_rsp 273 #define X86_TF_RIP(tf) tf->tf_rip 274 #define X86_TF_RFLAGS(tf) tf->tf_rflags 275 #else 276 #define X86_TF_RAX(tf) tf->tf_eax 277 #define X86_TF_RDX(tf) tf->tf_edx 278 #define X86_TF_RSP(tf) tf->tf_esp 279 #define X86_TF_RIP(tf) tf->tf_eip 280 #define X86_TF_RFLAGS(tf) tf->tf_eflags 281 #endif 282 283 /* 284 * Processor flag notes: The "primary" CPU has certain MI-defined 285 * roles (mostly relating to hardclock handling); we distinguish 286 * between the processor which booted us, and the processor currently 287 * holding the "primary" role just to give us the flexibility later to 288 * change primaries should we be sufficiently twisted. 289 */ 290 291 #define CPUF_BSP 0x0001 /* CPU is the original BSP */ 292 #define CPUF_AP 0x0002 /* CPU is an AP */ 293 #define CPUF_SP 0x0004 /* CPU is only processor */ 294 #define CPUF_PRIMARY 0x0008 /* CPU is active primary processor */ 295 296 #define CPUF_SYNCTSC 0x0800 /* Synchronize TSC */ 297 #define CPUF_PRESENT 0x1000 /* CPU is present */ 298 #define CPUF_RUNNING 0x2000 /* CPU is running */ 299 #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ 300 #define CPUF_GO 0x8000 /* CPU should start running */ 301 302 #endif /* _KERNEL || __KMEMUSER */ 303 304 #ifdef _KERNEL 305 /* 306 * We statically allocate the CPU info for the primary CPU (or, 307 * the only CPU on uniprocessors), and the primary CPU is the 308 * first CPU on the CPU info list. 309 */ 310 extern struct cpu_info cpu_info_primary; 311 extern struct cpu_info *cpu_info_list; 312 313 #define CPU_INFO_ITERATOR int __unused 314 #define CPU_INFO_FOREACH(cii, ci) ci = cpu_info_list; \ 315 ci != NULL; ci = ci->ci_next 316 317 #define CPU_STARTUP(_ci, _target) ((_ci)->ci_func->start(_ci, _target)) 318 #define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci)) 319 #define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci)) 320 321 #if !defined(__GNUC__) || defined(_MODULE) 322 /* For non-GCC and modules */ 323 struct cpu_info *x86_curcpu(void); 324 void cpu_set_curpri(int); 325 # ifdef __GNUC__ 326 lwp_t *x86_curlwp(void) __attribute__ ((const)); 327 # else 328 lwp_t *x86_curlwp(void); 329 # endif 330 #endif 331 332 #define cpu_number() (cpu_index(curcpu())) 333 334 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 335 336 #define X86_AST_GENERIC 0x01 337 #define X86_AST_PREEMPT 0x02 338 339 #define aston(l, why) ((l)->l_md.md_astpending |= (why)) 340 #define cpu_did_resched(l) ((l)->l_md.md_astpending &= ~X86_AST_PREEMPT) 341 342 void cpu_boot_secondary_processors(void); 343 void cpu_init_idle_lwps(void); 344 void cpu_init_msrs(struct cpu_info *, bool); 345 void cpu_load_pmap(struct pmap *, struct pmap *); 346 void cpu_broadcast_halt(void); 347 void cpu_kick(struct cpu_info *); 348 349 void cpu_pcpuarea_init(struct cpu_info *); 350 void cpu_svs_init(struct cpu_info *); 351 void cpu_speculation_init(struct cpu_info *); 352 353 #define curcpu() x86_curcpu() 354 #define curlwp x86_curlwp() 355 #define curpcb ((struct pcb *)lwp_getpcb(curlwp)) 356 357 /* 358 * Arguments to hardclock, softclock and statclock 359 * encapsulate the previous machine state in an opaque 360 * clockframe; for now, use generic intrframe. 361 */ 362 struct clockframe { 363 struct intrframe cf_if; 364 }; 365 366 /* 367 * Give a profiling tick to the current process when the user profiling 368 * buffer pages are invalid. On the i386, request an ast to send us 369 * through trap(), marking the proc as needing a profiling tick. 370 */ 371 extern void cpu_need_proftick(struct lwp *l); 372 373 /* 374 * Notify the LWP l that it has a signal pending, process as soon as 375 * possible. 376 */ 377 extern void cpu_signotify(struct lwp *); 378 379 /* 380 * We need a machine-independent name for this. 381 */ 382 extern void (*delay_func)(unsigned int); 383 struct timeval; 384 385 #ifndef __HIDE_DELAY 386 #define DELAY(x) (*delay_func)(x) 387 #define delay(x) (*delay_func)(x) 388 #endif 389 390 extern int biosbasemem; 391 extern int biosextmem; 392 extern int cputype; 393 extern int cpuid_level; 394 extern int cpu_class; 395 extern char cpu_brand_string[]; 396 extern int use_pae; 397 398 #ifdef __i386__ 399 #define i386_fpu_present 1 400 int npx586bug1(int, int); 401 extern int i386_fpu_fdivbug; 402 extern int i386_use_fxsave; 403 extern int i386_has_sse; 404 extern int i386_has_sse2; 405 #else 406 #define i386_fpu_present 1 407 #define i386_fpu_fdivbug 0 408 #define i386_use_fxsave 1 409 #define i386_has_sse 1 410 #define i386_has_sse2 1 411 #endif 412 413 extern int x86_fpu_save; 414 #define FPU_SAVE_FSAVE 0 415 #define FPU_SAVE_FXSAVE 1 416 #define FPU_SAVE_XSAVE 2 417 #define FPU_SAVE_XSAVEOPT 3 418 extern unsigned int x86_fpu_save_size; 419 extern uint64_t x86_xsave_features; 420 421 extern void (*x86_cpu_idle)(void); 422 #define cpu_idle() (*x86_cpu_idle)() 423 424 /* machdep.c */ 425 #ifdef i386 426 void cpu_set_tss_gates(struct cpu_info *); 427 #endif 428 void cpu_reset(void); 429 430 /* longrun.c */ 431 u_int tmx86_get_longrun_mode(void); 432 void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 433 void tmx86_init_longrun(void); 434 435 /* identcpu.c */ 436 void cpu_probe(struct cpu_info *); 437 void cpu_identify(struct cpu_info *); 438 void identify_hypervisor(void); 439 440 typedef enum vm_guest { 441 VM_GUEST_NO = 0, 442 VM_GUEST_VM, 443 VM_GUEST_XEN, 444 VM_GUEST_HV, 445 VM_GUEST_VMWARE, 446 VM_GUEST_KVM, 447 VM_LAST 448 } vm_guest_t; 449 extern vm_guest_t vm_guest; 450 451 /* cpu_topology.c */ 452 void x86_cpu_topology(struct cpu_info *); 453 454 /* locore.s */ 455 struct region_descriptor; 456 void lgdt(struct region_descriptor *); 457 #ifdef XEN 458 void lgdt_finish(void); 459 #endif 460 461 struct pcb; 462 void savectx(struct pcb *); 463 void lwp_trampoline(void); 464 #ifdef XEN 465 void startrtclock(void); 466 void xen_delay(unsigned int); 467 void xen_initclocks(void); 468 void xen_suspendclocks(struct cpu_info *); 469 void xen_resumeclocks(struct cpu_info *); 470 #else 471 /* clock.c */ 472 void initrtclock(u_long); 473 void startrtclock(void); 474 void i8254_delay(unsigned int); 475 void i8254_microtime(struct timeval *); 476 void i8254_initclocks(void); 477 #endif 478 479 /* cpu.c */ 480 void cpu_probe_features(struct cpu_info *); 481 482 /* vm_machdep.c */ 483 void cpu_proc_fork(struct proc *, struct proc *); 484 paddr_t kvtop(void *); 485 486 #ifdef USER_LDT 487 /* sys_machdep.h */ 488 int x86_get_ldt(struct lwp *, void *, register_t *); 489 int x86_set_ldt(struct lwp *, void *, register_t *); 490 #endif 491 492 /* isa_machdep.c */ 493 void isa_defaultirq(void); 494 int isa_nmi(void); 495 496 /* consinit.c */ 497 void kgdb_port_init(void); 498 499 /* bus_machdep.c */ 500 void x86_bus_space_init(void); 501 void x86_bus_space_mallocok(void); 502 503 #endif /* _KERNEL */ 504 505 #if defined(_KERNEL) || defined(_KMEMUSER) 506 #include <machine/psl.h> /* Must be after struct cpu_info declaration */ 507 #endif /* _KERNEL || __KMEMUSER */ 508 509 /* 510 * CTL_MACHDEP definitions. 511 */ 512 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 513 #define CPU_BIOSBASEMEM 2 /* int: bios-reported base mem (K) */ 514 #define CPU_BIOSEXTMEM 3 /* int: bios-reported ext. mem (K) */ 515 /* CPU_NKPDE 4 obsolete: int: number of kernel PDEs */ 516 #define CPU_BOOTED_KERNEL 5 /* string: booted kernel name */ 517 #define CPU_DISKINFO 6 /* struct disklist *: 518 * disk geometry information */ 519 #define CPU_FPU_PRESENT 7 /* int: FPU is present */ 520 #define CPU_OSFXSR 8 /* int: OS uses FXSAVE/FXRSTOR */ 521 #define CPU_SSE 9 /* int: OS/CPU supports SSE */ 522 #define CPU_SSE2 10 /* int: OS/CPU supports SSE2 */ 523 #define CPU_TMLR_MODE 11 /* int: longrun mode 524 * 0: minimum frequency 525 * 1: economy 526 * 2: performance 527 * 3: maximum frequency 528 */ 529 #define CPU_TMLR_FREQUENCY 12 /* int: current frequency */ 530 #define CPU_TMLR_VOLTAGE 13 /* int: current voltage */ 531 #define CPU_TMLR_PERCENTAGE 14 /* int: current clock percentage */ 532 #define CPU_FPU_SAVE 15 /* int: FPU Instructions layout 533 * to use this, CPU_OSFXSR must be true 534 * 0: FSAVE 535 * 1: FXSAVE 536 * 2: XSAVE 537 * 3: XSAVEOPT 538 */ 539 #define CPU_FPU_SAVE_SIZE 16 /* int: FPU Instruction layout size */ 540 #define CPU_XSAVE_FEATURES 17 /* quad: XSAVE features */ 541 542 #define CPU_MAXID 18 /* number of valid machdep ids */ 543 544 /* 545 * Structure for CPU_DISKINFO sysctl call. 546 * XXX this should be somewhere else. 547 */ 548 #define MAX_BIOSDISKS 16 549 550 struct disklist { 551 int dl_nbiosdisks; /* number of bios disks */ 552 int dl_unused; 553 struct biosdisk_info { 554 int bi_dev; /* BIOS device # (0x80 ..) */ 555 int bi_cyl; /* cylinders on disk */ 556 int bi_head; /* heads per track */ 557 int bi_sec; /* sectors per track */ 558 uint64_t bi_lbasecs; /* total sec. (iff ext13) */ 559 #define BIFLAG_INVALID 0x01 560 #define BIFLAG_EXTINT13 0x02 561 int bi_flags; 562 int bi_unused; 563 } dl_biosdisks[MAX_BIOSDISKS]; 564 565 int dl_nnativedisks; /* number of native disks */ 566 struct nativedisk_info { 567 char ni_devname[16]; /* native device name */ 568 int ni_nmatches; /* # of matches w/ BIOS */ 569 int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */ 570 } dl_nativedisks[1]; /* actually longer */ 571 }; 572 #endif /* !_X86_CPU_H_ */ 573
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