cpufunc.h revision 1.8 1 /* $NetBSD: cpufunc.h,v 1.8 2008/04/30 00:16:30 cegger Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 2007 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum, and by Andrew Doran.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef _X86_CPUFUNC_H_
33 #define _X86_CPUFUNC_H_
34
35 /*
36 * Functions to provide access to x86-specific instructions.
37 */
38
39 #include <sys/cdefs.h>
40 #include <sys/types.h>
41
42 #include <machine/segments.h>
43 #include <machine/specialreg.h>
44
45 #ifdef _KERNEL
46
47 void x86_pause(void);
48 void x86_lfence(void);
49 void x86_sfence(void);
50 void x86_mfence(void);
51 void x86_flush(void);
52 void x86_patch(void);
53 void invlpg(vaddr_t);
54 void lidt(struct region_descriptor *);
55 void lldt(u_short);
56 void ltr(u_short);
57 void lcr0(u_long);
58 u_long rcr0(void);
59 void lcr2(vaddr_t);
60 vaddr_t rcr2(void);
61 void lcr3(vaddr_t);
62 vaddr_t rcr3(void);
63 void lcr4(vaddr_t);
64 vaddr_t rcr4(void);
65 void lcr8(vaddr_t);
66 vaddr_t rcr8(void);
67 void tlbflush(void);
68 void tlbflushg(void);
69 void dr0(void *, uint32_t, uint32_t, uint32_t);
70 vaddr_t rdr6(void);
71 void ldr6(vaddr_t);
72 void wbinvd(void);
73 void breakpoint(void);
74 void x86_hlt(void);
75 void x86_stihlt(void);
76 u_int x86_getss(void);
77 void fldcw(void *);
78 void fnclex(void);
79 void fninit(void);
80 void fnsave(void *);
81 void fnstcw(void *);
82 void fnstsw(void *);
83 void fp_divide_by_0(void);
84 void frstor(void *);
85 void fwait(void);
86 void clts(void);
87 void stts(void);
88 void fldummy(const double *);
89 void fxsave(void *);
90 void fxrstor(void *);
91 void x86_monitor(const void *, uint32_t, uint32_t);
92 void x86_mwait(uint32_t, uint32_t);
93 void x86_ldmxcsr(void *);
94 #define x86_cpuid(a,b) x86_cpuid2((a),0,(b))
95 void x86_cpuid2(unsigned, unsigned, unsigned *);
96
97 /* Use read_psl, write_psl when saving and restoring interrupt state. */
98 void x86_disable_intr(void);
99 void x86_enable_intr(void);
100 u_long x86_read_psl(void);
101 void x86_write_psl(u_long);
102
103 /* Use read_flags, write_flags to adjust other members of %eflags. */
104 u_long x86_read_flags(void);
105 void x86_write_flags(u_long);
106
107 /*
108 * Some of the undocumented AMD64 MSRs need a 'passcode' to access.
109 *
110 * See LinuxBIOSv2: src/cpu/amd/model_fxx/model_fxx_init.c
111 */
112
113 #define OPTERON_MSR_PASSCODE 0x9c5a203aU
114
115 uint64_t rdmsr(u_int);
116 uint64_t rdmsr_locked(u_int, u_int);
117 uint64_t rdtsc(void);
118 uint64_t rdpmc(u_int);
119 void wrmsr(u_int, uint64_t);
120 void wrmsr_locked(u_int, u_int, uint64_t);
121
122 #endif /* _KERNEL */
123
124 #endif /* !_X86_CPUFUNC_H_ */
125