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dbregs.h revision 1.4.14.1 
      1 /*	$NetBSD: dbregs.h,v 1.4.14.1 2018/07/28 04:37:42 pgoyette Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2016 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     17  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     26  * POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #ifndef	_X86_DBREGS_H_
     30 #define	_X86_DBREGS_H_
     31 
     32 #include <sys/param.h>
     33 #include <sys/types.h>
     34 #include <machine/reg.h>
     35 
     36 /*
     37  * CPU Debug Status Register (DR6)
     38  *
     39  * Reserved bits: 4-12 and on x86_64 32-64
     40  */
     41 #define X86_DR6_DR0_BREAKPOINT_CONDITION_DETECTED	__BIT(0)
     42 #define X86_DR6_DR1_BREAKPOINT_CONDITION_DETECTED	__BIT(1)
     43 #define X86_DR6_DR2_BREAKPOINT_CONDITION_DETECTED	__BIT(2)
     44 #define X86_DR6_DR3_BREAKPOINT_CONDITION_DETECTED	__BIT(3)
     45 #define X86_DR6_DEBUG_REGISTER_ACCESS_DETECTED		__BIT(13)
     46 #define X86_DR6_SINGLE_STEP				__BIT(14)
     47 #define X86_DR6_TASK_SWITCH				__BIT(15)
     48 
     49 /*
     50  * CPU Debug Control Register (DR7)
     51  *
     52  * LOCAL_EXACT_BREAKPOINT and GLOBAL_EXACT_BREAKPOINT are no longer used
     53  * since the P6 processor family - portable code should set these bits
     54  * unconditionally in order to get exact breakpoints.
     55  *
     56  * Reserved bits: 10, 12, 14-15 and on x86_64 32-64.
     57  */
     58 #define X86_DR7_LOCAL_DR0_BREAKPOINT		__BIT(0)
     59 #define X86_DR7_GLOBAL_DR0_BREAKPOINT		__BIT(1)
     60 #define X86_DR7_LOCAL_DR1_BREAKPOINT		__BIT(2)
     61 #define X86_DR7_GLOBAL_DR1_BREAKPOINT		__BIT(3)
     62 #define X86_DR7_LOCAL_DR2_BREAKPOINT		__BIT(4)
     63 #define X86_DR7_GLOBAL_DR2_BREAKPOINT		__BIT(5)
     64 #define X86_DR7_LOCAL_DR3_BREAKPOINT		__BIT(6)
     65 #define X86_DR7_GLOBAL_DR3_BREAKPOINT		__BIT(7)
     66 #define X86_DR7_LOCAL_EXACT_BREAKPOINT		__BIT(8)
     67 #define X86_DR7_GLOBAL_EXACT_BREAKPOINT		__BIT(9)
     68 #define X86_DR7_RESTRICTED_TRANSACTIONAL_MEMORY	__BIT(11)
     69 #define X86_DR7_GENERAL_DETECT_ENABLE		__BIT(13)
     70 
     71 #define X86_DR7_DR0_CONDITION_MASK		__BITS(16, 17)
     72 #define X86_DR7_DR0_LENGTH_MASK			__BITS(18, 19)
     73 #define X86_DR7_DR1_CONDITION_MASK		__BITS(20, 21)
     74 #define X86_DR7_DR1_LENGTH_MASK			__BITS(22, 23)
     75 #define X86_DR7_DR2_CONDITION_MASK		__BITS(24, 25)
     76 #define X86_DR7_DR2_LENGTH_MASK			__BITS(26, 27)
     77 #define X86_DR7_DR3_CONDITION_MASK		__BITS(28, 29)
     78 #define X86_DR7_DR3_LENGTH_MASK			__BITS(30, 31)
     79 
     80 /*
     81  * X86_DR7_CONDITION_IO_READWRITE is currently unused. It requires DE
     82  * (debug extension) flag in control register CR4 set, and not all CPUs
     83  * support it.
     84  */
     85 enum x86_dr7_condition {
     86 	X86_DR7_CONDITION_EXECUTION		= 0x0,
     87 	X86_DR7_CONDITION_DATA_WRITE		= 0x1,
     88 	X86_DR7_CONDITION_IO_READWRITE		= 0x2,
     89 	X86_DR7_CONDITION_DATA_READWRITE	= 0x3
     90 };
     91 
     92 /*
     93  * 0x2 is currently unimplemented - it reflects 8 bytes on modern CPUs.
     94  */
     95 enum x86_dr7_length {
     96 	X86_DR7_LENGTH_BYTE		= 0x0,
     97 	X86_DR7_LENGTH_TWOBYTES		= 0x1,
     98 	/* 0x2 undefined */
     99 	X86_DR7_LENGTH_FOURBYTES	= 0x3
    100 };
    101 
    102 /*
    103  * The number of available watchpoint/breakpoint registers available since
    104  * Intel 80386. New CPUs (x86_64) ship with up to 16 Debug Registers but they
    105  * still offer the same number of watchpoints/breakpoints.
    106  */
    107 #define X86_DBREGS	4
    108 
    109 void x86_dbregs_init(void);
    110 void x86_dbregs_clear(struct lwp *);
    111 void x86_dbregs_abandon(struct lwp *);
    112 void x86_dbregs_read(struct lwp *, struct dbreg *);
    113 void x86_dbregs_store_dr6(struct lwp *);
    114 int x86_dbregs_user_trap(void);
    115 int x86_dbregs_validate(const struct dbreg *);
    116 void x86_dbregs_write(struct lwp *, const struct dbreg *);
    117 void x86_dbregs_switch(struct lwp *, struct lwp *);
    118 
    119 #endif /* !_X86_DBREGS_H_ */
    120