intr.h revision 1.16
1 /* $NetBSD: intr.h,v 1.16 2005/10/28 10:34:18 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _X86_INTR_H_ 40 #define _X86_INTR_H_ 41 42 #ifdef _KERNEL_OPT 43 #include "opt_multiprocessor.h" 44 #endif 45 46 #include <machine/intrdefs.h> 47 48 #ifndef _LOCORE 49 #include <machine/cpu.h> 50 #include <machine/pic.h> 51 52 /* 53 * Struct describing an interrupt source for a CPU. struct cpu_info 54 * has an array of MAX_INTR_SOURCES of these. The index in the array 55 * is equal to the stub number of the stubcode as present in vector.s 56 * 57 * The primary CPU's array of interrupt sources has its first 16 58 * entries reserved for legacy ISA irq handlers. This means that 59 * they have a 1:1 mapping for arrayindex:irq_num. This is not 60 * true for interrupts that come in through IO APICs, to find 61 * their source, go through ci->ci_isources[index].is_pic 62 * 63 * It's possible to always maintain a 1:1 mapping, but that means 64 * limiting the total number of interrupt sources to MAX_INTR_SOURCES 65 * (32), instead of 32 per CPU. It also would mean that having multiple 66 * IO APICs which deliver interrupts from an equal pin number would 67 * overlap if they were to be sent to the same CPU. 68 */ 69 70 struct intrstub { 71 void *ist_entry; 72 void *ist_recurse; 73 void *ist_resume; 74 }; 75 76 struct intrsource { 77 int is_maxlevel; /* max. IPL for this source */ 78 int is_pin; /* IRQ for legacy; pin for IO APIC */ 79 struct intrhand *is_handlers; /* handler chain */ 80 struct pic *is_pic; /* originating PIC */ 81 void *is_recurse; /* entry for spllower */ 82 void *is_resume; /* entry for doreti */ 83 struct evcnt is_evcnt; /* interrupt counter */ 84 char is_evname[32]; /* event counter name */ 85 int is_flags; /* see below */ 86 int is_type; /* level, edge */ 87 int is_idtvec; 88 int is_minlevel; 89 }; 90 91 #define IS_LEGACY 0x0001 /* legacy ISA irq source */ 92 #define IS_IPI 0x0002 93 #define IS_LOG 0x0004 94 95 96 /* 97 * Interrupt handler chains. *_intr_establish() insert a handler into 98 * the list. The handler is called with its (single) argument. 99 */ 100 101 struct intrhand { 102 int (*ih_fun)(void *); 103 void *ih_arg; 104 int ih_level; 105 int (*ih_realfun)(void *); 106 void *ih_realarg; 107 struct intrhand *ih_next; 108 int ih_pin; 109 int ih_slot; 110 struct cpu_info *ih_cpu; 111 }; 112 113 #define IMASK(ci,level) (ci)->ci_imask[(level)] 114 #define IUNMASK(ci,level) (ci)->ci_iunmask[(level)] 115 116 extern void Xspllower(int); 117 118 static __inline int splraise(int); 119 static __inline void spllower(int); 120 static __inline void softintr(int); 121 122 /* 123 * Convert spl level to local APIC level 124 */ 125 #define APIC_LEVEL(l) ((l) << 4) 126 127 /* 128 * Add a mask to cpl, and return the old value of cpl. 129 */ 130 static __inline int 131 splraise(int nlevel) 132 { 133 int olevel; 134 struct cpu_info *ci = curcpu(); 135 136 olevel = ci->ci_ilevel; 137 if (nlevel > olevel) 138 ci->ci_ilevel = nlevel; 139 __insn_barrier(); 140 return (olevel); 141 } 142 143 /* 144 * Restore a value to cpl (unmasking interrupts). If any unmasked 145 * interrupts are pending, call Xspllower() to process them. 146 */ 147 static __inline void 148 spllower(int nlevel) 149 { 150 struct cpu_info *ci = curcpu(); 151 u_int32_t imask; 152 u_long psl; 153 154 __insn_barrier(); 155 156 imask = IUNMASK(ci, nlevel); 157 psl = read_psl(); 158 disable_intr(); 159 if (ci->ci_ipending & imask) { 160 Xspllower(nlevel); 161 /* Xspllower does enable_intr() */ 162 } else { 163 ci->ci_ilevel = nlevel; 164 write_psl(psl); 165 } 166 } 167 168 /* 169 * Hardware interrupt masks 170 */ 171 #define splbio() splraise(IPL_BIO) 172 #define splnet() splraise(IPL_NET) 173 #define spltty() splraise(IPL_TTY) 174 #define spllpt() spltty() 175 #define splaudio() splraise(IPL_AUDIO) 176 #define splclock() splraise(IPL_CLOCK) 177 #define splstatclock() splclock() 178 #define splserial() splraise(IPL_SERIAL) 179 #define splipi() splraise(IPL_IPI) 180 181 #define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x)) 182 183 /* 184 * Software interrupt masks 185 * 186 * NOTE: spllowersoftclock() is used by hardclock() to lower the priority from 187 * clock to softclock before it calls softclock(). 188 */ 189 #define spllowersoftclock() spllower(IPL_SOFTCLOCK) 190 191 #define splsoftclock() splraise(IPL_SOFTCLOCK) 192 #define splsoftnet() splraise(IPL_SOFTNET) 193 #define splsoftserial() splraise(IPL_SOFTSERIAL) 194 195 /* 196 * Miscellaneous 197 */ 198 #define splvm() splraise(IPL_VM) 199 #define splhigh() splraise(IPL_HIGH) 200 #define spl0() spllower(IPL_NONE) 201 #define splsched() splraise(IPL_SCHED) 202 #define spllock() splhigh() 203 #define splx(x) spllower(x) 204 205 /* 206 * Software interrupt registration 207 * 208 * We hand-code this to ensure that it's atomic. 209 * 210 * XXX always scheduled on the current CPU. 211 */ 212 static __inline void 213 softintr(int sir) 214 { 215 struct cpu_info *ci = curcpu(); 216 217 __asm __volatile("lock ; orl %1, %0" : 218 "=m"(ci->ci_ipending) : "ir" (1 << sir)); 219 } 220 221 /* 222 * XXX 223 */ 224 #define setsoftnet() softintr(SIR_NET) 225 226 /* 227 * Stub declarations. 228 */ 229 230 extern void Xsoftclock(void); 231 extern void Xsoftnet(void); 232 extern void Xsoftserial(void); 233 234 extern struct intrstub i8259_stubs[]; 235 extern struct intrstub ioapic_edge_stubs[]; 236 extern struct intrstub ioapic_level_stubs[]; 237 238 struct cpu_info; 239 240 extern char idt_allocmap[]; 241 242 struct pcibus_attach_args; 243 244 void intr_default_setup(void); 245 int x86_nmi(void); 246 void intr_calculatemasks(struct cpu_info *); 247 int intr_allocate_slot_cpu(struct cpu_info *, struct pic *, int, int *); 248 int intr_allocate_slot(struct pic *, int, int, int, struct cpu_info **, int *, 249 int *); 250 void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *); 251 void intr_disestablish(struct intrhand *); 252 void intr_add_pcibus(struct pcibus_attach_args *); 253 const char *intr_string(int); 254 void cpu_intr_init(struct cpu_info *); 255 int intr_find_mpmapping(int, int, int *); 256 #ifdef INTRDEBUG 257 void intr_printconfig(void); 258 #endif 259 260 #ifdef MULTIPROCESSOR 261 int x86_send_ipi(struct cpu_info *, int); 262 void x86_broadcast_ipi(int); 263 void x86_multicast_ipi(int, int); 264 void x86_ipi_handler(void); 265 void x86_intlock(struct intrframe *); 266 void x86_intunlock(struct intrframe *); 267 void x86_softintlock(void); 268 void x86_softintunlock(void); 269 270 extern void (*ipifunc[X86_NIPI])(struct cpu_info *); 271 #endif 272 273 #endif /* !_LOCORE */ 274 275 /* 276 * Generic software interrupt support. 277 */ 278 279 #define X86_SOFTINTR_SOFTCLOCK 0 280 #define X86_SOFTINTR_SOFTNET 1 281 #define X86_SOFTINTR_SOFTSERIAL 2 282 #define X86_NSOFTINTR 3 283 284 #ifndef _LOCORE 285 #include <sys/queue.h> 286 287 struct x86_soft_intrhand { 288 TAILQ_ENTRY(x86_soft_intrhand) 289 sih_q; 290 struct x86_soft_intr *sih_intrhead; 291 void (*sih_fn)(void *); 292 void *sih_arg; 293 int sih_pending; 294 }; 295 296 struct x86_soft_intr { 297 TAILQ_HEAD(, x86_soft_intrhand) 298 softintr_q; 299 int softintr_ssir; 300 struct simplelock softintr_slock; 301 }; 302 303 #define x86_softintr_lock(si, s) \ 304 do { \ 305 (s) = splhigh(); \ 306 simple_lock(&si->softintr_slock); \ 307 } while (/*CONSTCOND*/ 0) 308 309 #define x86_softintr_unlock(si, s) \ 310 do { \ 311 simple_unlock(&si->softintr_slock); \ 312 splx((s)); \ 313 } while (/*CONSTCOND*/ 0) 314 315 void *softintr_establish(int, void (*)(void *), void *); 316 void softintr_disestablish(void *); 317 void softintr_init(void); 318 void softintr_dispatch(int); 319 320 #define softintr_schedule(arg) \ 321 do { \ 322 struct x86_soft_intrhand *__sih = (arg); \ 323 struct x86_soft_intr *__si = __sih->sih_intrhead; \ 324 int __s; \ 325 \ 326 x86_softintr_lock(__si, __s); \ 327 if (__sih->sih_pending == 0) { \ 328 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 329 __sih->sih_pending = 1; \ 330 softintr(__si->softintr_ssir); \ 331 } \ 332 x86_softintr_unlock(__si, __s); \ 333 } while (/*CONSTCOND*/ 0) 334 #endif /* _LOCORE */ 335 336 #endif /* !_X86_INTR_H_ */ 337
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