intr.h revision 1.20
1 /* $NetBSD: intr.h,v 1.20 2006/02/16 20:17:15 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _X86_INTR_H_ 40 #define _X86_INTR_H_ 41 42 #ifdef _KERNEL_OPT 43 #include "opt_multiprocessor.h" 44 #endif 45 46 #include <machine/intrdefs.h> 47 48 #ifndef _LOCORE 49 #include <machine/cpu.h> 50 #include <machine/pic.h> 51 52 /* 53 * Struct describing an interrupt source for a CPU. struct cpu_info 54 * has an array of MAX_INTR_SOURCES of these. The index in the array 55 * is equal to the stub number of the stubcode as present in vector.s 56 * 57 * The primary CPU's array of interrupt sources has its first 16 58 * entries reserved for legacy ISA irq handlers. This means that 59 * they have a 1:1 mapping for arrayindex:irq_num. This is not 60 * true for interrupts that come in through IO APICs, to find 61 * their source, go through ci->ci_isources[index].is_pic 62 * 63 * It's possible to always maintain a 1:1 mapping, but that means 64 * limiting the total number of interrupt sources to MAX_INTR_SOURCES 65 * (32), instead of 32 per CPU. It also would mean that having multiple 66 * IO APICs which deliver interrupts from an equal pin number would 67 * overlap if they were to be sent to the same CPU. 68 */ 69 70 struct intrstub { 71 void *ist_entry; 72 void *ist_recurse; 73 void *ist_resume; 74 }; 75 76 struct intrsource { 77 int is_maxlevel; /* max. IPL for this source */ 78 int is_pin; /* IRQ for legacy; pin for IO APIC */ 79 struct intrhand *is_handlers; /* handler chain */ 80 struct pic *is_pic; /* originating PIC */ 81 void *is_recurse; /* entry for spllower */ 82 void *is_resume; /* entry for doreti */ 83 struct evcnt is_evcnt; /* interrupt counter */ 84 char is_evname[32]; /* event counter name */ 85 int is_flags; /* see below */ 86 int is_type; /* level, edge */ 87 int is_idtvec; 88 int is_minlevel; 89 }; 90 91 #define IS_LEGACY 0x0001 /* legacy ISA irq source */ 92 #define IS_IPI 0x0002 93 #define IS_LOG 0x0004 94 95 96 /* 97 * Interrupt handler chains. *_intr_establish() insert a handler into 98 * the list. The handler is called with its (single) argument. 99 */ 100 101 struct intrhand { 102 int (*ih_fun)(void *); 103 void *ih_arg; 104 int ih_level; 105 int (*ih_realfun)(void *); 106 void *ih_realarg; 107 struct intrhand *ih_next; 108 int ih_pin; 109 int ih_slot; 110 struct cpu_info *ih_cpu; 111 }; 112 113 #define IMASK(ci,level) (ci)->ci_imask[(level)] 114 #define IUNMASK(ci,level) (ci)->ci_iunmask[(level)] 115 116 extern void Xspllower(int); 117 118 static __inline int splraise(int); 119 static __inline void spllower(int); 120 static __inline void softintr(int); 121 122 /* 123 * Convert spl level to local APIC level 124 */ 125 #define APIC_LEVEL(l) ((l) << 4) 126 127 /* 128 * Add a mask to cpl, and return the old value of cpl. 129 */ 130 static __inline int 131 splraise(int nlevel) 132 { 133 int olevel; 134 struct cpu_info *ci = curcpu(); 135 136 olevel = ci->ci_ilevel; 137 if (nlevel > olevel) 138 ci->ci_ilevel = nlevel; 139 __insn_barrier(); 140 return (olevel); 141 } 142 143 /* 144 * Restore a value to cpl (unmasking interrupts). If any unmasked 145 * interrupts are pending, call Xspllower() to process them. 146 */ 147 static __inline void 148 spllower(int nlevel) 149 { 150 struct cpu_info *ci = curcpu(); 151 u_int32_t imask; 152 u_long psl; 153 154 __insn_barrier(); 155 156 imask = IUNMASK(ci, nlevel); 157 psl = read_psl(); 158 disable_intr(); 159 if (ci->ci_ipending & imask) { 160 Xspllower(nlevel); 161 /* Xspllower does enable_intr() */ 162 } else { 163 ci->ci_ilevel = nlevel; 164 write_psl(psl); 165 } 166 } 167 168 #define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x)) 169 170 /* 171 * Software interrupt masks 172 * 173 * NOTE: spllowersoftclock() is used by hardclock() to lower the priority from 174 * clock to softclock before it calls softclock(). 175 */ 176 #define spllowersoftclock() spllower(IPL_SOFTCLOCK) 177 178 /* 179 * Miscellaneous 180 */ 181 #define spl0() spllower(IPL_NONE) 182 #define splraiseipl(x) splraise(x) 183 #define splx(x) spllower(x) 184 185 #include <sys/spl.h> 186 187 /* 188 * Software interrupt registration 189 * 190 * We hand-code this to ensure that it's atomic. 191 * 192 * XXX always scheduled on the current CPU. 193 */ 194 static __inline void 195 softintr(int sir) 196 { 197 struct cpu_info *ci = curcpu(); 198 199 __asm volatile("lock ; orl %1, %0" : 200 "=m"(ci->ci_ipending) : "ir" (1 << sir)); 201 } 202 203 /* 204 * XXX 205 */ 206 #define setsoftnet() softintr(SIR_NET) 207 208 /* 209 * Stub declarations. 210 */ 211 212 extern void Xsoftclock(void); 213 extern void Xsoftnet(void); 214 extern void Xsoftserial(void); 215 216 extern struct intrstub i8259_stubs[]; 217 extern struct intrstub ioapic_edge_stubs[]; 218 extern struct intrstub ioapic_level_stubs[]; 219 220 struct cpu_info; 221 222 extern char idt_allocmap[]; 223 224 struct pcibus_attach_args; 225 226 void intr_default_setup(void); 227 int x86_nmi(void); 228 void intr_calculatemasks(struct cpu_info *); 229 int intr_allocate_slot_cpu(struct cpu_info *, struct pic *, int, int *); 230 int intr_allocate_slot(struct pic *, int, int, int, struct cpu_info **, int *, 231 int *); 232 void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *); 233 void intr_disestablish(struct intrhand *); 234 void intr_add_pcibus(struct pcibus_attach_args *); 235 const char *intr_string(int); 236 void cpu_intr_init(struct cpu_info *); 237 int intr_find_mpmapping(int, int, int *); 238 #ifdef INTRDEBUG 239 void intr_printconfig(void); 240 #endif 241 242 #ifdef MULTIPROCESSOR 243 int x86_send_ipi(struct cpu_info *, int); 244 void x86_broadcast_ipi(int); 245 void x86_multicast_ipi(int, int); 246 void x86_ipi_handler(void); 247 void x86_intlock(struct intrframe *); 248 void x86_intunlock(struct intrframe *); 249 void x86_softintlock(void); 250 void x86_softintunlock(void); 251 252 extern void (*ipifunc[X86_NIPI])(struct cpu_info *); 253 #endif 254 255 #endif /* !_LOCORE */ 256 257 /* 258 * Generic software interrupt support. 259 */ 260 261 #define X86_SOFTINTR_SOFTCLOCK 0 262 #define X86_SOFTINTR_SOFTNET 1 263 #define X86_SOFTINTR_SOFTSERIAL 2 264 #define X86_NSOFTINTR 3 265 266 #ifndef _LOCORE 267 #include <sys/queue.h> 268 269 struct x86_soft_intrhand { 270 TAILQ_ENTRY(x86_soft_intrhand) 271 sih_q; 272 struct x86_soft_intr *sih_intrhead; 273 void (*sih_fn)(void *); 274 void *sih_arg; 275 int sih_pending; 276 }; 277 278 struct x86_soft_intr { 279 TAILQ_HEAD(, x86_soft_intrhand) 280 softintr_q; 281 int softintr_ssir; 282 struct simplelock softintr_slock; 283 }; 284 285 #define x86_softintr_lock(si, s) \ 286 do { \ 287 (s) = splhigh(); \ 288 simple_lock(&si->softintr_slock); \ 289 } while (/*CONSTCOND*/ 0) 290 291 #define x86_softintr_unlock(si, s) \ 292 do { \ 293 simple_unlock(&si->softintr_slock); \ 294 splx((s)); \ 295 } while (/*CONSTCOND*/ 0) 296 297 void *softintr_establish(int, void (*)(void *), void *); 298 void softintr_disestablish(void *); 299 void softintr_init(void); 300 void softintr_dispatch(int); 301 302 #define softintr_schedule(arg) \ 303 do { \ 304 struct x86_soft_intrhand *__sih = (arg); \ 305 struct x86_soft_intr *__si = __sih->sih_intrhead; \ 306 int __s; \ 307 \ 308 x86_softintr_lock(__si, __s); \ 309 if (__sih->sih_pending == 0) { \ 310 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 311 __sih->sih_pending = 1; \ 312 softintr(__si->softintr_ssir); \ 313 } \ 314 x86_softintr_unlock(__si, __s); \ 315 } while (/*CONSTCOND*/ 0) 316 #endif /* _LOCORE */ 317 318 #endif /* !_X86_INTR_H_ */ 319
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