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intr.h revision 1.31 
      1 /*	$NetBSD: intr.h,v 1.31 2008/01/21 02:56:14 dyoung Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1998, 2001, 2006, 2007 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Charles M. Hannum, and by Jason R. Thorpe.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *        This product includes software developed by the NetBSD
     21  *        Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 #ifndef _X86_INTR_H_
     40 #define _X86_INTR_H_
     41 
     42 #define	__HAVE_FAST_SOFTINTS
     43 
     44 #include <machine/intrdefs.h>
     45 
     46 #ifndef _LOCORE
     47 #include <machine/pic.h>
     48 
     49 /*
     50  * Struct describing an interrupt source for a CPU. struct cpu_info
     51  * has an array of MAX_INTR_SOURCES of these. The index in the array
     52  * is equal to the stub number of the stubcode as present in vector.s
     53  *
     54  * The primary CPU's array of interrupt sources has its first 16
     55  * entries reserved for legacy ISA irq handlers. This means that
     56  * they have a 1:1 mapping for arrayindex:irq_num. This is not
     57  * true for interrupts that come in through IO APICs, to find
     58  * their source, go through ci->ci_isources[index].is_pic
     59  *
     60  * It's possible to always maintain a 1:1 mapping, but that means
     61  * limiting the total number of interrupt sources to MAX_INTR_SOURCES
     62  * (32), instead of 32 per CPU. It also would mean that having multiple
     63  * IO APICs which deliver interrupts from an equal pin number would
     64  * overlap if they were to be sent to the same CPU.
     65  */
     66 
     67 struct intrstub {
     68 	void *ist_entry;
     69 	void *ist_recurse;
     70 	void *ist_resume;
     71 };
     72 
     73 struct intrsource {
     74 	int is_maxlevel;		/* max. IPL for this source */
     75 	int is_pin;			/* IRQ for legacy; pin for IO APIC */
     76 	struct intrhand *is_handlers;	/* handler chain */
     77 	struct pic *is_pic;		/* originating PIC */
     78 	void *is_recurse;		/* entry for spllower */
     79 	void *is_resume;		/* entry for doreti */
     80 	lwp_t *is_lwp;			/* for soft interrupts */
     81 	struct evcnt is_evcnt;		/* interrupt counter */
     82 	int is_flags;			/* see below */
     83 	int is_type;			/* level, edge */
     84 	int is_idtvec;
     85 	int is_minlevel;
     86 	char is_evname[32];		/* event counter name */
     87 };
     88 
     89 #define IS_LEGACY	0x0001		/* legacy ISA irq source */
     90 #define IS_IPI		0x0002
     91 #define IS_LOG		0x0004
     92 
     93 /*
     94  * Interrupt handler chains.  *_intr_establish() insert a handler into
     95  * the list.  The handler is called with its (single) argument.
     96  */
     97 
     98 struct intrhand {
     99 	int	(*ih_fun)(void *);
    100 	void	*ih_arg;
    101 	int	ih_level;
    102 	int	(*ih_realfun)(void *);
    103 	void	*ih_realarg;
    104 	struct	intrhand *ih_next;
    105 	int	ih_pin;
    106 	int	ih_slot;
    107 	struct cpu_info *ih_cpu;
    108 };
    109 
    110 #define IMASK(ci,level) (ci)->ci_imask[(level)]
    111 #define IUNMASK(ci,level) (ci)->ci_iunmask[(level)]
    112 
    113 void Xspllower(int);
    114 void spllower(int);
    115 int splraise(int);
    116 void softintr(int);
    117 
    118 /*
    119  * Convert spl level to local APIC level
    120  */
    121 
    122 #define APIC_LEVEL(l)   ((l) << 4)
    123 
    124 /*
    125  * Miscellaneous
    126  */
    127 
    128 #define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x))
    129 #define	spl0()		spllower(IPL_NONE)
    130 #define	splx(x)		spllower(x)
    131 
    132 typedef uint8_t ipl_t;
    133 typedef struct {
    134 	ipl_t _ipl;
    135 } ipl_cookie_t;
    136 
    137 static inline ipl_cookie_t
    138 makeiplcookie(ipl_t ipl)
    139 {
    140 
    141 	return (ipl_cookie_t){._ipl = ipl};
    142 }
    143 
    144 static inline int
    145 splraiseipl(ipl_cookie_t icookie)
    146 {
    147 
    148 	return splraise(icookie._ipl);
    149 }
    150 
    151 #include <sys/spl.h>
    152 
    153 /*
    154  * Stub declarations.
    155  */
    156 
    157 void Xsoftintr(void);
    158 
    159 extern struct intrstub i8259_stubs[];
    160 extern struct intrstub ioapic_edge_stubs[];
    161 extern struct intrstub ioapic_level_stubs[];
    162 
    163 struct cpu_info;
    164 
    165 struct pcibus_attach_args;
    166 
    167 void intr_default_setup(void);
    168 void *nmi_establish(int (*)(void *), void *);
    169 bool nmi_disestablish(void *);
    170 int nmi_dispatch(void);
    171 int x86_nmi(void);
    172 void intr_calculatemasks(struct cpu_info *);
    173 int intr_allocate_slot_cpu(struct cpu_info *, struct pic *, int, int *);
    174 int intr_allocate_slot(struct pic *, int, int, int, struct cpu_info **, int *,
    175 		       int *);
    176 void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *);
    177 void intr_disestablish(struct intrhand *);
    178 void intr_add_pcibus(struct pcibus_attach_args *);
    179 const char *intr_string(int);
    180 void cpu_intr_init(struct cpu_info *);
    181 int intr_find_mpmapping(int, int, int *);
    182 struct pic *intr_findpic(int);
    183 #ifdef INTRDEBUG
    184 void intr_printconfig(void);
    185 #endif
    186 
    187 int x86_send_ipi(struct cpu_info *, int);
    188 void x86_broadcast_ipi(int);
    189 void x86_multicast_ipi(int, int);
    190 void x86_ipi_handler(void);
    191 
    192 extern void (*ipifunc[X86_NIPI])(struct cpu_info *);
    193 
    194 #endif /* !_LOCORE */
    195 
    196 #endif /* !_X86_INTR_H_ */
    197