intr.h revision 1.35
1 /* $NetBSD: intr.h,v 1.35 2008/05/30 19:03:10 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _X86_INTR_H_ 33 #define _X86_INTR_H_ 34 35 #define __HAVE_FAST_SOFTINTS 36 #define __HAVE_PREEMPTION 37 38 #include <machine/intrdefs.h> 39 40 #ifndef _LOCORE 41 #include <machine/pic.h> 42 43 /* 44 * Struct describing an interrupt source for a CPU. struct cpu_info 45 * has an array of MAX_INTR_SOURCES of these. The index in the array 46 * is equal to the stub number of the stubcode as present in vector.s 47 * 48 * The primary CPU's array of interrupt sources has its first 16 49 * entries reserved for legacy ISA irq handlers. This means that 50 * they have a 1:1 mapping for arrayindex:irq_num. This is not 51 * true for interrupts that come in through IO APICs, to find 52 * their source, go through ci->ci_isources[index].is_pic 53 * 54 * It's possible to always maintain a 1:1 mapping, but that means 55 * limiting the total number of interrupt sources to MAX_INTR_SOURCES 56 * (32), instead of 32 per CPU. It also would mean that having multiple 57 * IO APICs which deliver interrupts from an equal pin number would 58 * overlap if they were to be sent to the same CPU. 59 */ 60 61 struct intrstub { 62 void *ist_entry; 63 void *ist_recurse; 64 void *ist_resume; 65 }; 66 67 struct intrsource { 68 int is_maxlevel; /* max. IPL for this source */ 69 int is_pin; /* IRQ for legacy; pin for IO APIC */ 70 struct intrhand *is_handlers; /* handler chain */ 71 struct pic *is_pic; /* originating PIC */ 72 void *is_recurse; /* entry for spllower */ 73 void *is_resume; /* entry for doreti */ 74 lwp_t *is_lwp; /* for soft interrupts */ 75 struct evcnt is_evcnt; /* interrupt counter */ 76 int is_flags; /* see below */ 77 int is_type; /* level, edge */ 78 int is_idtvec; 79 int is_minlevel; 80 char is_evname[32]; /* event counter name */ 81 }; 82 83 #define IS_LEGACY 0x0001 /* legacy ISA irq source */ 84 #define IS_IPI 0x0002 85 #define IS_LOG 0x0004 86 87 /* 88 * Interrupt handler chains. *_intr_establish() insert a handler into 89 * the list. The handler is called with its (single) argument. 90 */ 91 92 struct intrhand { 93 int (*ih_fun)(void *); 94 void *ih_arg; 95 int ih_level; 96 int (*ih_realfun)(void *); 97 void *ih_realarg; 98 struct intrhand *ih_next; 99 int ih_pin; 100 int ih_slot; 101 struct cpu_info *ih_cpu; 102 }; 103 104 #define IMASK(ci,level) (ci)->ci_imask[(level)] 105 #define IUNMASK(ci,level) (ci)->ci_iunmask[(level)] 106 107 void Xspllower(int); 108 void spllower(int); 109 int splraise(int); 110 void softintr(int); 111 112 /* 113 * Convert spl level to local APIC level 114 */ 115 116 #define APIC_LEVEL(l) ((l) << 4) 117 118 /* 119 * Miscellaneous 120 */ 121 122 #define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x)) 123 #define spl0() spllower(IPL_NONE) 124 #define splx(x) spllower(x) 125 126 typedef uint8_t ipl_t; 127 typedef struct { 128 ipl_t _ipl; 129 } ipl_cookie_t; 130 131 static inline ipl_cookie_t 132 makeiplcookie(ipl_t ipl) 133 { 134 135 return (ipl_cookie_t){._ipl = ipl}; 136 } 137 138 static inline int 139 splraiseipl(ipl_cookie_t icookie) 140 { 141 142 return splraise(icookie._ipl); 143 } 144 145 #include <sys/spl.h> 146 147 /* 148 * Stub declarations. 149 */ 150 151 void Xsoftintr(void); 152 void Xpreemptrecurse(void); 153 void Xpreemptresume(void); 154 155 extern struct intrstub i8259_stubs[]; 156 extern struct intrstub ioapic_edge_stubs[]; 157 extern struct intrstub ioapic_level_stubs[]; 158 159 struct cpu_info; 160 161 struct pcibus_attach_args; 162 163 void intr_default_setup(void); 164 void *nmi_establish(int (*)(void *), void *); 165 bool nmi_disestablish(void *); 166 int nmi_dispatch(void); 167 int x86_nmi(void); 168 void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *, bool); 169 void intr_disestablish(struct intrhand *); 170 void intr_add_pcibus(struct pcibus_attach_args *); 171 const char *intr_string(int); 172 void cpu_intr_init(struct cpu_info *); 173 int intr_find_mpmapping(int, int, int *); 174 struct pic *intr_findpic(int); 175 #ifdef INTRDEBUG 176 void intr_printconfig(void); 177 #endif 178 179 int x86_send_ipi(struct cpu_info *, int); 180 void x86_broadcast_ipi(int); 181 void x86_multicast_ipi(int, int); 182 void x86_ipi_handler(void); 183 184 extern void (*ipifunc[X86_NIPI])(struct cpu_info *); 185 186 #endif /* !_LOCORE */ 187 188 #endif /* !_X86_INTR_H_ */ 189
Indexes created Wed Sep 24 15:09:51 GMT 2025