intr.h revision 1.38
1 /* $NetBSD: intr.h,v 1.38 2009/03/27 16:09:24 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _X86_INTR_H_ 33 #define _X86_INTR_H_ 34 35 #define __HAVE_FAST_SOFTINTS 36 #define __HAVE_PREEMPTION 37 38 #ifdef _KERNEL 39 #include <sys/types.h> 40 #else 41 #include <stdbool.h> 42 #endif 43 44 #include <sys/evcnt.h> 45 #include <machine/intrdefs.h> 46 47 #ifndef _LOCORE 48 #include <machine/pic.h> 49 50 /* 51 * Struct describing an interrupt source for a CPU. struct cpu_info 52 * has an array of MAX_INTR_SOURCES of these. The index in the array 53 * is equal to the stub number of the stubcode as present in vector.s 54 * 55 * The primary CPU's array of interrupt sources has its first 16 56 * entries reserved for legacy ISA irq handlers. This means that 57 * they have a 1:1 mapping for arrayindex:irq_num. This is not 58 * true for interrupts that come in through IO APICs, to find 59 * their source, go through ci->ci_isources[index].is_pic 60 * 61 * It's possible to always maintain a 1:1 mapping, but that means 62 * limiting the total number of interrupt sources to MAX_INTR_SOURCES 63 * (32), instead of 32 per CPU. It also would mean that having multiple 64 * IO APICs which deliver interrupts from an equal pin number would 65 * overlap if they were to be sent to the same CPU. 66 */ 67 68 struct intrstub { 69 void *ist_entry; 70 void *ist_recurse; 71 void *ist_resume; 72 }; 73 74 struct intrsource { 75 int is_maxlevel; /* max. IPL for this source */ 76 int is_pin; /* IRQ for legacy; pin for IO APIC */ 77 struct intrhand *is_handlers; /* handler chain */ 78 struct pic *is_pic; /* originating PIC */ 79 void *is_recurse; /* entry for spllower */ 80 void *is_resume; /* entry for doreti */ 81 lwp_t *is_lwp; /* for soft interrupts */ 82 struct evcnt is_evcnt; /* interrupt counter */ 83 int is_flags; /* see below */ 84 int is_type; /* level, edge */ 85 int is_idtvec; 86 int is_minlevel; 87 char is_evname[32]; /* event counter name */ 88 }; 89 90 #define IS_LEGACY 0x0001 /* legacy ISA irq source */ 91 #define IS_IPI 0x0002 92 #define IS_LOG 0x0004 93 94 /* 95 * Interrupt handler chains. *_intr_establish() insert a handler into 96 * the list. The handler is called with its (single) argument. 97 */ 98 99 struct intrhand { 100 int (*ih_fun)(void *); 101 void *ih_arg; 102 int ih_level; 103 int (*ih_realfun)(void *); 104 void *ih_realarg; 105 struct intrhand *ih_next; 106 int ih_pin; 107 int ih_slot; 108 struct cpu_info *ih_cpu; 109 }; 110 111 #define IMASK(ci,level) (ci)->ci_imask[(level)] 112 #define IUNMASK(ci,level) (ci)->ci_iunmask[(level)] 113 114 void Xspllower(int); 115 void spllower(int); 116 int splraise(int); 117 void softintr(int); 118 119 /* 120 * Convert spl level to local APIC level 121 */ 122 123 #define APIC_LEVEL(l) ((l) << 4) 124 125 /* 126 * Miscellaneous 127 */ 128 129 #define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x)) 130 #define spl0() spllower(IPL_NONE) 131 #define splx(x) spllower(x) 132 133 typedef uint8_t ipl_t; 134 typedef struct { 135 ipl_t _ipl; 136 } ipl_cookie_t; 137 138 static inline ipl_cookie_t 139 makeiplcookie(ipl_t ipl) 140 { 141 142 return (ipl_cookie_t){._ipl = ipl}; 143 } 144 145 static inline int 146 splraiseipl(ipl_cookie_t icookie) 147 { 148 149 return splraise(icookie._ipl); 150 } 151 152 #include <sys/spl.h> 153 154 /* 155 * Stub declarations. 156 */ 157 158 void Xsoftintr(void); 159 void Xpreemptrecurse(void); 160 void Xpreemptresume(void); 161 162 extern struct intrstub i8259_stubs[]; 163 extern struct intrstub ioapic_edge_stubs[]; 164 extern struct intrstub ioapic_level_stubs[]; 165 166 struct cpu_info; 167 168 struct pcibus_attach_args; 169 170 void intr_default_setup(void); 171 int x86_nmi(void); 172 void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *, bool); 173 void intr_disestablish(struct intrhand *); 174 void intr_add_pcibus(struct pcibus_attach_args *); 175 const char *intr_string(int); 176 void cpu_intr_init(struct cpu_info *); 177 int intr_find_mpmapping(int, int, int *); 178 struct pic *intr_findpic(int); 179 #ifdef INTRDEBUG 180 void intr_printconfig(void); 181 #endif 182 183 int x86_send_ipi(struct cpu_info *, int); 184 void x86_broadcast_ipi(int); 185 void x86_multicast_ipi(int, int); 186 void x86_ipi_handler(void); 187 188 extern void (*ipifunc[X86_NIPI])(struct cpu_info *); 189 190 #endif /* !_LOCORE */ 191 192 #endif /* !_X86_INTR_H_ */ 193
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