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intr.h revision 1.4
      1 /*	$NetBSD: intr.h,v 1.4 2003/06/23 11:01:52 martin Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Charles M. Hannum, and by Jason R. Thorpe.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *        This product includes software developed by the NetBSD
     21  *        Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 #ifndef _X86_INTR_H_
     40 #define _X86_INTR_H_
     41 
     42 #include "opt_multiprocessor.h"
     43 #include <machine/intrdefs.h>
     44 
     45 #ifndef _LOCORE
     46 #include <machine/cpu.h>
     47 #include <machine/pic.h>
     48 
     49 /*
     50  * Struct describing an interrupt source for a CPU. struct cpu_info
     51  * has an array of MAX_INTR_SOURCES of these. The index in the array
     52  * is equal to the stub number of the stubcode as present in vector.s
     53  *
     54  * The primary CPU's array of interrupt sources has its first 16
     55  * entries reserved for legacy ISA irq handlers. This means that
     56  * they have a 1:1 mapping for arrayindex:irq_num. This is not
     57  * true for interrupts that come in through IO APICs, to find
     58  * their source, go through ci->ci_isources[index].is_pic
     59  *
     60  * It's possible to always maintain a 1:1 mapping, but that means
     61  * limiting the total number of interrupt sources to MAX_INTR_SOURCES
     62  * (32), instead of 32 per CPU. It also would mean that having multiple
     63  * IO APICs which deliver interrupts from an equal pin number would
     64  * overlap if they were to be sent to the same CPU.
     65  */
     66 
     67 struct intrstub {
     68 	void *ist_entry;
     69 	void *ist_recurse;
     70 	void *ist_resume;
     71 };
     72 
     73 struct intrsource {
     74 	int is_maxlevel;		/* max. IPL for this source */
     75 	int is_pin;			/* IRQ for legacy; pin for IO APIC */
     76 	struct intrhand *is_handlers;	/* handler chain */
     77 	struct pic *is_pic;		/* originating PIC */
     78 	void *is_recurse;		/* entry for spllower */
     79 	void *is_resume;		/* entry for doreti */
     80 	struct evcnt is_evcnt;		/* interrupt counter */
     81 	char is_evname[32];		/* event counter name */
     82 	int is_flags;			/* see below */
     83 	int is_type;			/* level, edge */
     84 	int is_idtvec;
     85 	int is_minlevel;
     86 };
     87 
     88 #define IS_LEGACY	0x0001		/* legacy ISA irq source */
     89 #define IS_IPI		0x0002
     90 #define IS_LOG		0x0004
     91 
     92 
     93 /*
     94  * Interrupt handler chains.  *_intr_establish() insert a handler into
     95  * the list.  The handler is called with its (single) argument.
     96  */
     97 
     98 struct intrhand {
     99 	int	(*ih_fun)(void *);
    100 	void	*ih_arg;
    101 	int	ih_level;
    102 	struct	intrhand *ih_next;
    103 	int	ih_pin;
    104 	int	ih_slot;
    105 	struct cpu_info *ih_cpu;
    106 };
    107 
    108 #define IMASK(ci,level) (ci)->ci_imask[(level)]
    109 #define IUNMASK(ci,level) (ci)->ci_iunmask[(level)]
    110 
    111 extern void Xspllower __P((int));
    112 
    113 static __inline int splraise __P((int));
    114 static __inline void spllower __P((int));
    115 static __inline void softintr __P((int));
    116 
    117 /*
    118  * Convert spl level to local APIC level
    119  */
    120 #define APIC_LEVEL(l)   ((l) << 4)
    121 
    122 /*
    123  * compiler barrier: prevent reordering of instructions.
    124  * XXX something similar will move to <sys/cdefs.h>
    125  * or thereabouts.
    126  * This prevents the compiler from reordering code around
    127  * this "instruction", acting as a sequence point for code generation.
    128  */
    129 
    130 #define	__splbarrier() __asm __volatile("":::"memory")
    131 
    132 /*
    133  * Add a mask to cpl, and return the old value of cpl.
    134  */
    135 static __inline int
    136 splraise(int nlevel)
    137 {
    138 	int olevel;
    139 	struct cpu_info *ci = curcpu();
    140 
    141 	olevel = ci->ci_ilevel;
    142 	if (nlevel > olevel)
    143 		ci->ci_ilevel = nlevel;
    144 	__splbarrier();
    145 	return (olevel);
    146 }
    147 
    148 /*
    149  * Restore a value to cpl (unmasking interrupts).  If any unmasked
    150  * interrupts are pending, call Xspllower() to process them.
    151  */
    152 static __inline void
    153 spllower(int nlevel)
    154 {
    155 	struct cpu_info *ci = curcpu();
    156 
    157 	__splbarrier();
    158 	/*
    159 	 * Since this should only lower the interrupt level,
    160 	 * the XOR below should only show interrupts that
    161 	 * are being unmasked.
    162 	 */
    163 	if (ci->ci_ipending & IUNMASK(ci,nlevel))
    164 		Xspllower(nlevel);
    165 	else
    166 		ci->ci_ilevel = nlevel;
    167 }
    168 
    169 /*
    170  * Hardware interrupt masks
    171  */
    172 #define	splbio()	splraise(IPL_BIO)
    173 #define	splnet()	splraise(IPL_NET)
    174 #define	spltty()	splraise(IPL_TTY)
    175 #define	splaudio()	splraise(IPL_AUDIO)
    176 #define	splclock()	splraise(IPL_CLOCK)
    177 #define	splstatclock()	splclock()
    178 #define	splserial()	splraise(IPL_SERIAL)
    179 #define splipi()	splraise(IPL_IPI)
    180 
    181 #define spllpt()	spltty()
    182 
    183 #define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x))
    184 #define	spllpt()	spltty()
    185 
    186 /*
    187  * Software interrupt masks
    188  *
    189  * NOTE: splsoftclock() is used by hardclock() to lower the priority from
    190  * clock to softclock before it calls softclock().
    191  */
    192 #define	spllowersoftclock() spllower(IPL_SOFTCLOCK)
    193 
    194 #define	splsoftclock()	splraise(IPL_SOFTCLOCK)
    195 #define	splsoftnet()	splraise(IPL_SOFTNET)
    196 #define	splsoftserial()	splraise(IPL_SOFTSERIAL)
    197 
    198 /*
    199  * Miscellaneous
    200  */
    201 #define	splvm()		splraise(IPL_VM)
    202 #define	splhigh()	splraise(IPL_HIGH)
    203 #define	spl0()		spllower(IPL_NONE)
    204 #define	splsched()	splraise(IPL_SCHED)
    205 #define spllock() 	splhigh()
    206 #define	splx(x)		spllower(x)
    207 
    208 /*
    209  * Software interrupt registration
    210  *
    211  * We hand-code this to ensure that it's atomic.
    212  *
    213  * XXX always scheduled on the current CPU.
    214  */
    215 static __inline void
    216 softintr(int sir)
    217 {
    218 	struct cpu_info *ci = curcpu();
    219 
    220 	__asm __volatile("lock ; orl %1, %0" :
    221 	    "=m"(ci->ci_ipending) : "ir" (1 << sir));
    222 }
    223 
    224 /*
    225  * XXX
    226  */
    227 #define	setsoftnet()	softintr(SIR_NET)
    228 
    229 /*
    230  * Stub declarations.
    231  */
    232 
    233 extern void Xsoftclock(void);
    234 extern void Xsoftnet(void);
    235 extern void Xsoftserial(void);
    236 
    237 extern struct intrstub i8259_stubs[];
    238 extern struct intrstub ioapic_edge_stubs[];
    239 extern struct intrstub ioapic_level_stubs[];
    240 
    241 struct cpu_info;
    242 
    243 extern char idt_allocmap[];
    244 
    245 void intr_default_setup(void);
    246 int x86_nmi(void);
    247 void intr_calculatemasks(struct cpu_info *);
    248 int intr_allocate_slot_cpu(struct cpu_info *, struct pic *, int, int *);
    249 int intr_allocate_slot(struct pic *, int, int, int, struct cpu_info **, int *,
    250 		       int *);
    251 void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *);
    252 void intr_disestablish(struct intrhand *);
    253 void cpu_intr_init(struct cpu_info *);
    254 int intr_find_mpmapping(int bus, int pin, int *handle);
    255 #ifdef INTRDEBUG
    256 void intr_printconfig(void);
    257 #endif
    258 
    259 #ifdef MULTIPROCESSOR
    260 int x86_send_ipi(struct cpu_info *, int);
    261 void x86_broadcast_ipi(int);
    262 void x86_multicast_ipi(int, int);
    263 void x86_ipi_handler(void);
    264 void x86_intlock(struct intrframe);
    265 void x86_intunlock(struct intrframe);
    266 void x86_softintlock(void);
    267 void x86_softintunlock(void);
    268 
    269 extern void (*ipifunc[X86_NIPI])(struct cpu_info *);
    270 #endif
    271 
    272 #endif /* !_LOCORE */
    273 
    274 /*
    275  * Generic software interrupt support.
    276  */
    277 
    278 #define	X86_SOFTINTR_SOFTCLOCK		0
    279 #define	X86_SOFTINTR_SOFTNET		1
    280 #define	X86_SOFTINTR_SOFTSERIAL	2
    281 #define	X86_NSOFTINTR			3
    282 
    283 #ifndef _LOCORE
    284 #include <sys/queue.h>
    285 
    286 struct x86_soft_intrhand {
    287 	TAILQ_ENTRY(x86_soft_intrhand)
    288 		sih_q;
    289 	struct x86_soft_intr *sih_intrhead;
    290 	void	(*sih_fn)(void *);
    291 	void	*sih_arg;
    292 	int	sih_pending;
    293 };
    294 
    295 struct x86_soft_intr {
    296 	TAILQ_HEAD(, x86_soft_intrhand)
    297 		softintr_q;
    298 	int softintr_ssir;
    299 	struct simplelock softintr_slock;
    300 };
    301 
    302 #define	x86_softintr_lock(si, s)					\
    303 do {									\
    304 	(s) = splhigh();						\
    305 	simple_lock(&si->softintr_slock);				\
    306 } while (/*CONSTCOND*/ 0)
    307 
    308 #define	x86_softintr_unlock(si, s)					\
    309 do {									\
    310 	simple_unlock(&si->softintr_slock);				\
    311 	splx((s));							\
    312 } while (/*CONSTCOND*/ 0)
    313 
    314 void	*softintr_establish(int, void (*)(void *), void *);
    315 void	softintr_disestablish(void *);
    316 void	softintr_init(void);
    317 void	softintr_dispatch(int);
    318 
    319 #define	softintr_schedule(arg)						\
    320 do {									\
    321 	struct x86_soft_intrhand *__sih = (arg);			\
    322 	struct x86_soft_intr *__si = __sih->sih_intrhead;		\
    323 	int __s;							\
    324 									\
    325 	x86_softintr_lock(__si, __s);					\
    326 	if (__sih->sih_pending == 0) {					\
    327 		TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q);	\
    328 		__sih->sih_pending = 1;					\
    329 		softintr(__si->softintr_ssir);				\
    330 	}								\
    331 	x86_softintr_unlock(__si, __s);					\
    332 } while (/*CONSTCOND*/ 0)
    333 #endif /* _LOCORE */
    334 
    335 #endif /* !_X86_INTR_H_ */
    336