intr.h revision 1.52
1 /* $NetBSD: intr.h,v 1.52 2017/11/04 14:56:48 cherry Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _X86_INTR_H_ 33 #define _X86_INTR_H_ 34 35 #if !defined(XEN) 36 #define __HAVE_FAST_SOFTINTS 37 #define __HAVE_PREEMPTION 38 #endif /* !defined(XEN) */ 39 40 #ifdef _KERNEL 41 #include <sys/types.h> 42 #else 43 #include <stdbool.h> 44 #endif 45 46 #include <sys/evcnt.h> 47 #include <sys/queue.h> 48 #include <machine/intrdefs.h> 49 50 #ifndef _LOCORE 51 #include <machine/pic.h> 52 53 /* 54 * Struct describing an interrupt source for a CPU. struct cpu_info 55 * has an array of MAX_INTR_SOURCES of these. The index in the array 56 * is equal to the stub number of the stubcode as present in vector.s 57 * 58 * The primary CPU's array of interrupt sources has its first 16 59 * entries reserved for legacy ISA irq handlers. This means that 60 * they have a 1:1 mapping for arrayindex:irq_num. This is not 61 * true for interrupts that come in through IO APICs, to find 62 * their source, go through ci->ci_isources[index].is_pic 63 * 64 * It's possible to always maintain a 1:1 mapping, but that means 65 * limiting the total number of interrupt sources to MAX_INTR_SOURCES 66 * (32), instead of 32 per CPU. It also would mean that having multiple 67 * IO APICs which deliver interrupts from an equal pin number would 68 * overlap if they were to be sent to the same CPU. 69 */ 70 71 struct intrstub { 72 #if !defined(XEN) 73 void *ist_entry; 74 #endif 75 void *ist_recurse; 76 void *ist_resume; 77 }; 78 79 struct percpu_evcnt { 80 cpuid_t cpuid; 81 uint64_t count; 82 }; 83 84 struct intrsource { 85 int is_maxlevel; /* max. IPL for this source */ 86 int is_pin; /* IRQ for legacy; pin for IO APIC, 87 -1 for MSI */ 88 struct intrhand *is_handlers; /* handler chain */ 89 struct pic *is_pic; /* originating PIC */ 90 void *is_recurse; /* entry for spllower */ 91 void *is_resume; /* entry for doreti */ 92 lwp_t *is_lwp; /* for soft interrupts */ 93 #if defined(XEN) 94 u_long ipl_evt_mask1; /* pending events for this IPL */ 95 u_long ipl_evt_mask2[NR_EVENT_CHANNELS]; 96 #endif 97 struct evcnt is_evcnt; /* interrupt counter per cpu */ 98 int is_flags; /* see below */ 99 int is_type; /* level, edge */ 100 int is_idtvec; 101 int is_minlevel; 102 char is_evname[32]; /* event counter name */ 103 char is_intrid[INTRIDBUF]; /* intrid created by create_intrid() */ 104 char is_xname[INTRDEVNAMEBUF]; /* device names */ 105 cpuid_t is_active_cpu; /* active cpuid */ 106 struct percpu_evcnt *is_saved_evcnt; /* interrupt count of deactivated cpus */ 107 SIMPLEQ_ENTRY(intrsource) is_list; /* link of intrsources */ 108 }; 109 110 #define IS_LEGACY 0x0001 /* legacy ISA irq source */ 111 #define IS_IPI 0x0002 112 #define IS_LOG 0x0004 113 114 /* 115 * Interrupt handler chains. *_intr_establish() insert a handler into 116 * the list. The handler is called with its (single) argument. 117 */ 118 119 struct intrhand { 120 #if defined(XEN) 121 /* 122 * Note: This is transitional and will go away. 123 * 124 * We ought to use a union here, but too much effort. 125 * We use this field to tear down the cookie handed to us 126 * via x86/intr.c:intr_disestablish(); 127 * Interestingly, the intr_establish_xname() function returns 128 * a "void *" - so we abuse this for now. 129 */ 130 int pic_type; /* Overloading wrt struct pintrhand */ 131 #endif 132 int (*ih_fun)(void *); 133 void *ih_arg; 134 int ih_level; 135 int (*ih_realfun)(void *); 136 void *ih_realarg; 137 struct intrhand *ih_next; 138 struct intrhand **ih_prevp; 139 int ih_pin; 140 int ih_slot; 141 #if defined(XEN) 142 struct intrhand *ih_evt_next; 143 #endif 144 struct cpu_info *ih_cpu; 145 }; 146 147 #define IMASK(ci,level) (ci)->ci_imask[(level)] 148 #define IUNMASK(ci,level) (ci)->ci_iunmask[(level)] 149 150 #ifdef _KERNEL 151 152 void Xspllower(int); 153 void spllower(int); 154 int splraise(int); 155 void softintr(int); 156 157 /* 158 * Convert spl level to local APIC level 159 */ 160 161 #define APIC_LEVEL(l) ((l) << 4) 162 163 /* 164 * Miscellaneous 165 */ 166 167 #define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x)) 168 #define spl0() spllower(IPL_NONE) 169 #define splx(x) spllower(x) 170 171 typedef uint8_t ipl_t; 172 typedef struct { 173 ipl_t _ipl; 174 } ipl_cookie_t; 175 176 static inline ipl_cookie_t 177 makeiplcookie(ipl_t ipl) 178 { 179 180 return (ipl_cookie_t){._ipl = ipl}; 181 } 182 183 static inline int 184 splraiseipl(ipl_cookie_t icookie) 185 { 186 187 return splraise(icookie._ipl); 188 } 189 190 #include <sys/spl.h> 191 192 /* 193 * Stub declarations. 194 */ 195 196 void Xsoftintr(void); 197 void Xpreemptrecurse(void); 198 void Xpreemptresume(void); 199 200 extern struct intrstub i8259_stubs[]; 201 extern struct intrstub ioapic_edge_stubs[]; 202 extern struct intrstub ioapic_level_stubs[]; 203 extern struct intrstub x2apic_edge_stubs[]; 204 extern struct intrstub x2apic_level_stubs[]; 205 206 struct cpu_info; 207 208 struct pcibus_attach_args; 209 210 typedef uint64_t intr_handle_t; 211 212 void intr_default_setup(void); 213 void x86_nmi(void); 214 void *intr_establish_xname(int, struct pic *, int, int, int, int (*)(void *), 215 void *, bool, const char *); 216 void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *, bool); 217 void intr_disestablish(struct intrhand *); 218 void intr_add_pcibus(struct pcibus_attach_args *); 219 const char *intr_string(intr_handle_t, char *, size_t); 220 void cpu_intr_init(struct cpu_info *); 221 int intr_find_mpmapping(int, int, intr_handle_t *); 222 struct pic *intr_findpic(int); 223 void intr_printconfig(void); 224 225 struct intrsource *intr_allocate_io_intrsource(const char *); 226 void intr_free_io_intrsource(const char *); 227 228 int x86_send_ipi(struct cpu_info *, int); 229 void x86_broadcast_ipi(int); 230 void x86_ipi_handler(void); 231 232 #ifndef XEN 233 extern void (* const ipifunc[X86_NIPI])(struct cpu_info *); 234 #endif 235 236 #endif /* _KERNEL */ 237 238 #endif /* !_LOCORE */ 239 240 #endif /* !_X86_INTR_H_ */ 241
Indexes created Wed Sep 24 02:09:48 GMT 2025