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intrdefs.h revision 1.11 
      1 /*	$NetBSD: intrdefs.h,v 1.11 2007/12/03 15:34:27 ad Exp $	*/
      2 
      3 #ifndef _X86_INTRDEFS_H_
      4 #define _X86_INTRDEFS_H_
      5 
      6 /* Interrupt priority levels. */
      7 #define	IPL_NONE	0x0	/* nothing */
      8 #define	IPL_SOFTCLOCK	0x1	/* timeouts */
      9 #define	IPL_SOFTBIO	0x2	/* block I/O passdown */
     10 #define	IPL_SOFTNET	0x3	/* protocol stacks */
     11 #define	IPL_SOFTSERIAL	0x4	/* serial passdown */
     12 #define	IPL_VM		0x5	/* low I/O, memory allocation */
     13 #define IPL_SCHED	0x6	/* medium I/O, scheduler, clock */
     14 #define	IPL_HIGH	0x7	/* high I/O, statclock, IPIs */
     15 #define	NIPL		8
     16 
     17 /* Interrupt sharing types. */
     18 #define	IST_NONE	0	/* none */
     19 #define	IST_PULSE	1	/* pulsed */
     20 #define	IST_EDGE	2	/* edge-triggered */
     21 #define	IST_LEVEL	3	/* level-triggered */
     22 
     23 /*
     24  * Local APIC masks and software interrupt masks, in order
     25  * of priority.  Must not conflict with SIR_* below.
     26  */
     27 #define LIR_IPI		31
     28 #define LIR_TIMER	30
     29 
     30 /*
     31  * XXX These should be lowest numbered, but right now would
     32  * conflict with the legacy IRQs.  Their current position
     33  * means that soft interrupt take priority over hardware
     34  * interrupts when lowering the priority level!
     35  */
     36 #define	SIR_SERIAL	29
     37 #define	SIR_NET		28
     38 #define	SIR_BIO		27
     39 #define	SIR_CLOCK	26
     40 
     41 /*
     42  * Maximum # of interrupt sources per CPU. 32 to fit in one word.
     43  * ioapics can theoretically produce more, but it's not likely to
     44  * happen. For multiple ioapics, things can be routed to different
     45  * CPUs.
     46  */
     47 #define MAX_INTR_SOURCES	32
     48 #define NUM_LEGACY_IRQS		16
     49 
     50 /*
     51  * Low and high boundaries between which interrupt gates will
     52  * be allocated in the IDT.
     53  */
     54 #define IDT_INTR_LOW	(0x20 + NUM_LEGACY_IRQS)
     55 #define IDT_INTR_HIGH	0xef
     56 
     57 #define X86_IPI_HALT			0x00000001
     58 #define X86_IPI_MICROSET		0x00000002
     59 #define X86_IPI_FLUSH_FPU		0x00000004
     60 #define X86_IPI_SYNCH_FPU		0x00000008
     61 #define X86_IPI_MTRR			0x00000010
     62 #define X86_IPI_GDT			0x00000020
     63 #define X86_IPI_WRITE_MSR		0x00000040
     64 
     65 #define X86_NIPI		7
     66 
     67 #define X86_IPI_NAMES { "halt IPI", "timeset IPI", "FPU flush IPI", \
     68 			 "FPU synch IPI", "MTRR update IPI", \
     69 			 "GDT update IPI", "MSR write IPI" }
     70 
     71 #define IREENT_MAGIC	0x18041969
     72 
     73 #endif /* _X86_INTRDEFS_H_ */
     74