Home | History | Annotate | Line # | Download | only in include
intrdefs.h revision 1.4 
      1 /*	$NetBSD: intrdefs.h,v 1.4 2005/04/16 07:45:59 yamt Exp $	*/
      2 
      3 #ifndef _X86_INTRDEFS_H_
      4 #define _X86_INTRDEFS_H_
      5 
      6 /*
      7  * Interrupt priority levels.
      8  *
      9  * There are tty, network and disk drivers that use free() at interrupt
     10  * time, so imp > (tty | net | bio).
     11  *
     12  * Since run queues may be manipulated by both the statclock and tty,
     13  * network, and disk drivers, clock > imp.
     14  *
     15  * IPL_HIGH must block everything that can manipulate a run queue.
     16  *
     17  * We need serial drivers to run at the absolute highest priority to
     18  * avoid overruns, so serial > high.
     19  *
     20  * The level numbers are picked to fit into APIC vector priorities.
     21  *
     22  */
     23 #define	IPL_NONE	0x0	/* nothing */
     24 #define	IPL_SOFTCLOCK	0x4	/* timeouts */
     25 #define	IPL_SOFTNET	0x5	/* protocol stacks */
     26 #define	IPL_BIO		0x6	/* block I/O */
     27 #define	IPL_NET		0x7	/* network */
     28 #define	IPL_SOFTSERIAL	0x8	/* serial */
     29 #define	IPL_TTY		0x9	/* terminal */
     30 #define	IPL_VM		0xa	/* memory allocation */
     31 #define	IPL_AUDIO	0xb	/* audio */
     32 #define	IPL_CLOCK	0xc	/* clock */
     33 #define IPL_SCHED	IPL_CLOCK
     34 #define	IPL_HIGH	0xd	/* everything */
     35 #define	IPL_SERIAL	0xd	/* serial */
     36 #define IPL_IPI		0xe	/* inter-processor interrupts */
     37 #define	NIPL		16
     38 
     39 /* Interrupt sharing types. */
     40 #define	IST_NONE	0	/* none */
     41 #define	IST_PULSE	1	/* pulsed */
     42 #define	IST_EDGE	2	/* edge-triggered */
     43 #define	IST_LEVEL	3	/* level-triggered */
     44 
     45 /*
     46  * Local APIC masks. Must not conflict with SIR_* above, and must
     47  * be >= NUM_LEGACY_IRQs. Note that LIR_IPI must be first.
     48  */
     49 #define LIR_IPI		31
     50 #define LIR_TIMER	30
     51 
     52 /* Soft interrupt masks. */
     53 #define	SIR_CLOCK	29
     54 #define	SIR_NET		28
     55 #define	SIR_SERIAL	27
     56 
     57 
     58 /*
     59  * Maximum # of interrupt sources per CPU. 32 to fit in one word.
     60  * ioapics can theoretically produce more, but it's not likely to
     61  * happen. For multiple ioapics, things can be routed to different
     62  * CPUs.
     63  */
     64 #define MAX_INTR_SOURCES	32
     65 #define NUM_LEGACY_IRQS		16
     66 
     67 /*
     68  * Low and high boundaries between which interrupt gates will
     69  * be allocated in the IDT.
     70  */
     71 #define IDT_INTR_LOW	(0x20 + NUM_LEGACY_IRQS)
     72 #define IDT_INTR_HIGH	0xef
     73 
     74 #define X86_IPI_HALT			0x00000001
     75 #define X86_IPI_MICROSET		0x00000002
     76 #define X86_IPI_FLUSH_FPU		0x00000004
     77 #define X86_IPI_SYNCH_FPU		0x00000008
     78 #define X86_IPI_TLB			0x00000010
     79 #define X86_IPI_MTRR			0x00000020
     80 #define X86_IPI_GDT			0x00000040
     81 
     82 #define X86_NIPI		7
     83 
     84 #define X86_IPI_NAMES { "halt IPI", "timeset IPI", "FPU flush IPI", \
     85 			 "FPU synch IPI", "TLB shootdown IPI", \
     86 			 "MTRR update IPI", "GDT update IPI" }
     87 
     88 #define IREENT_MAGIC	0x18041969
     89 
     90 #endif /* _X86_INTRDEFS_H_ */
     91