lock.h revision 1.15
1 /* $NetBSD: lock.h,v 1.15 2007/09/10 11:34:10 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2006 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Machine-dependent spin lock operations. 41 */ 42 43 #ifndef _X86_LOCK_H_ 44 #define _X86_LOCK_H_ 45 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #endif 49 50 #include <machine/cpufunc.h> 51 52 static __inline int 53 __SIMPLELOCK_LOCKED_P(__cpu_simple_lock_t *__ptr) 54 { 55 return *__ptr == __SIMPLELOCK_LOCKED; 56 } 57 58 static __inline int 59 __SIMPLELOCK_UNLOCKED_P(__cpu_simple_lock_t *__ptr) 60 { 61 return *__ptr == __SIMPLELOCK_UNLOCKED; 62 } 63 64 #ifdef LOCKDEBUG 65 66 extern void __cpu_simple_lock_init(__cpu_simple_lock_t *); 67 extern void __cpu_simple_lock(__cpu_simple_lock_t *); 68 extern int __cpu_simple_lock_try(__cpu_simple_lock_t *); 69 extern void __cpu_simple_unlock(__cpu_simple_lock_t *); 70 71 #else 72 73 #include <machine/atomic.h> 74 75 static __inline void __cpu_simple_lock_init(__cpu_simple_lock_t *) 76 __attribute__((__unused__)); 77 static __inline void __cpu_simple_lock(__cpu_simple_lock_t *) 78 __attribute__((__unused__)); 79 static __inline int __cpu_simple_lock_try(__cpu_simple_lock_t *) 80 __attribute__((__unused__)); 81 static __inline void __cpu_simple_unlock(__cpu_simple_lock_t *) 82 __attribute__((__unused__)); 83 84 static __inline void 85 __cpu_simple_lock_set(__cpu_simple_lock_t *__ptr) 86 { 87 88 *__ptr = __SIMPLELOCK_LOCKED; 89 } 90 91 static __inline void 92 __cpu_simple_lock_clear(__cpu_simple_lock_t *__ptr) 93 { 94 95 *__ptr = __SIMPLELOCK_UNLOCKED; 96 } 97 98 static __inline void 99 __cpu_simple_lock_init(__cpu_simple_lock_t *lockp) 100 { 101 102 *lockp = __SIMPLELOCK_UNLOCKED; 103 __insn_barrier(); 104 } 105 106 static __inline void 107 __cpu_simple_lock(__cpu_simple_lock_t *lockp) 108 { 109 110 while (x86_atomic_testset_b(lockp, __SIMPLELOCK_LOCKED) 111 != __SIMPLELOCK_UNLOCKED) { 112 do { 113 x86_pause(); 114 } while (*lockp == __SIMPLELOCK_LOCKED); 115 } 116 __insn_barrier(); 117 } 118 119 static __inline int 120 __cpu_simple_lock_try(__cpu_simple_lock_t *lockp) 121 { 122 int r = (x86_atomic_testset_b(lockp, __SIMPLELOCK_LOCKED) 123 == __SIMPLELOCK_UNLOCKED); 124 125 __insn_barrier(); 126 127 return (r); 128 } 129 130 /* 131 * Note on x86 memory ordering 132 * 133 * When releasing a lock we must ensure that no stores or loads from within 134 * the critical section are re-ordered by the CPU to occur outside of it: 135 * they must have completed and be visible to other processors once the lock 136 * has been released. 137 * 138 * NetBSD usually runs with the kernel mapped (via MTRR) in a WB (write 139 * back) memory region. In that case, memory ordering on x86 platforms 140 * looks like this: 141 * 142 * i386 All loads/stores occur in instruction sequence. 143 * 144 * i486 All loads/stores occur in instruction sequence. In 145 * Pentium exceptional circumstances, loads can be re-ordered around 146 * stores, but for the purposes of releasing a lock it does 147 * not matter. Stores may not be immediately visible to other 148 * processors as they can be buffered. However, since the 149 * stores are buffered in order the lock release will always be 150 * the last operation in the critical section that becomes 151 * visible to other CPUs. 152 * 153 * Pentium Pro The "Intel 64 and IA-32 Architectures Software Developer's 154 * onwards Manual" volume 3A (order number 248966) says that (1) "Reads 155 * can be carried out speculatively and in any order" and (2) 156 * "Reads can pass buffered stores, but the processor is 157 * self-consistent.". This would be a problem for the below, 158 * and would mandate a locked instruction cycle or load fence 159 * before releasing the simple lock. 160 * 161 * The "Intel Pentium 4 Processor Optimization" guide (order 162 * number 253668-022US) says: "Loads can be moved before stores 163 * that occurred earlier in the program if they are not 164 * predicted to load from the same linear address.". This is 165 * not a problem since the only loads that can be re-ordered 166 * take place once the lock has been released via a store. 167 * 168 * The above two documents seem to contradict each other, 169 * however with the exception of early steppings of the Pentium 170 * Pro, the second document is closer to the truth: a store 171 * will always act as a load fence for all loads that precede 172 * the store in instruction order. 173 * 174 * Again, note that stores can be buffered and will not always 175 * become immediately visible to other CPUs: they are however 176 * buffered in order. 177 * 178 * AMD64 Stores occur in order and are buffered. Loads can be 179 * reordered, however stores act as load fences, meaning that 180 * loads can not be reordered around stores. 181 */ 182 static __inline void 183 __cpu_simple_unlock(__cpu_simple_lock_t *lockp) 184 { 185 186 __insn_barrier(); 187 *lockp = __SIMPLELOCK_UNLOCKED; 188 } 189 190 #endif /* !LOCKDEBUG */ 191 192 #define SPINLOCK_SPIN_HOOK /* nothing */ 193 #define SPINLOCK_BACKOFF_HOOK x86_pause() 194 195 #ifdef _KERNEL 196 void mb_read(void); 197 void mb_write(void); 198 void mb_memory(void); 199 #else /* _KERNEL */ 200 static __inline void 201 mb_read(void) 202 { 203 x86_lfence(); 204 } 205 206 static __inline void 207 mb_write(void) 208 { 209 __insn_barrier(); 210 } 211 212 static __inline void 213 mb_memory(void) 214 { 215 x86_mfence(); 216 } 217 #endif /* _KERNEL */ 218 219 #endif /* _X86_LOCK_H_ */ 220
Indexes created Tue Sep 30 11:09:46 GMT 2025