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lock.h revision 1.23.10.1 
      1 /*	$NetBSD: lock.h,v 1.23.10.1 2008/05/16 02:23:28 yamt Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2000, 2006 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Jason R. Thorpe and Andrew Doran.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * Machine-dependent spin lock operations.
     34  */
     35 
     36 #ifndef _X86_LOCK_H_
     37 #define	_X86_LOCK_H_
     38 
     39 static __inline int
     40 __SIMPLELOCK_LOCKED_P(__cpu_simple_lock_t *__ptr)
     41 {
     42 	return *__ptr == __SIMPLELOCK_LOCKED;
     43 }
     44 
     45 static __inline int
     46 __SIMPLELOCK_UNLOCKED_P(__cpu_simple_lock_t *__ptr)
     47 {
     48 	return *__ptr == __SIMPLELOCK_UNLOCKED;
     49 }
     50 
     51 static __inline void
     52 __cpu_simple_lock_set(__cpu_simple_lock_t *__ptr)
     53 {
     54 
     55 	*__ptr = __SIMPLELOCK_LOCKED;
     56 }
     57 
     58 static __inline void
     59 __cpu_simple_lock_clear(__cpu_simple_lock_t *__ptr)
     60 {
     61 
     62 	*__ptr = __SIMPLELOCK_UNLOCKED;
     63 }
     64 
     65 #ifdef _KERNEL
     66 
     67 #include <machine/cpufunc.h>
     68 
     69 void	__cpu_simple_lock_init(__cpu_simple_lock_t *);
     70 void	__cpu_simple_lock(__cpu_simple_lock_t *);
     71 int	__cpu_simple_lock_try(__cpu_simple_lock_t *);
     72 void	__cpu_simple_unlock(__cpu_simple_lock_t *);
     73 
     74 #define	SPINLOCK_SPIN_HOOK	/* nothing */
     75 
     76 #ifdef SPINLOCK_BACKOFF_HOOK
     77 #undef SPINLOCK_BACKOFF_HOOK
     78 #endif
     79 #define	SPINLOCK_BACKOFF_HOOK	x86_pause()
     80 
     81 #else
     82 
     83 static __inline void __cpu_simple_lock_init(__cpu_simple_lock_t *)
     84 	__unused;
     85 static __inline void __cpu_simple_lock(__cpu_simple_lock_t *)
     86 	__unused;
     87 static __inline int __cpu_simple_lock_try(__cpu_simple_lock_t *)
     88 	__unused;
     89 static __inline void __cpu_simple_unlock(__cpu_simple_lock_t *)
     90 	__unused;
     91 
     92 static __inline void
     93 __cpu_simple_lock_init(__cpu_simple_lock_t *lockp)
     94 {
     95 
     96 	*lockp = __SIMPLELOCK_UNLOCKED;
     97 	__insn_barrier();
     98 }
     99 
    100 static __inline int
    101 __cpu_simple_lock_try(__cpu_simple_lock_t *lockp)
    102 {
    103 	uint8_t val;
    104 
    105 	val = __SIMPLELOCK_LOCKED;
    106 	__asm volatile ("xchgb %0,(%2)" :
    107 	    "=r" (val)
    108 	    :"0" (val), "r" (lockp));
    109 	__insn_barrier();
    110 	return val == __SIMPLELOCK_UNLOCKED;
    111 }
    112 
    113 static __inline void
    114 __cpu_simple_lock(__cpu_simple_lock_t *lockp)
    115 {
    116 
    117 	while (!__cpu_simple_lock_try(lockp))
    118 		/* nothing */;
    119 	__insn_barrier();
    120 }
    121 
    122 /*
    123  * Note on x86 memory ordering
    124  *
    125  * When releasing a lock we must ensure that no stores or loads from within
    126  * the critical section are re-ordered by the CPU to occur outside of it:
    127  * they must have completed and be visible to other processors once the lock
    128  * has been released.
    129  *
    130  * NetBSD usually runs with the kernel mapped (via MTRR) in a WB (write
    131  * back) memory region.  In that case, memory ordering on x86 platforms
    132  * looks like this:
    133  *
    134  * i386		All loads/stores occur in instruction sequence.
    135  *
    136  * i486		All loads/stores occur in instruction sequence.  In
    137  * Pentium	exceptional circumstances, loads can be re-ordered around
    138  *		stores, but for the purposes of releasing a lock it does
    139  *		not matter.  Stores may not be immediately visible to other
    140  *		processors as they can be buffered.  However, since the
    141  *		stores are buffered in order the lock release will always be
    142  *		the last operation in the critical section that becomes
    143  *		visible to other CPUs.
    144  *
    145  * Pentium Pro	The "Intel 64 and IA-32 Architectures Software Developer's
    146  * onwards	Manual" volume 3A (order number 248966) says that (1) "Reads
    147  *		can be carried out speculatively and in any order" and (2)
    148  *		"Reads can pass buffered stores, but the processor is
    149  *		self-consistent.".  This would be a problem for the below,
    150  *		and would mandate a locked instruction cycle or load fence
    151  *		before releasing the simple lock.
    152  *
    153  *		The "Intel Pentium 4 Processor Optimization" guide (order
    154  *		number 253668-022US) says: "Loads can be moved before stores
    155  *		that occurred earlier in the program if they are not
    156  *		predicted to load from the same linear address.".  This is
    157  *		not a problem since the only loads that can be re-ordered
    158  *		take place once the lock has been released via a store.
    159  *
    160  *		The above two documents seem to contradict each other,
    161  *		however with the exception of early steppings of the Pentium
    162  *		Pro, the second document is closer to the truth: a store
    163  *		will always act as a load fence for all loads that precede
    164  *		the store in instruction order.
    165  *
    166  *		Again, note that stores can be buffered and will not always
    167  *		become immediately visible to other CPUs: they are however
    168  *		buffered in order.
    169  *
    170  * AMD64	Stores occur in order and are buffered.  Loads can be
    171  *		reordered, however stores act as load fences, meaning that
    172  *		loads can not be reordered around stores.
    173  */
    174 static __inline void
    175 __cpu_simple_unlock(__cpu_simple_lock_t *lockp)
    176 {
    177 
    178 	__insn_barrier();
    179 	*lockp = __SIMPLELOCK_UNLOCKED;
    180 }
    181 
    182 #endif	/* _KERNEL */
    183 
    184 #endif /* _X86_LOCK_H_ */
    185