isa_machdep.c revision 1.7
1 /* $NetBSD: isa_machdep.c,v 1.7 2003/05/07 21:33:58 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /*- 41 * Copyright (c) 1991 The Regents of the University of California. 42 * All rights reserved. 43 * 44 * This code is derived from software contributed to Berkeley by 45 * William Jolitz. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 1. Redistributions of source code must retain the above copyright 51 * notice, this list of conditions and the following disclaimer. 52 * 2. Redistributions in binary form must reproduce the above copyright 53 * notice, this list of conditions and the following disclaimer in the 54 * documentation and/or other materials provided with the distribution. 55 * 3. All advertising materials mentioning features or use of this software 56 * must display the following acknowledgement: 57 * This product includes software developed by the University of 58 * California, Berkeley and its contributors. 59 * 4. Neither the name of the University nor the names of its contributors 60 * may be used to endorse or promote products derived from this software 61 * without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 64 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 65 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 66 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 67 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 68 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 69 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 70 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 71 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 72 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 73 * SUCH DAMAGE. 74 * 75 * @(#)isa.c 7.2 (Berkeley) 5/13/91 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: isa_machdep.c,v 1.7 2003/05/07 21:33:58 fvdl Exp $"); 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/kernel.h> 84 #include <sys/syslog.h> 85 #include <sys/device.h> 86 #include <sys/malloc.h> 87 #include <sys/proc.h> 88 #include <sys/mbuf.h> 89 90 #define _X86_BUS_DMA_PRIVATE 91 #include <machine/bus.h> 92 93 #include <machine/pio.h> 94 #include <machine/cpufunc.h> 95 96 #include <dev/isa/isareg.h> 97 #include <dev/isa/isavar.h> 98 99 #include <uvm/uvm_extern.h> 100 101 #include "ioapic.h" 102 103 #if NIOAPIC > 0 104 #include <machine/i82093var.h> 105 #include <machine/mpbiosvar.h> 106 #endif 107 108 static int _isa_dma_may_bounce(bus_dma_tag_t, bus_dmamap_t, int, int *); 109 110 struct x86_bus_dma_tag isa_bus_dma_tag = { 111 ISA_DMA_BOUNCE_THRESHOLD, /* _bounce_thresh */ 112 0, /* _bounce_alloc_lo */ 113 ISA_DMA_BOUNCE_THRESHOLD, /* _bounce_alloc_hi */ 114 _isa_dma_may_bounce, 115 _bus_dmamap_create, 116 _bus_dmamap_destroy, 117 _bus_dmamap_load, 118 _bus_dmamap_load_mbuf, 119 _bus_dmamap_load_uio, 120 _bus_dmamap_load_raw, 121 _bus_dmamap_unload, 122 _bus_dmamap_sync, 123 _bus_dmamem_alloc, 124 _bus_dmamem_free, 125 _bus_dmamem_map, 126 _bus_dmamem_unmap, 127 _bus_dmamem_mmap, 128 }; 129 130 #define IDTVEC(name) __CONCAT(X,name) 131 typedef void (vector) __P((void)); 132 extern vector *IDTVEC(intr)[]; 133 134 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < NUM_LEGACY_IRQS && (x) != 2) 135 136 int 137 isa_intr_alloc(isa_chipset_tag_t ic, int mask, int type, int *irq) 138 { 139 int i, tmp, bestirq, count; 140 struct intrhand **p, *q; 141 struct intrsource *isp; 142 struct cpu_info *ci; 143 144 if (type == IST_NONE) 145 panic("intr_alloc: bogus type"); 146 147 ci = &cpu_info_primary; 148 149 bestirq = -1; 150 count = -1; 151 152 /* some interrupts should never be dynamically allocated */ 153 mask &= 0xdef8; 154 155 /* 156 * XXX some interrupts will be used later (6 for fdc, 12 for pms). 157 * the right answer is to do "breadth-first" searching of devices. 158 */ 159 mask &= 0xefbf; 160 161 simple_lock(&ci->ci_slock); 162 163 for (i = 0; i < NUM_LEGACY_IRQS; i++) { 164 if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0) 165 continue; 166 isp = ci->ci_isources[i]; 167 if (isp == NULL) { 168 /* 169 * if nothing's using the irq, just return it 170 */ 171 *irq = i; 172 simple_unlock(&ci->ci_slock); 173 return (0); 174 } 175 176 switch(isp->is_type) { 177 case IST_EDGE: 178 case IST_LEVEL: 179 if (type != isp->is_type) 180 continue; 181 /* 182 * if the irq is shareable, count the number of other 183 * handlers, and if it's smaller than the last irq like 184 * this, remember it 185 * 186 * XXX We should probably also consider the 187 * interrupt level and stick IPL_TTY with other 188 * IPL_TTY, etc. 189 */ 190 for (p = &isp->is_handlers, tmp = 0; (q = *p) != NULL; 191 p = &q->ih_next, tmp++) 192 ; 193 if ((bestirq == -1) || (count > tmp)) { 194 bestirq = i; 195 count = tmp; 196 } 197 break; 198 199 case IST_PULSE: 200 /* this just isn't shareable */ 201 continue; 202 } 203 } 204 205 simple_unlock(&ci->ci_slock); 206 207 if (bestirq == -1) 208 return (1); 209 210 *irq = bestirq; 211 212 return (0); 213 } 214 215 const struct evcnt * 216 isa_intr_evcnt(isa_chipset_tag_t ic, int irq) 217 { 218 219 /* XXX for now, no evcnt parent reported */ 220 return NULL; 221 } 222 223 void * 224 isa_intr_establish(ic, irq, type, level, ih_fun, ih_arg) 225 isa_chipset_tag_t ic; 226 int irq; 227 int type; 228 int level; 229 int (*ih_fun) __P((void *)); 230 void *ih_arg; 231 { 232 struct pic *pic; 233 int pin; 234 #if NIOAPIC > 0 235 int mpih; 236 #endif 237 238 pin = irq; 239 pic = &i8259_pic; 240 241 #if NIOAPIC > 0 242 if (mp_busses != NULL) { 243 if (intr_find_mpmapping(mp_isa_bus, irq, &mpih) == 0 || 244 intr_find_mpmapping(mp_eisa_bus, irq, &mpih) == 0) { 245 if (!APIC_IRQ_ISLEGACY(mpih)) { 246 pin = APIC_IRQ_PIN(mpih); 247 pic = (struct pic *) 248 ioapic_find(APIC_IRQ_APIC(mpih)); 249 if (pic == NULL) { 250 printf("isa_intr_establish: " 251 "unknown apic %d\n", 252 APIC_IRQ_APIC(mpih)); 253 return NULL; 254 } 255 } 256 } else 257 printf("isa_intr_establish: no MP mapping found\n"); 258 } 259 #endif 260 return intr_establish(irq, pic, pin, type, level, ih_fun, ih_arg); 261 } 262 263 /* 264 * Deregister an interrupt handler. 265 */ 266 void 267 isa_intr_disestablish(ic, arg) 268 isa_chipset_tag_t ic; 269 void *arg; 270 { 271 struct intrhand *ih = arg; 272 273 if (!LEGAL_IRQ(ih->ih_pin)) 274 panic("intr_disestablish: bogus irq"); 275 276 intr_disestablish(ih); 277 } 278 279 void 280 isa_attach_hook(parent, self, iba) 281 struct device *parent, *self; 282 struct isabus_attach_args *iba; 283 { 284 extern struct x86_isa_chipset x86_isa_chipset; 285 extern int isa_has_been_seen; 286 287 /* 288 * Notify others that might need to know that the ISA bus 289 * has now been attached. 290 */ 291 if (isa_has_been_seen) 292 panic("isaattach: ISA bus already seen!"); 293 isa_has_been_seen = 1; 294 295 /* 296 * Since we can only have one ISA bus, we just use a single 297 * statically allocated ISA chipset structure. Pass it up 298 * now. 299 */ 300 iba->iba_ic = &x86_isa_chipset; 301 } 302 303 int 304 isa_mem_alloc(t, size, align, boundary, flags, addrp, bshp) 305 bus_space_tag_t t; 306 bus_size_t size, align; 307 bus_addr_t boundary; 308 int flags; 309 bus_addr_t *addrp; 310 bus_space_handle_t *bshp; 311 { 312 313 /* 314 * Allocate physical address space in the ISA hole. 315 */ 316 return (bus_space_alloc(t, IOM_BEGIN, IOM_END - 1, size, align, 317 boundary, flags, addrp, bshp)); 318 } 319 320 void 321 isa_mem_free(t, bsh, size) 322 bus_space_tag_t t; 323 bus_space_handle_t bsh; 324 bus_size_t size; 325 { 326 327 bus_space_free(t, bsh, size); 328 } 329 330 /* 331 * ISA only has 24-bits of address space. This means 332 * we can't DMA to pages over 16M. In order to DMA to 333 * arbitrary buffers, we use "bounce buffers" - pages 334 * in memory below the 16M boundary. On DMA reads, 335 * DMA happens to the bounce buffers, and is copied into 336 * the caller's buffer. On writes, data is copied into 337 * but bounce buffer, and the DMA happens from those 338 * pages. To software using the DMA mapping interface, 339 * this looks simply like a data cache. 340 * 341 * If we have more than 16M of RAM in the system, we may 342 * need bounce buffers. We check and remember that here. 343 * 344 * There are exceptions, however. VLB devices can do 345 * 32-bit DMA, and indicate that here. 346 * 347 * ...or, there is an opposite case. The most segments 348 * a transfer will require is (maxxfer / PAGE_SIZE) + 1. If 349 * the caller can't handle that many segments (e.g. the 350 * ISA DMA controller), we may have to bounce it as well. 351 */ 352 static int 353 _isa_dma_may_bounce(bus_dma_tag_t t, bus_dmamap_t map, int flags, 354 int *cookieflagsp) 355 { 356 if ((flags & ISABUS_DMA_32BIT) != 0) 357 map->_dm_bounce_thresh = 0; 358 359 if (((map->_dm_size / PAGE_SIZE) + 1) > map->_dm_segcnt) 360 *cookieflagsp |= X86_DMA_ID_MIGHT_NEED_BOUNCE; 361 return 0; 362 } 363
Indexes created Mon Sep 29 03:10:08 GMT 2025