amdtemp.c revision 1.1
1 /* $NetBSD: amdtemp.c,v 1.1 2008/04/22 22:37:14 cegger Exp $ */ 2 /* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */ 3 4 /* 5 * Copyright (c) 2008 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Christoph Egger. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Copyright (c) 2008 Constantine A. Murenin <cnst+openbsd (at) bugmail.mojo.ru> 38 * 39 * Permission to use, copy, modify, and distribute this software for any 40 * purpose with or without fee is hereby granted, provided that the above 41 * copyright notice and this permission notice appear in all copies. 42 * 43 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 44 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 45 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 46 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 47 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 48 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 49 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 50 */ 51 52 53 #include <sys/cdefs.h> 54 __KERNEL_RCSID(0, "$NetBSD: amdtemp.c,v 1.1 2008/04/22 22:37:14 cegger Exp $ "); 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 #include <sys/kmem.h> 60 #include <dev/sysmon/sysmonvar.h> 61 62 #include <machine/bus.h> 63 #include <machine/cpu.h> 64 #include <machine/specialreg.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 /* 71 * AMD K8: 72 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf 73 * Family10h: 74 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF 75 */ 76 77 /* AMD Proessors, Function 3 -- Miscellaneous Control 78 */ 79 80 /* Function 3 Registers */ 81 #define THERMTRIP_STAT_R 0xe4 82 #define NORTHBRIDGE_CAP_R 0xe8 83 #define CPUID_FAMILY_MODEL_R 0xfc 84 85 /* 86 * AMD NPT Family 0Fh Processors, Function 3 -- Miscellaneous Control 87 */ 88 89 /* Bits within Thermtrip Status Register */ 90 #define K8_THERM_SENSE_SEL (1 << 6) 91 #define K8_THERM_SENSE_CORE_SEL (1 << 2) 92 93 /* Flip core and sensor selection bits */ 94 #define K8_T_SEL_C0(v) (v |= K8_THERM_SENSE_CORE_SEL) 95 #define K8_T_SEL_C1(v) (v &= ~(K8_THERM_SENSE_CORE_SEL)) 96 #define K8_T_SEL_S0(v) (v &= ~(K8_THERM_SENSE_SEL)) 97 #define K8_T_SEL_S1(v) (v |= K8_THERM_SENSE_SEL) 98 99 100 101 /* 102 * AMD Family 10h Processorcs, Function 3 -- Miscellaneous Control 103 */ 104 105 /* Function 3 Registers */ 106 #define F10_TEMPERATURE_CTL_R 0xa4 107 108 /* Bits within Reported Temperature Control Register */ 109 #define F10_TEMP_CURTEMP (1 << 21) 110 111 /* 112 * Revision Guide for AMD NPT Family 0Fh Processors, 113 * Publication # 33610, Revision 3.30, February 2008 114 */ 115 static const struct { 116 const char rev[5]; 117 const pcireg_t cpuid[5]; 118 } amdtemp_core[] = { 119 { "BH-F", { 0x00040FB0, 0x00040F80, 0, 0, 0 } }, /* F2 */ 120 { "DH-F", { 0x00040FF0, 0x00050FF0, 0x00040FC0, 0, 0 } }, /* F2, F3 */ 121 { "JH-F", { 0x00040F10, 0x00040F30, 0x000C0F10, 0, 0 } }, /* F2, F3 */ 122 { "BH-G", { 0x00060FB0, 0x00060F80, 0, 0, 0 } }, /* G1, G2 */ 123 { "DH-G", { 0x00070FF0, 0x00060FF0, 124 0x00060FC0, 0x00070FC0, 0 } } /* G1, G2 */ 125 }; 126 127 128 struct amdtemp_softc { 129 pci_chipset_tag_t sc_pc; 130 pcitag_t sc_pcitag; 131 132 struct sysmon_envsys *sc_sme; 133 envsys_data_t *sc_sensor; 134 135 char sc_rev; 136 int8_t sc_numsensors; 137 uint32_t sc_family; 138 }; 139 140 141 static int amdtemp_match(device_t, cfdata_t, void *); 142 static void amdtemp_attach(device_t, device_t, void *); 143 144 static void amdtemp_k8_init(struct amdtemp_softc *, pcireg_t); 145 static void amdtemp_k8_setup_sensors(struct amdtemp_softc *, int); 146 static void amdtemp_k8_refresh(struct sysmon_envsys *, envsys_data_t *); 147 148 static void amdtemp_family10_init(struct amdtemp_softc *); 149 static void amdtemp_family10_setup_sensors(struct amdtemp_softc *, int); 150 static void amdtemp_family10_refresh(struct sysmon_envsys *, envsys_data_t *); 151 152 CFATTACH_DECL_NEW(amdtemp, sizeof(struct amdtemp_softc), 153 amdtemp_match, amdtemp_attach, NULL, NULL); 154 155 static int 156 amdtemp_match(device_t parent, cfdata_t match, void *aux) 157 { 158 struct pci_attach_args *pa = aux; 159 pcireg_t cpu_signature; 160 uint32_t family; 161 162 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 163 return 0; 164 165 switch (PCI_PRODUCT(pa->pa_id)) { 166 case PCI_PRODUCT_AMD_AMD64_MISC: 167 case PCI_PRODUCT_AMD_AMD64_F10_MISC: 168 case PCI_PRODUCT_AMD_AMD64_F11_MISC: 169 break; 170 default: 171 return 0; 172 } 173 174 cpu_signature = pci_conf_read(pa->pa_pc, pa->pa_tag, 175 CPUID_FAMILY_MODEL_R); 176 177 /* This CPUID northbridge register has been introduced 178 * in Revision F */ 179 if (cpu_signature == 0x0) 180 return 0; 181 182 family = CPUID2FAMILY(cpu_signature); 183 if (family == 0xf) 184 family += CPUID2EXTFAMILY(cpu_signature); 185 186 /* Not yet supported CPUs */ 187 if (family >= 0x12) 188 return 0; 189 190 return 2; /* supercede pchb(4) */ 191 } 192 193 static void 194 amdtemp_attach(device_t parent, device_t self, void *aux) 195 { 196 struct amdtemp_softc *sc = device_private(self); 197 struct pci_attach_args *pa = aux; 198 pcireg_t cpu_signature; 199 size_t len; 200 int error; 201 uint8_t i; 202 203 aprint_naive("\n"); 204 aprint_normal("\n"); 205 206 aprint_normal_dev(self, "AMD CPU Temperature Sensors"); 207 208 cpu_signature = pci_conf_read(pa->pa_pc, pa->pa_tag, 209 CPUID_FAMILY_MODEL_R); 210 211 /* If we hit this, then match routine is wrong. */ 212 KASSERT(cpu_signature != 0x0); 213 214 sc->sc_family = CPUID2FAMILY(cpu_signature) 215 + CPUID2EXTFAMILY(cpu_signature); 216 KASSERT(sc->sc_family >= 0xf); 217 218 sc->sc_pc = pa->pa_pc; 219 sc->sc_pcitag = pa->pa_tag; 220 221 switch (sc->sc_family) { 222 case 0xf: /* AMD K8 NPT */ 223 amdtemp_k8_init(sc, cpu_signature); 224 break; 225 226 case 0x10: /* AMD Barcelona/Phenom */ 227 case 0x11: /* AMD Griffin */ 228 amdtemp_family10_init(sc); 229 break; 230 231 default: 232 /* Not supported */ 233 return; 234 } 235 236 aprint_normal("\n"); 237 238 sc->sc_sme = sysmon_envsys_create(); 239 len = sizeof(envsys_data_t) * sc->sc_numsensors; 240 sc->sc_sensor = kmem_zalloc(len, KM_NOSLEEP); 241 if (!sc->sc_sensor) 242 goto bad2; 243 244 switch (sc->sc_family) { 245 case 0xf: 246 amdtemp_k8_setup_sensors(sc, device_unit(self)); 247 break; 248 case 0x10: 249 case 0x11: 250 amdtemp_family10_setup_sensors(sc, device_unit(self)); 251 break; 252 } 253 254 /* 255 * Set properties in sensors. 256 */ 257 for (i = 0; i < sc->sc_numsensors; i++) { 258 if (sysmon_envsys_sensor_attach(sc->sc_sme, 259 &sc->sc_sensor[i])) 260 goto bad; 261 } 262 263 /* 264 * Register the sysmon_envsys device. 265 */ 266 sc->sc_sme->sme_name = device_xname(self); 267 sc->sc_sme->sme_cookie = sc; 268 269 switch (sc->sc_family) { 270 case 0xf: 271 sc->sc_sme->sme_refresh = amdtemp_k8_refresh; 272 break; 273 case 0x10: 274 case 0x11: 275 sc->sc_sme->sme_refresh = amdtemp_family10_refresh; 276 break; 277 } 278 279 error = sysmon_envsys_register(sc->sc_sme); 280 if (error) { 281 aprint_error_dev(self, "unable to register with sysmon " 282 "(error=%d)\n", error); 283 goto bad; 284 } 285 286 if (!pmf_device_register(self, NULL, NULL)) 287 aprint_error_dev(self, "couldn't establish power handler\n"); 288 289 return; 290 291 bad: 292 kmem_free(sc->sc_sensor, len); 293 bad2: 294 sysmon_envsys_destroy(sc->sc_sme); 295 } 296 297 static void 298 amdtemp_k8_init(struct amdtemp_softc *sc, pcireg_t cpu_signature) 299 { 300 pcireg_t data; 301 uint32_t cmpcap; 302 uint8_t i, j; 303 304 aprint_normal(" (K8"); 305 306 for (i = 0; i < __arraycount(amdtemp_core) && sc->sc_rev == '\0'; i++) { 307 for (j = 0; amdtemp_core[i].cpuid[j] != 0; j++) { 308 if ((cpu_signature & ~0xf) 309 == amdtemp_core[i].cpuid[j]) 310 { 311 sc->sc_rev = amdtemp_core[i].rev[3]; 312 aprint_normal(": core rev %.4s%.1x", 313 amdtemp_core[i].rev, 314 CPUID2STEPPING(cpu_signature)); 315 } 316 } 317 } 318 319 if (sc->sc_rev == '\0') { 320 /* CPUID Family Model Register was introduced in 321 * Revision F */ 322 sc->sc_rev = 'G'; /* newer than E, assume G */ 323 aprint_normal(": cpuid 0x%x", cpu_signature); 324 } 325 326 aprint_normal(")"); 327 328 data = pci_conf_read(sc->sc_pc, sc->sc_pcitag, NORTHBRIDGE_CAP_R); 329 cmpcap = (data >> 12) & 0x3; 330 331 sc->sc_numsensors = cmpcap ? 4 : 2; 332 } 333 334 335 static void 336 amdtemp_k8_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 337 { 338 uint8_t i; 339 340 /* There are two sensors per CPU core. So we use the 341 * device unit as socket counter to correctly enumerate 342 * the CPUs on multi-socket machines. 343 */ 344 dv_unit *= (sc->sc_numsensors / 2); 345 for (i = 0; i < sc->sc_numsensors; i++) { 346 sc->sc_sensor[i].units = ENVSYS_STEMP; 347 sc->sc_sensor[i].state = ENVSYS_SVALID; 348 349 snprintf(sc->sc_sensor[i].desc, sizeof(sc->sc_sensor[i].desc), 350 "CPU%u Sensor%u", dv_unit + (i / 2), i % 2); 351 } 352 } 353 354 355 static void 356 amdtemp_k8_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 357 { 358 struct amdtemp_softc *sc = sme->sme_cookie; 359 pcireg_t status, match, tmp; 360 uint32_t value; 361 362 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 363 364 switch(edata->sensor) { /* sensor number */ 365 case 0: /* Core 0 Sensor 0 */ 366 K8_T_SEL_C0(status); 367 K8_T_SEL_S0(status); 368 break; 369 case 1: /* Core 0 Sensor 1 */ 370 K8_T_SEL_C0(status); 371 K8_T_SEL_S1(status); 372 break; 373 case 2: /* Core 1 Sensor 0 */ 374 K8_T_SEL_C1(status); 375 K8_T_SEL_S0(status); 376 break; 377 case 3: /* Core 1 Sensor 1 */ 378 K8_T_SEL_C1(status); 379 K8_T_SEL_S1(status); 380 break; 381 } 382 383 match = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 384 pci_conf_write(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R, status); 385 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 386 tmp = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 387 388 value = 0x3ff & (status >> 14); 389 if (sc->sc_rev != 'G') 390 value &= ~0x3; 391 392 edata->state = ENVSYS_SINVALID; 393 if ((tmp == match) && ((value & ~0x3) != 0)) { 394 edata->state = ENVSYS_SVALID; 395 edata->value_cur = (value * 250000 - 49000000) + 273150000; 396 } 397 } 398 399 400 static void 401 amdtemp_family10_init(struct amdtemp_softc *sc) 402 { 403 aprint_normal(" (Family10h)"); 404 405 sc->sc_numsensors = 1; 406 } 407 408 static void 409 amdtemp_family10_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 410 { 411 /* sanity check for future enhancements */ 412 KASSERT(sc->sc_numsensors == 1); 413 414 /* There's one sensor per memory controller (= socket) 415 * so we use the device unit as socket counter 416 * to correctly enumerate the CPUs 417 */ 418 sc->sc_sensor[0].units = ENVSYS_STEMP; 419 sc->sc_sensor[0].state = ENVSYS_SVALID; 420 421 snprintf(sc->sc_sensor[0].desc, sizeof(sc->sc_sensor[0].desc), 422 "CPU%u Sensor0", dv_unit); 423 } 424 425 426 static void 427 amdtemp_family10_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 428 { 429 struct amdtemp_softc *sc = sme->sme_cookie; 430 pcireg_t status; 431 uint32_t value; 432 433 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, F10_TEMPERATURE_CTL_R); 434 435 value = (status >> 21); 436 437 edata->state = ENVSYS_SVALID; 438 edata->value_cur = (value * 125000) + 255875000; 439 } 440
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