amdtemp.c revision 1.1.2.2
1 /* $NetBSD: amdtemp.c,v 1.1.2.2 2009/05/04 08:12:10 yamt Exp $ */ 2 /* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */ 3 4 /* 5 * Copyright (c) 2008 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Christoph Egger. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 2008 Constantine A. Murenin <cnst+openbsd (at) bugmail.mojo.ru> 35 * 36 * Permission to use, copy, modify, and distribute this software for any 37 * purpose with or without fee is hereby granted, provided that the above 38 * copyright notice and this permission notice appear in all copies. 39 * 40 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 41 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 42 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 43 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 44 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 45 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 46 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 47 */ 48 49 50 #include <sys/cdefs.h> 51 __KERNEL_RCSID(0, "$NetBSD: amdtemp.c,v 1.1.2.2 2009/05/04 08:12:10 yamt Exp $ "); 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/device.h> 56 #include <sys/kmem.h> 57 #include <dev/sysmon/sysmonvar.h> 58 59 #include <machine/bus.h> 60 #include <machine/cpu.h> 61 #include <machine/specialreg.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 67 /* 68 * AMD K8: 69 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf 70 * Family10h: 71 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF 72 */ 73 74 /* AMD Proessors, Function 3 -- Miscellaneous Control 75 */ 76 77 /* Function 3 Registers */ 78 #define THERMTRIP_STAT_R 0xe4 79 #define NORTHBRIDGE_CAP_R 0xe8 80 #define CPUID_FAMILY_MODEL_R 0xfc 81 82 /* 83 * AMD NPT Family 0Fh Processors, Function 3 -- Miscellaneous Control 84 */ 85 86 /* Bits within Thermtrip Status Register */ 87 #define K8_THERM_SENSE_SEL (1 << 6) 88 #define K8_THERM_SENSE_CORE_SEL (1 << 2) 89 90 /* Flip core and sensor selection bits */ 91 #define K8_T_SEL_C0(v) (v |= K8_THERM_SENSE_CORE_SEL) 92 #define K8_T_SEL_C1(v) (v &= ~(K8_THERM_SENSE_CORE_SEL)) 93 #define K8_T_SEL_S0(v) (v &= ~(K8_THERM_SENSE_SEL)) 94 #define K8_T_SEL_S1(v) (v |= K8_THERM_SENSE_SEL) 95 96 97 98 /* 99 * AMD Family 10h Processorcs, Function 3 -- Miscellaneous Control 100 */ 101 102 /* Function 3 Registers */ 103 #define F10_TEMPERATURE_CTL_R 0xa4 104 105 /* Bits within Reported Temperature Control Register */ 106 #define F10_TEMP_CURTEMP (1 << 21) 107 108 /* 109 * Revision Guide for AMD NPT Family 0Fh Processors, 110 * Publication # 33610, Revision 3.30, February 2008 111 */ 112 #define K8_SOCKET_F 1 /* Server */ 113 #define K8_SOCKET_AM2 2 /* Desktop */ 114 #define K8_SOCKET_S1 3 /* Laptop */ 115 116 static const struct { 117 const char rev[5]; 118 const struct { 119 const pcireg_t cpuid; 120 const uint8_t socket; 121 } cpu[5]; 122 } amdtemp_core[] = { 123 { "BH-F", { { 0x00040FB0, K8_SOCKET_AM2 }, /* F2 */ 124 { 0x00040F80, K8_SOCKET_S1 }, /* F2 */ 125 { 0, 0 }, { 0, 0 }, { 0, 0 } } }, 126 { "DH-F", { { 0x00040FF0, K8_SOCKET_AM2 }, /* F2 */ 127 { 0x00040FC0, K8_SOCKET_S1 }, /* F2 */ 128 { 0x00050FF0, K8_SOCKET_AM2 }, /* F2, F3 */ 129 { 0, 0 }, { 0, 0 } } }, 130 { "JH-F", { { 0x00040F10, K8_SOCKET_F }, /* F2, F3 */ 131 { 0x00040F30, K8_SOCKET_AM2 }, /* F2, F3 */ 132 { 0x000C0F10, K8_SOCKET_F }, /* F3 */ 133 { 0, 0 }, { 0, 0 } } }, 134 { "BH-G", { { 0x00060FB0, K8_SOCKET_AM2 }, /* G1, G2 */ 135 { 0x00060F80, K8_SOCKET_S1 }, /* G1, G2 */ 136 { 0, 0 }, { 0, 0 }, { 0, 0 } } }, 137 { "DH-G", { { 0x00060FF0, K8_SOCKET_AM2 }, /* G1, G2 */ 138 { 0x00060FC0, K8_SOCKET_S1 }, /* G2 */ 139 { 0x00070FF0, K8_SOCKET_AM2 }, /* G1, G2 */ 140 { 0x00070FC0, K8_SOCKET_S1 }, /* G2 */ 141 { 0, 0 } } } 142 }; 143 144 145 struct amdtemp_softc { 146 pci_chipset_tag_t sc_pc; 147 pcitag_t sc_pcitag; 148 149 struct sysmon_envsys *sc_sme; 150 envsys_data_t *sc_sensor; 151 152 char sc_rev; 153 int8_t sc_numsensors; 154 uint32_t sc_family; 155 int32_t sc_adjustment; 156 }; 157 158 159 static int amdtemp_match(device_t, cfdata_t, void *); 160 static void amdtemp_attach(device_t, device_t, void *); 161 162 static void amdtemp_k8_init(struct amdtemp_softc *, pcireg_t); 163 static void amdtemp_k8_setup_sensors(struct amdtemp_softc *, int); 164 static void amdtemp_k8_refresh(struct sysmon_envsys *, envsys_data_t *); 165 166 static void amdtemp_family10_init(struct amdtemp_softc *); 167 static void amdtemp_family10_setup_sensors(struct amdtemp_softc *, int); 168 static void amdtemp_family10_refresh(struct sysmon_envsys *, envsys_data_t *); 169 170 CFATTACH_DECL_NEW(amdtemp, sizeof(struct amdtemp_softc), 171 amdtemp_match, amdtemp_attach, NULL, NULL); 172 173 static int 174 amdtemp_match(device_t parent, cfdata_t match, void *aux) 175 { 176 struct pci_attach_args *pa = aux; 177 pcireg_t cpu_signature; 178 uint32_t family; 179 180 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 181 return 0; 182 183 switch (PCI_PRODUCT(pa->pa_id)) { 184 case PCI_PRODUCT_AMD_AMD64_MISC: 185 case PCI_PRODUCT_AMD_AMD64_F10_MISC: 186 case PCI_PRODUCT_AMD_AMD64_F11_MISC: 187 break; 188 default: 189 return 0; 190 } 191 192 cpu_signature = pci_conf_read(pa->pa_pc, pa->pa_tag, 193 CPUID_FAMILY_MODEL_R); 194 195 /* This CPUID northbridge register has been introduced 196 * in Revision F */ 197 if (cpu_signature == 0x0) 198 return 0; 199 200 family = CPUID2FAMILY(cpu_signature); 201 if (family == 0xf) 202 family += CPUID2EXTFAMILY(cpu_signature); 203 204 /* Not yet supported CPUs */ 205 if (family >= 0x12) 206 return 0; 207 208 return 2; /* supercede pchb(4) */ 209 } 210 211 static void 212 amdtemp_attach(device_t parent, device_t self, void *aux) 213 { 214 struct amdtemp_softc *sc = device_private(self); 215 struct pci_attach_args *pa = aux; 216 pcireg_t cpu_signature; 217 size_t len; 218 int error; 219 uint8_t i; 220 221 aprint_naive("\n"); 222 aprint_normal(": AMD CPU Temperature Sensors"); 223 224 cpu_signature = pci_conf_read(pa->pa_pc, pa->pa_tag, 225 CPUID_FAMILY_MODEL_R); 226 227 /* If we hit this, then match routine is wrong. */ 228 KASSERT(cpu_signature != 0x0); 229 230 sc->sc_family = CPUID2FAMILY(cpu_signature) 231 + CPUID2EXTFAMILY(cpu_signature); 232 KASSERT(sc->sc_family >= 0xf); 233 234 sc->sc_pc = pa->pa_pc; 235 sc->sc_pcitag = pa->pa_tag; 236 sc->sc_adjustment = 0; 237 238 switch (sc->sc_family) { 239 case 0xf: /* AMD K8 NPT */ 240 amdtemp_k8_init(sc, cpu_signature); 241 break; 242 243 case 0x10: /* AMD Barcelona/Phenom */ 244 case 0x11: /* AMD Griffin */ 245 amdtemp_family10_init(sc); 246 break; 247 248 default: 249 aprint_normal(", family 0x%x not supported\n", 250 sc->sc_family); 251 return; 252 } 253 254 aprint_normal("\n"); 255 256 if (sc->sc_adjustment != 0) 257 aprint_debug_dev(self, "Workaround enabled\n"); 258 259 sc->sc_sme = sysmon_envsys_create(); 260 len = sizeof(envsys_data_t) * sc->sc_numsensors; 261 sc->sc_sensor = kmem_zalloc(len, KM_NOSLEEP); 262 if (!sc->sc_sensor) 263 goto bad2; 264 265 switch (sc->sc_family) { 266 case 0xf: 267 amdtemp_k8_setup_sensors(sc, device_unit(self)); 268 break; 269 case 0x10: 270 case 0x11: 271 amdtemp_family10_setup_sensors(sc, device_unit(self)); 272 break; 273 } 274 275 /* 276 * Set properties in sensors. 277 */ 278 for (i = 0; i < sc->sc_numsensors; i++) { 279 if (sysmon_envsys_sensor_attach(sc->sc_sme, 280 &sc->sc_sensor[i])) 281 goto bad; 282 } 283 284 /* 285 * Register the sysmon_envsys device. 286 */ 287 sc->sc_sme->sme_name = device_xname(self); 288 sc->sc_sme->sme_cookie = sc; 289 290 switch (sc->sc_family) { 291 case 0xf: 292 sc->sc_sme->sme_refresh = amdtemp_k8_refresh; 293 break; 294 case 0x10: 295 case 0x11: 296 sc->sc_sme->sme_refresh = amdtemp_family10_refresh; 297 break; 298 } 299 300 error = sysmon_envsys_register(sc->sc_sme); 301 if (error) { 302 aprint_error_dev(self, "unable to register with sysmon " 303 "(error=%d)\n", error); 304 goto bad; 305 } 306 307 if (!pmf_device_register(self, NULL, NULL)) 308 aprint_error_dev(self, "couldn't establish power handler\n"); 309 310 return; 311 312 bad: 313 kmem_free(sc->sc_sensor, len); 314 bad2: 315 sysmon_envsys_destroy(sc->sc_sme); 316 } 317 318 static void 319 amdtemp_k8_init(struct amdtemp_softc *sc, pcireg_t cpu_signature) 320 { 321 pcireg_t data; 322 uint32_t cmpcap; 323 uint8_t i, j; 324 325 aprint_normal(" (K8"); 326 327 for (i = 0; i < __arraycount(amdtemp_core) && sc->sc_rev == '\0'; i++) { 328 for (j = 0; amdtemp_core[i].cpu[j].cpuid != 0; j++) { 329 if ((cpu_signature & ~0xf) 330 != amdtemp_core[i].cpu[j].cpuid) 331 continue; 332 333 sc->sc_rev = amdtemp_core[i].rev[3]; 334 aprint_normal(": core rev %.4s%.1x", 335 amdtemp_core[i].rev, 336 CPUID2STEPPING(cpu_signature)); 337 338 switch (amdtemp_core[i].cpu[j].socket) { 339 case K8_SOCKET_AM2: 340 if (sc->sc_rev == 'G') 341 sc->sc_adjustment = 21000000; 342 aprint_normal(", socket AM2"); 343 break; 344 case K8_SOCKET_S1: 345 aprint_normal(", socket S1"); 346 break; 347 case K8_SOCKET_F: 348 aprint_normal(", socket F"); 349 break; 350 } 351 } 352 } 353 354 if (sc->sc_rev == '\0') { 355 /* CPUID Family Model Register was introduced in 356 * Revision F */ 357 sc->sc_rev = 'G'; /* newer than E, assume G */ 358 aprint_normal(": cpuid 0x%x", cpu_signature); 359 } 360 361 aprint_normal(")"); 362 363 data = pci_conf_read(sc->sc_pc, sc->sc_pcitag, NORTHBRIDGE_CAP_R); 364 cmpcap = (data >> 12) & 0x3; 365 366 sc->sc_numsensors = cmpcap ? 4 : 2; 367 } 368 369 370 static void 371 amdtemp_k8_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 372 { 373 uint8_t i; 374 375 /* There are two sensors per CPU core. So we use the 376 * device unit as socket counter to correctly enumerate 377 * the CPUs on multi-socket machines. 378 */ 379 dv_unit *= (sc->sc_numsensors / 2); 380 for (i = 0; i < sc->sc_numsensors; i++) { 381 sc->sc_sensor[i].units = ENVSYS_STEMP; 382 sc->sc_sensor[i].state = ENVSYS_SVALID; 383 384 snprintf(sc->sc_sensor[i].desc, sizeof(sc->sc_sensor[i].desc), 385 "CPU%u Sensor%u", dv_unit + (i / 2), i % 2); 386 } 387 } 388 389 390 static void 391 amdtemp_k8_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 392 { 393 struct amdtemp_softc *sc = sme->sme_cookie; 394 pcireg_t status, match, tmp; 395 uint32_t value; 396 397 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 398 399 switch(edata->sensor) { /* sensor number */ 400 case 0: /* Core 0 Sensor 0 */ 401 K8_T_SEL_C0(status); 402 K8_T_SEL_S0(status); 403 break; 404 case 1: /* Core 0 Sensor 1 */ 405 K8_T_SEL_C0(status); 406 K8_T_SEL_S1(status); 407 break; 408 case 2: /* Core 1 Sensor 0 */ 409 K8_T_SEL_C1(status); 410 K8_T_SEL_S0(status); 411 break; 412 case 3: /* Core 1 Sensor 1 */ 413 K8_T_SEL_C1(status); 414 K8_T_SEL_S1(status); 415 break; 416 } 417 418 match = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 419 pci_conf_write(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R, status); 420 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 421 tmp = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 422 423 value = 0x3ff & (status >> 14); 424 if (sc->sc_rev != 'G') 425 value &= ~0x3; 426 427 edata->state = ENVSYS_SINVALID; 428 if ((tmp == match) && ((value & ~0x3) != 0)) { 429 edata->state = ENVSYS_SVALID; 430 edata->value_cur = (value * 250000 - 49000000) + 273150000 431 + sc->sc_adjustment; 432 } 433 } 434 435 436 static void 437 amdtemp_family10_init(struct amdtemp_softc *sc) 438 { 439 aprint_normal(" (Family10h / Family11h)"); 440 441 sc->sc_numsensors = 1; 442 } 443 444 static void 445 amdtemp_family10_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 446 { 447 /* sanity check for future enhancements */ 448 KASSERT(sc->sc_numsensors == 1); 449 450 /* There's one sensor per memory controller (= socket) 451 * so we use the device unit as socket counter 452 * to correctly enumerate the CPUs 453 */ 454 sc->sc_sensor[0].units = ENVSYS_STEMP; 455 sc->sc_sensor[0].state = ENVSYS_SVALID; 456 457 snprintf(sc->sc_sensor[0].desc, sizeof(sc->sc_sensor[0].desc), 458 "CPU%u Sensor0", dv_unit); 459 } 460 461 462 static void 463 amdtemp_family10_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 464 { 465 struct amdtemp_softc *sc = sme->sme_cookie; 466 pcireg_t status; 467 uint32_t value; 468 469 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, F10_TEMPERATURE_CTL_R); 470 471 value = (status >> 21); 472 473 edata->state = ENVSYS_SVALID; 474 /* envsys(4) wants uK... convert from Celsius. */ 475 edata->value_cur = (value * 125000) + 273150000; 476 } 477
Indexes created Thu Oct 02 14:10:14 GMT 2025