amdtemp.c revision 1.20.8.1
1 /* $NetBSD: amdtemp.c,v 1.20.8.1 2018/09/30 01:45:48 pgoyette Exp $ */ 2 /* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */ 3 4 /* 5 * Copyright (c) 2008 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Christoph Egger. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 2008 Constantine A. Murenin <cnst+openbsd (at) bugmail.mojo.ru> 35 * 36 * Permission to use, copy, modify, and distribute this software for any 37 * purpose with or without fee is hereby granted, provided that the above 38 * copyright notice and this permission notice appear in all copies. 39 * 40 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 41 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 42 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 43 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 44 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 45 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 46 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: amdtemp.c,v 1.20.8.1 2018/09/30 01:45:48 pgoyette Exp $ "); 51 52 #include <sys/param.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/systm.h> 56 #include <sys/device.h> 57 #include <sys/kmem.h> 58 #include <sys/module.h> 59 60 #include <machine/specialreg.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcidevs.h> 65 66 #include <dev/sysmon/sysmonvar.h> 67 68 /* 69 * AMD K8: 70 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf 71 * AMD K8 Errata: #141 72 * http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf 73 * 74 * Family10h: 75 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF 76 * Family10h Errata: #319 77 * http://support.amd.com/de/Processor_TechDocs/41322.pdf 78 * 79 * Family11h: 80 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/41256.pdf 81 */ 82 83 /* AMD Processors, Function 3 -- Miscellaneous Control 84 */ 85 86 /* Function 3 Registers */ 87 #define THERMTRIP_STAT_R 0xe4 88 #define NORTHBRIDGE_CAP_R 0xe8 89 #define CPUID_FAMILY_MODEL_R 0xfc 90 91 /* 92 * AMD NPT Family 0Fh Processors, Function 3 -- Miscellaneous Control 93 */ 94 95 /* Bits within Thermtrip Status Register */ 96 #define K8_THERM_SENSE_SEL (1 << 6) 97 #define K8_THERM_SENSE_CORE_SEL (1 << 2) 98 99 /* Flip core and sensor selection bits */ 100 #define K8_T_SEL_C0(v) (v |= K8_THERM_SENSE_CORE_SEL) 101 #define K8_T_SEL_C1(v) (v &= ~(K8_THERM_SENSE_CORE_SEL)) 102 #define K8_T_SEL_S0(v) (v &= ~(K8_THERM_SENSE_SEL)) 103 #define K8_T_SEL_S1(v) (v |= K8_THERM_SENSE_SEL) 104 105 /* 106 * AMD Family 10h Processors, Function 3 -- Miscellaneous Control 107 */ 108 109 /* Function 3 Registers */ 110 #define F10_TEMPERATURE_CTL_R 0xa4 111 #define F10_TEMP_CURTMP __BITS(31,21) 112 113 /* 114 * Revision Guide for AMD NPT Family 0Fh Processors, 115 * Publication # 33610, Revision 3.30, February 2008 116 */ 117 #define K8_SOCKET_F 1 /* Server */ 118 #define K8_SOCKET_AM2 2 /* Desktop */ 119 #define K8_SOCKET_S1 3 /* Laptop */ 120 121 static const struct { 122 const char rev[5]; 123 const struct { 124 const pcireg_t cpuid; 125 const uint8_t socket; 126 } cpu[5]; 127 } amdtemp_core[] = { 128 { "BH-F", { { 0x00040FB0, K8_SOCKET_AM2 }, /* F2 */ 129 { 0x00040F80, K8_SOCKET_S1 }, /* F2 */ 130 { 0, 0 }, { 0, 0 }, { 0, 0 } } }, 131 { "DH-F", { { 0x00040FF0, K8_SOCKET_AM2 }, /* F2 */ 132 { 0x00040FC0, K8_SOCKET_S1 }, /* F2 */ 133 { 0x00050FF0, K8_SOCKET_AM2 }, /* F2, F3 */ 134 { 0, 0 }, { 0, 0 } } }, 135 { "JH-F", { { 0x00040F10, K8_SOCKET_F }, /* F2, F3 */ 136 { 0x00040F30, K8_SOCKET_AM2 }, /* F2, F3 */ 137 { 0x000C0F10, K8_SOCKET_F }, /* F3 */ 138 { 0, 0 }, { 0, 0 } } }, 139 { "BH-G", { { 0x00060FB0, K8_SOCKET_AM2 }, /* G1, G2 */ 140 { 0x00060F80, K8_SOCKET_S1 }, /* G1, G2 */ 141 { 0, 0 }, { 0, 0 }, { 0, 0 } } }, 142 { "DH-G", { { 0x00060FF0, K8_SOCKET_AM2 }, /* G1, G2 */ 143 { 0x00060FC0, K8_SOCKET_S1 }, /* G2 */ 144 { 0x00070FF0, K8_SOCKET_AM2 }, /* G1, G2 */ 145 { 0x00070FC0, K8_SOCKET_S1 }, /* G2 */ 146 { 0, 0 } } } 147 }; 148 149 struct amdtemp_softc { 150 pci_chipset_tag_t sc_pc; 151 pcitag_t sc_pcitag; 152 153 struct sysmon_envsys *sc_sme; 154 envsys_data_t *sc_sensor; 155 size_t sc_sensor_len; 156 157 char sc_rev; 158 int8_t sc_numsensors; 159 uint32_t sc_family; 160 int32_t sc_adjustment; 161 }; 162 163 static int amdtemp_match(device_t, cfdata_t, void *); 164 static void amdtemp_attach(device_t, device_t, void *); 165 static int amdtemp_detach(device_t, int); 166 167 static void amdtemp_k8_init(struct amdtemp_softc *, pcireg_t); 168 static void amdtemp_k8_setup_sensors(struct amdtemp_softc *, int); 169 static void amdtemp_k8_refresh(struct sysmon_envsys *, envsys_data_t *); 170 171 static void amdtemp_family10_init(struct amdtemp_softc *); 172 static void amdtemp_family10_setup_sensors(struct amdtemp_softc *, int); 173 static void amdtemp_family10_refresh(struct sysmon_envsys *, envsys_data_t *); 174 175 CFATTACH_DECL_NEW(amdtemp, sizeof(struct amdtemp_softc), 176 amdtemp_match, amdtemp_attach, amdtemp_detach, NULL); 177 178 static int 179 amdtemp_match(device_t parent, cfdata_t match, void *aux) 180 { 181 struct pci_attach_args *pa = aux; 182 pcireg_t cpu_signature; 183 uint32_t family; 184 185 KASSERT(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD); 186 187 cpu_signature = pci_conf_read(pa->pa_pc, 188 pa->pa_tag, CPUID_FAMILY_MODEL_R); 189 190 /* 191 * This CPUID northbridge register has been introduced in 192 * Revision F. 193 */ 194 if (cpu_signature == 0x0) 195 return 0; 196 197 family = CPUID_TO_FAMILY(cpu_signature); 198 199 /* Errata #319: This has been fixed in Revision C2. */ 200 if (family == 0x10) { 201 if (CPUID_TO_BASEMODEL(cpu_signature) < 4) 202 return 0; 203 if (CPUID_TO_BASEMODEL(cpu_signature) == 4 && 204 CPUID_TO_STEPPING(cpu_signature) < 2) 205 return 0; 206 } 207 208 /* Not yet supported CPUs. */ 209 if (family > 0x15) 210 return 0; 211 212 return 1; 213 } 214 215 static void 216 amdtemp_attach(device_t parent, device_t self, void *aux) 217 { 218 struct amdtemp_softc *sc = device_private(self); 219 struct pci_attach_args *pa = aux; 220 pcireg_t cpu_signature; 221 int error; 222 uint8_t i; 223 224 aprint_naive("\n"); 225 aprint_normal(": AMD CPU Temperature Sensors"); 226 227 cpu_signature = pci_conf_read(pa->pa_pc, 228 pa->pa_tag, CPUID_FAMILY_MODEL_R); 229 230 /* If we hit this, then match routine is wrong. */ 231 KASSERT(cpu_signature != 0x0); 232 233 sc->sc_family = CPUID_TO_FAMILY(cpu_signature); 234 235 KASSERT(sc->sc_family >= 0xf); 236 237 sc->sc_sme = NULL; 238 sc->sc_sensor = NULL; 239 240 sc->sc_pc = pa->pa_pc; 241 sc->sc_pcitag = pa->pa_tag; 242 sc->sc_adjustment = 0; 243 244 switch (sc->sc_family) { 245 case 0xf: /* AMD K8 NPT */ 246 amdtemp_k8_init(sc, cpu_signature); 247 break; 248 249 case 0x10: /* AMD Barcelona/Phenom */ 250 case 0x11: /* AMD Griffin */ 251 case 0x12: /* AMD Lynx/Sabine (Llano) */ 252 case 0x14: /* AMD Brazos (Ontario/Zacate/Desna) */ 253 case 0x15: 254 amdtemp_family10_init(sc); 255 break; 256 257 default: 258 aprint_normal(", family 0x%x not supported\n", 259 sc->sc_family); 260 return; 261 } 262 263 aprint_normal("\n"); 264 265 if (sc->sc_adjustment != 0) 266 aprint_debug_dev(self, "Workaround enabled\n"); 267 268 sc->sc_sme = sysmon_envsys_create(); 269 sc->sc_sensor_len = sizeof(envsys_data_t) * sc->sc_numsensors; 270 sc->sc_sensor = kmem_zalloc(sc->sc_sensor_len, KM_SLEEP); 271 272 switch (sc->sc_family) { 273 case 0xf: 274 amdtemp_k8_setup_sensors(sc, device_unit(self)); 275 break; 276 case 0x10: 277 case 0x11: 278 case 0x12: 279 case 0x14: 280 case 0x15: 281 amdtemp_family10_setup_sensors(sc, device_unit(self)); 282 break; 283 } 284 285 /* 286 * Set properties in sensors. 287 */ 288 for (i = 0; i < sc->sc_numsensors; i++) { 289 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[i])) 290 goto bad; 291 } 292 293 /* 294 * Register the sysmon_envsys device. 295 */ 296 sc->sc_sme->sme_name = device_xname(self); 297 sc->sc_sme->sme_cookie = sc; 298 299 switch (sc->sc_family) { 300 case 0xf: 301 sc->sc_sme->sme_refresh = amdtemp_k8_refresh; 302 break; 303 case 0x10: 304 case 0x11: 305 case 0x12: 306 case 0x14: 307 case 0x15: 308 sc->sc_sme->sme_refresh = amdtemp_family10_refresh; 309 break; 310 } 311 312 error = sysmon_envsys_register(sc->sc_sme); 313 if (error) { 314 aprint_error_dev(self, "unable to register with sysmon " 315 "(error=%d)\n", error); 316 goto bad; 317 } 318 319 (void)pmf_device_register(self, NULL, NULL); 320 321 return; 322 323 bad: 324 if (sc->sc_sme != NULL) { 325 sysmon_envsys_destroy(sc->sc_sme); 326 sc->sc_sme = NULL; 327 } 328 329 if (sc->sc_sensor != NULL) { 330 kmem_free(sc->sc_sensor, sc->sc_sensor_len); 331 sc->sc_sensor = NULL; 332 } 333 } 334 335 static int 336 amdtemp_detach(device_t self, int flags) 337 { 338 struct amdtemp_softc *sc = device_private(self); 339 340 pmf_device_deregister(self); 341 if (sc->sc_sme != NULL) 342 sysmon_envsys_unregister(sc->sc_sme); 343 344 if (sc->sc_sensor != NULL) 345 kmem_free(sc->sc_sensor, sc->sc_sensor_len); 346 347 return 0; 348 } 349 350 static void 351 amdtemp_k8_init(struct amdtemp_softc *sc, pcireg_t cpu_signature) 352 { 353 pcireg_t data; 354 uint32_t cmpcap; 355 uint8_t i, j; 356 357 aprint_normal(" (K8"); 358 359 for (i = 0; i < __arraycount(amdtemp_core) && sc->sc_rev == '\0'; i++) { 360 for (j = 0; amdtemp_core[i].cpu[j].cpuid != 0; j++) { 361 if ((cpu_signature & ~0xf) 362 != amdtemp_core[i].cpu[j].cpuid) 363 continue; 364 365 sc->sc_rev = amdtemp_core[i].rev[3]; 366 aprint_normal(": core rev %.4s%.1x", 367 amdtemp_core[i].rev, 368 CPUID_TO_STEPPING(cpu_signature)); 369 370 switch (amdtemp_core[i].cpu[j].socket) { 371 case K8_SOCKET_AM2: 372 if (sc->sc_rev == 'G') 373 sc->sc_adjustment = 21000000; 374 aprint_normal(", socket AM2"); 375 break; 376 case K8_SOCKET_S1: 377 aprint_normal(", socket S1"); 378 break; 379 case K8_SOCKET_F: 380 aprint_normal(", socket F"); 381 break; 382 } 383 } 384 } 385 386 if (sc->sc_rev == '\0') { 387 /* 388 * CPUID Family Model Register was introduced in 389 * Revision F 390 */ 391 sc->sc_rev = 'G'; /* newer than E, assume G */ 392 aprint_normal(": cpuid 0x%x", cpu_signature); 393 } 394 395 aprint_normal(")"); 396 397 data = pci_conf_read(sc->sc_pc, sc->sc_pcitag, NORTHBRIDGE_CAP_R); 398 cmpcap = (data >> 12) & 0x3; 399 400 sc->sc_numsensors = cmpcap ? 4 : 2; 401 } 402 403 static void 404 amdtemp_k8_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 405 { 406 uint8_t i; 407 408 /* 409 * There are two sensors per CPU core. So we use the device unit as 410 * socket counter to correctly enumerate the CPUs on multi-socket 411 * machines. 412 */ 413 dv_unit *= (sc->sc_numsensors / 2); 414 for (i = 0; i < sc->sc_numsensors; i++) { 415 sc->sc_sensor[i].units = ENVSYS_STEMP; 416 sc->sc_sensor[i].state = ENVSYS_SVALID; 417 sc->sc_sensor[i].flags = ENVSYS_FHAS_ENTROPY; 418 419 snprintf(sc->sc_sensor[i].desc, sizeof(sc->sc_sensor[i].desc), 420 "CPU%u Sensor%u", dv_unit + (i / 2), i % 2); 421 } 422 } 423 424 static void 425 amdtemp_k8_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 426 { 427 struct amdtemp_softc *sc = sme->sme_cookie; 428 pcireg_t status, match, tmp; 429 uint32_t value; 430 431 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 432 433 switch (edata->sensor) { /* sensor number */ 434 case 0: /* Core 0 Sensor 0 */ 435 K8_T_SEL_C0(status); 436 K8_T_SEL_S0(status); 437 break; 438 case 1: /* Core 0 Sensor 1 */ 439 K8_T_SEL_C0(status); 440 K8_T_SEL_S1(status); 441 break; 442 case 2: /* Core 1 Sensor 0 */ 443 K8_T_SEL_C1(status); 444 K8_T_SEL_S0(status); 445 break; 446 case 3: /* Core 1 Sensor 1 */ 447 K8_T_SEL_C1(status); 448 K8_T_SEL_S1(status); 449 break; 450 } 451 452 match = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 453 pci_conf_write(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R, status); 454 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 455 tmp = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 456 457 value = 0x3ff & (status >> 14); 458 if (sc->sc_rev != 'G') 459 value &= ~0x3; 460 461 edata->state = ENVSYS_SINVALID; 462 if ((tmp == match) && ((value & ~0x3) != 0)) { 463 edata->state = ENVSYS_SVALID; 464 edata->value_cur = (value * 250000 - 49000000) + 273150000 + 465 sc->sc_adjustment; 466 } 467 } 468 469 static void 470 amdtemp_family10_init(struct amdtemp_softc *sc) 471 { 472 aprint_normal(" (Family%02xh)", sc->sc_family); 473 474 sc->sc_numsensors = 1; 475 } 476 477 static void 478 amdtemp_family10_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 479 { 480 /* sanity check for future enhancements */ 481 KASSERT(sc->sc_numsensors == 1); 482 483 /* 484 * There's one sensor per memory controller (= socket), so we use the 485 * device unit as socket counter to correctly enumerate the CPUs. 486 */ 487 sc->sc_sensor[0].units = ENVSYS_STEMP; 488 sc->sc_sensor[0].state = ENVSYS_SVALID; 489 sc->sc_sensor[0].flags = ENVSYS_FHAS_ENTROPY; 490 491 snprintf(sc->sc_sensor[0].desc, sizeof(sc->sc_sensor[0].desc), 492 "cpu%u temperature", dv_unit); 493 } 494 495 static void 496 amdtemp_family10_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 497 { 498 struct amdtemp_softc *sc = sme->sme_cookie; 499 pcireg_t status; 500 uint32_t value; 501 502 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 503 F10_TEMPERATURE_CTL_R); 504 value = __SHIFTOUT(status, F10_TEMP_CURTMP); 505 506 /* From Celsius to micro-Kelvin. */ 507 edata->value_cur = (value * 125000) + 273150000; 508 edata->state = ENVSYS_SVALID; 509 } 510 511 MODULE(MODULE_CLASS_DRIVER, amdtemp, "sysmon_envsys"); 512 513 #ifdef _MODULE 514 #include "ioconf.c" 515 #endif 516 517 static int 518 amdtemp_modcmd(modcmd_t cmd, void *aux) 519 { 520 int error = 0; 521 522 switch (cmd) { 523 case MODULE_CMD_INIT: 524 #ifdef _MODULE 525 error = config_init_component(cfdriver_ioconf_amdtemp, 526 cfattach_ioconf_amdtemp, cfdata_ioconf_amdtemp); 527 #endif 528 return error; 529 case MODULE_CMD_FINI: 530 #ifdef _MODULE 531 error = config_fini_component(cfdriver_ioconf_amdtemp, 532 cfattach_ioconf_amdtemp, cfdata_ioconf_amdtemp); 533 #endif 534 return error; 535 default: 536 return ENOTTY; 537 } 538 } 539
Indexes created Thu Oct 02 14:10:14 GMT 2025