amdtemp.c revision 1.6
1 /* $NetBSD: amdtemp.c,v 1.6 2008/12/04 18:54:24 cegger Exp $ */ 2 /* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */ 3 4 /* 5 * Copyright (c) 2008 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Christoph Egger. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 2008 Constantine A. Murenin <cnst+openbsd (at) bugmail.mojo.ru> 35 * 36 * Permission to use, copy, modify, and distribute this software for any 37 * purpose with or without fee is hereby granted, provided that the above 38 * copyright notice and this permission notice appear in all copies. 39 * 40 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 41 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 42 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 43 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 44 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 45 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 46 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 47 */ 48 49 50 #include <sys/cdefs.h> 51 __KERNEL_RCSID(0, "$NetBSD: amdtemp.c,v 1.6 2008/12/04 18:54:24 cegger Exp $ "); 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/device.h> 56 #include <sys/kmem.h> 57 #include <dev/sysmon/sysmonvar.h> 58 59 #include <machine/bus.h> 60 #include <machine/cpu.h> 61 #include <machine/specialreg.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 67 /* 68 * AMD K8: 69 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf 70 * Family10h: 71 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF 72 */ 73 74 /* AMD Proessors, Function 3 -- Miscellaneous Control 75 */ 76 77 /* Function 3 Registers */ 78 #define THERMTRIP_STAT_R 0xe4 79 #define NORTHBRIDGE_CAP_R 0xe8 80 #define CPUID_FAMILY_MODEL_R 0xfc 81 82 /* 83 * AMD NPT Family 0Fh Processors, Function 3 -- Miscellaneous Control 84 */ 85 86 /* Bits within Thermtrip Status Register */ 87 #define K8_THERM_SENSE_SEL (1 << 6) 88 #define K8_THERM_SENSE_CORE_SEL (1 << 2) 89 90 /* Flip core and sensor selection bits */ 91 #define K8_T_SEL_C0(v) (v |= K8_THERM_SENSE_CORE_SEL) 92 #define K8_T_SEL_C1(v) (v &= ~(K8_THERM_SENSE_CORE_SEL)) 93 #define K8_T_SEL_S0(v) (v &= ~(K8_THERM_SENSE_SEL)) 94 #define K8_T_SEL_S1(v) (v |= K8_THERM_SENSE_SEL) 95 96 97 98 /* 99 * AMD Family 10h Processorcs, Function 3 -- Miscellaneous Control 100 */ 101 102 /* Function 3 Registers */ 103 #define F10_TEMPERATURE_CTL_R 0xa4 104 105 /* Bits within Reported Temperature Control Register */ 106 #define F10_TEMP_CURTEMP (1 << 21) 107 108 /* 109 * Revision Guide for AMD NPT Family 0Fh Processors, 110 * Publication # 33610, Revision 3.30, February 2008 111 */ 112 #define K8_SOCKET_F 1 /* Server */ 113 #define K8_SOCKET_AM2 2 /* Desktop */ 114 #define K8_SOCKET_S1 3 /* Laptop */ 115 116 static const struct { 117 const char rev[5]; 118 const struct { 119 const pcireg_t cpuid; 120 const uint8_t socket; 121 } cpu[5]; 122 } amdtemp_core[] = { 123 { "BH-F", { { 0x00040FB0, K8_SOCKET_AM2 }, /* F2 */ 124 { 0x00040F80, K8_SOCKET_S1 }, /* F2 */ 125 { 0, 0 }, { 0, 0 }, { 0, 0 } } }, 126 { "DH-F", { { 0x00040FF0, K8_SOCKET_AM2 }, /* F2 */ 127 { 0x00040FC0, K8_SOCKET_S1 }, /* F2 */ 128 { 0x00050FF0, K8_SOCKET_AM2 }, /* F2, F3 */ 129 { 0, 0 }, { 0, 0 } } }, 130 { "JH-F", { { 0x00040F10, K8_SOCKET_F }, /* F2, F3 */ 131 { 0x00040F30, K8_SOCKET_AM2 }, /* F2, F3 */ 132 { 0x000C0F10, K8_SOCKET_F }, /* F3 */ 133 { 0, 0 }, { 0, 0 } } }, 134 { "BH-G", { { 0x00060FB0, K8_SOCKET_AM2 }, /* G1, G2 */ 135 { 0x00060F80, K8_SOCKET_S1 }, /* G1, G2 */ 136 { 0, 0 }, { 0, 0 }, { 0, 0 } } }, 137 { "DH-G", { { 0x00060FF0, K8_SOCKET_AM2 }, /* G1, G2 */ 138 { 0x00060FC0, K8_SOCKET_S1 }, /* G2 */ 139 { 0x00070FF0, K8_SOCKET_AM2 }, /* G1, G2 */ 140 { 0x00070FC0, K8_SOCKET_S1 }, /* G2 */ 141 { 0, 0 } } } 142 }; 143 144 145 struct amdtemp_softc { 146 pci_chipset_tag_t sc_pc; 147 pcitag_t sc_pcitag; 148 149 struct sysmon_envsys *sc_sme; 150 envsys_data_t *sc_sensor; 151 152 char sc_rev; 153 int8_t sc_numsensors; 154 uint32_t sc_family; 155 int32_t sc_adjustment; 156 }; 157 158 159 static int amdtemp_match(device_t, cfdata_t, void *); 160 static void amdtemp_attach(device_t, device_t, void *); 161 162 static void amdtemp_k8_init(struct amdtemp_softc *, pcireg_t); 163 static void amdtemp_k8_setup_sensors(struct amdtemp_softc *, int); 164 static void amdtemp_k8_refresh(struct sysmon_envsys *, envsys_data_t *); 165 166 static void amdtemp_family10_init(struct amdtemp_softc *); 167 static void amdtemp_family10_setup_sensors(struct amdtemp_softc *, int); 168 static void amdtemp_family10_refresh(struct sysmon_envsys *, envsys_data_t *); 169 170 CFATTACH_DECL_NEW(amdtemp, sizeof(struct amdtemp_softc), 171 amdtemp_match, amdtemp_attach, NULL, NULL); 172 173 static int 174 amdtemp_match(device_t parent, cfdata_t match, void *aux) 175 { 176 struct pci_attach_args *pa = aux; 177 pcireg_t cpu_signature; 178 uint32_t family; 179 180 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 181 return 0; 182 183 switch (PCI_PRODUCT(pa->pa_id)) { 184 case PCI_PRODUCT_AMD_AMD64_MISC: 185 case PCI_PRODUCT_AMD_AMD64_F10_MISC: 186 case PCI_PRODUCT_AMD_AMD64_F11_MISC: 187 break; 188 default: 189 return 0; 190 } 191 192 cpu_signature = pci_conf_read(pa->pa_pc, pa->pa_tag, 193 CPUID_FAMILY_MODEL_R); 194 195 /* This CPUID northbridge register has been introduced 196 * in Revision F */ 197 if (cpu_signature == 0x0) 198 return 0; 199 200 family = CPUID2FAMILY(cpu_signature); 201 if (family == 0xf) 202 family += CPUID2EXTFAMILY(cpu_signature); 203 204 /* Not yet supported CPUs */ 205 if (family >= 0x12) 206 return 0; 207 208 return 2; /* supercede pchb(4) */ 209 } 210 211 static void 212 amdtemp_attach(device_t parent, device_t self, void *aux) 213 { 214 struct amdtemp_softc *sc = device_private(self); 215 struct pci_attach_args *pa = aux; 216 pcireg_t cpu_signature; 217 size_t len; 218 int error; 219 uint8_t i; 220 221 aprint_naive("\n"); 222 aprint_normal("\n"); 223 224 aprint_normal_dev(self, "AMD CPU Temperature Sensors"); 225 226 cpu_signature = pci_conf_read(pa->pa_pc, pa->pa_tag, 227 CPUID_FAMILY_MODEL_R); 228 229 /* If we hit this, then match routine is wrong. */ 230 KASSERT(cpu_signature != 0x0); 231 232 sc->sc_family = CPUID2FAMILY(cpu_signature) 233 + CPUID2EXTFAMILY(cpu_signature); 234 KASSERT(sc->sc_family >= 0xf); 235 236 sc->sc_pc = pa->pa_pc; 237 sc->sc_pcitag = pa->pa_tag; 238 sc->sc_adjustment = 0; 239 240 switch (sc->sc_family) { 241 case 0xf: /* AMD K8 NPT */ 242 amdtemp_k8_init(sc, cpu_signature); 243 break; 244 245 case 0x10: /* AMD Barcelona/Phenom */ 246 case 0x11: /* AMD Griffin */ 247 amdtemp_family10_init(sc); 248 break; 249 250 default: 251 /* Not supported */ 252 return; 253 } 254 255 aprint_normal("\n"); 256 257 if (sc->sc_adjustment != 0) 258 aprint_debug_dev(self, "Workaround enabled\n"); 259 260 sc->sc_sme = sysmon_envsys_create(); 261 len = sizeof(envsys_data_t) * sc->sc_numsensors; 262 sc->sc_sensor = kmem_zalloc(len, KM_NOSLEEP); 263 if (!sc->sc_sensor) 264 goto bad2; 265 266 switch (sc->sc_family) { 267 case 0xf: 268 amdtemp_k8_setup_sensors(sc, device_unit(self)); 269 break; 270 case 0x10: 271 case 0x11: 272 amdtemp_family10_setup_sensors(sc, device_unit(self)); 273 break; 274 } 275 276 /* 277 * Set properties in sensors. 278 */ 279 for (i = 0; i < sc->sc_numsensors; i++) { 280 if (sysmon_envsys_sensor_attach(sc->sc_sme, 281 &sc->sc_sensor[i])) 282 goto bad; 283 } 284 285 /* 286 * Register the sysmon_envsys device. 287 */ 288 sc->sc_sme->sme_name = device_xname(self); 289 sc->sc_sme->sme_cookie = sc; 290 291 switch (sc->sc_family) { 292 case 0xf: 293 sc->sc_sme->sme_refresh = amdtemp_k8_refresh; 294 break; 295 case 0x10: 296 case 0x11: 297 sc->sc_sme->sme_refresh = amdtemp_family10_refresh; 298 break; 299 } 300 301 error = sysmon_envsys_register(sc->sc_sme); 302 if (error) { 303 aprint_error_dev(self, "unable to register with sysmon " 304 "(error=%d)\n", error); 305 goto bad; 306 } 307 308 if (!pmf_device_register(self, NULL, NULL)) 309 aprint_error_dev(self, "couldn't establish power handler\n"); 310 311 return; 312 313 bad: 314 kmem_free(sc->sc_sensor, len); 315 bad2: 316 sysmon_envsys_destroy(sc->sc_sme); 317 } 318 319 static void 320 amdtemp_k8_init(struct amdtemp_softc *sc, pcireg_t cpu_signature) 321 { 322 pcireg_t data; 323 uint32_t cmpcap; 324 uint8_t i, j; 325 326 aprint_normal(" (K8"); 327 328 for (i = 0; i < __arraycount(amdtemp_core) && sc->sc_rev == '\0'; i++) { 329 for (j = 0; amdtemp_core[i].cpu[j].cpuid != 0; j++) { 330 if ((cpu_signature & ~0xf) 331 != amdtemp_core[i].cpu[j].cpuid) 332 continue; 333 334 sc->sc_rev = amdtemp_core[i].rev[3]; 335 aprint_normal(": core rev %.4s%.1x", 336 amdtemp_core[i].rev, 337 CPUID2STEPPING(cpu_signature)); 338 339 switch (amdtemp_core[i].cpu[j].socket) { 340 case K8_SOCKET_AM2: 341 if (sc->sc_rev == 'G') 342 sc->sc_adjustment = 21000000; 343 aprint_normal(", socket AM2"); 344 break; 345 case K8_SOCKET_S1: 346 aprint_normal(", socket S1"); 347 break; 348 case K8_SOCKET_F: 349 aprint_normal(", socket F"); 350 break; 351 } 352 } 353 } 354 355 if (sc->sc_rev == '\0') { 356 /* CPUID Family Model Register was introduced in 357 * Revision F */ 358 sc->sc_rev = 'G'; /* newer than E, assume G */ 359 aprint_normal(": cpuid 0x%x", cpu_signature); 360 } 361 362 aprint_normal(")"); 363 364 data = pci_conf_read(sc->sc_pc, sc->sc_pcitag, NORTHBRIDGE_CAP_R); 365 cmpcap = (data >> 12) & 0x3; 366 367 sc->sc_numsensors = cmpcap ? 4 : 2; 368 } 369 370 371 static void 372 amdtemp_k8_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 373 { 374 uint8_t i; 375 376 /* There are two sensors per CPU core. So we use the 377 * device unit as socket counter to correctly enumerate 378 * the CPUs on multi-socket machines. 379 */ 380 dv_unit *= (sc->sc_numsensors / 2); 381 for (i = 0; i < sc->sc_numsensors; i++) { 382 sc->sc_sensor[i].units = ENVSYS_STEMP; 383 sc->sc_sensor[i].state = ENVSYS_SVALID; 384 385 snprintf(sc->sc_sensor[i].desc, sizeof(sc->sc_sensor[i].desc), 386 "CPU%u Sensor%u", dv_unit + (i / 2), i % 2); 387 } 388 } 389 390 391 static void 392 amdtemp_k8_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 393 { 394 struct amdtemp_softc *sc = sme->sme_cookie; 395 pcireg_t status, match, tmp; 396 uint32_t value; 397 398 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 399 400 switch(edata->sensor) { /* sensor number */ 401 case 0: /* Core 0 Sensor 0 */ 402 K8_T_SEL_C0(status); 403 K8_T_SEL_S0(status); 404 break; 405 case 1: /* Core 0 Sensor 1 */ 406 K8_T_SEL_C0(status); 407 K8_T_SEL_S1(status); 408 break; 409 case 2: /* Core 1 Sensor 0 */ 410 K8_T_SEL_C1(status); 411 K8_T_SEL_S0(status); 412 break; 413 case 3: /* Core 1 Sensor 1 */ 414 K8_T_SEL_C1(status); 415 K8_T_SEL_S1(status); 416 break; 417 } 418 419 match = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 420 pci_conf_write(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R, status); 421 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 422 tmp = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 423 424 value = 0x3ff & (status >> 14); 425 if (sc->sc_rev != 'G') 426 value &= ~0x3; 427 428 edata->state = ENVSYS_SINVALID; 429 if ((tmp == match) && ((value & ~0x3) != 0)) { 430 edata->state = ENVSYS_SVALID; 431 edata->value_cur = (value * 250000 - 49000000) + 273150000 432 + sc->sc_adjustment; 433 } 434 } 435 436 437 static void 438 amdtemp_family10_init(struct amdtemp_softc *sc) 439 { 440 aprint_normal(" (Family10h / Family11h)"); 441 442 sc->sc_numsensors = 1; 443 } 444 445 static void 446 amdtemp_family10_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 447 { 448 /* sanity check for future enhancements */ 449 KASSERT(sc->sc_numsensors == 1); 450 451 /* There's one sensor per memory controller (= socket) 452 * so we use the device unit as socket counter 453 * to correctly enumerate the CPUs 454 */ 455 sc->sc_sensor[0].units = ENVSYS_STEMP; 456 sc->sc_sensor[0].state = ENVSYS_SVALID; 457 458 snprintf(sc->sc_sensor[0].desc, sizeof(sc->sc_sensor[0].desc), 459 "CPU%u Sensor0", dv_unit); 460 } 461 462 463 static void 464 amdtemp_family10_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 465 { 466 struct amdtemp_softc *sc = sme->sme_cookie; 467 pcireg_t status; 468 uint32_t value; 469 470 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, F10_TEMPERATURE_CTL_R); 471 472 value = (status >> 21); 473 474 edata->state = ENVSYS_SVALID; 475 /* envsys(4) wants uK... convert from Celsius. */ 476 edata->value_cur = (value * 125000) + 273150000; 477 } 478
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