amdtemp.c revision 1.6.4.2
1 /* $NetBSD: amdtemp.c,v 1.6.4.2 2009/07/23 23:31:37 jym Exp $ */ 2 /* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */ 3 4 /* 5 * Copyright (c) 2008 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Christoph Egger. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 2008 Constantine A. Murenin <cnst+openbsd (at) bugmail.mojo.ru> 35 * 36 * Permission to use, copy, modify, and distribute this software for any 37 * purpose with or without fee is hereby granted, provided that the above 38 * copyright notice and this permission notice appear in all copies. 39 * 40 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 41 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 42 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 43 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 44 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 45 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 46 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 47 */ 48 49 50 #include <sys/cdefs.h> 51 __KERNEL_RCSID(0, "$NetBSD: amdtemp.c,v 1.6.4.2 2009/07/23 23:31:37 jym Exp $ "); 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/device.h> 56 #include <sys/kmem.h> 57 #include <dev/sysmon/sysmonvar.h> 58 59 #include <sys/bus.h> 60 #include <sys/cpu.h> 61 #include <machine/specialreg.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 67 /* 68 * AMD K8: 69 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf 70 * AMD K8 Errata: #141 71 * http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf 72 * 73 * Family10h: 74 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF 75 * 76 * Family11h: 77 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/41256.pdf 78 */ 79 80 /* AMD Proessors, Function 3 -- Miscellaneous Control 81 */ 82 83 /* Function 3 Registers */ 84 #define THERMTRIP_STAT_R 0xe4 85 #define NORTHBRIDGE_CAP_R 0xe8 86 #define CPUID_FAMILY_MODEL_R 0xfc 87 88 /* 89 * AMD NPT Family 0Fh Processors, Function 3 -- Miscellaneous Control 90 */ 91 92 /* Bits within Thermtrip Status Register */ 93 #define K8_THERM_SENSE_SEL (1 << 6) 94 #define K8_THERM_SENSE_CORE_SEL (1 << 2) 95 96 /* Flip core and sensor selection bits */ 97 #define K8_T_SEL_C0(v) (v |= K8_THERM_SENSE_CORE_SEL) 98 #define K8_T_SEL_C1(v) (v &= ~(K8_THERM_SENSE_CORE_SEL)) 99 #define K8_T_SEL_S0(v) (v &= ~(K8_THERM_SENSE_SEL)) 100 #define K8_T_SEL_S1(v) (v |= K8_THERM_SENSE_SEL) 101 102 103 104 /* 105 * AMD Family 10h Processorcs, Function 3 -- Miscellaneous Control 106 */ 107 108 /* Function 3 Registers */ 109 #define F10_TEMPERATURE_CTL_R 0xa4 110 111 /* Bits within Reported Temperature Control Register */ 112 #define F10_TEMP_CURTEMP (1 << 21) 113 114 /* 115 * Revision Guide for AMD NPT Family 0Fh Processors, 116 * Publication # 33610, Revision 3.30, February 2008 117 */ 118 #define K8_SOCKET_F 1 /* Server */ 119 #define K8_SOCKET_AM2 2 /* Desktop */ 120 #define K8_SOCKET_S1 3 /* Laptop */ 121 122 static const struct { 123 const char rev[5]; 124 const struct { 125 const pcireg_t cpuid; 126 const uint8_t socket; 127 } cpu[5]; 128 } amdtemp_core[] = { 129 { "BH-F", { { 0x00040FB0, K8_SOCKET_AM2 }, /* F2 */ 130 { 0x00040F80, K8_SOCKET_S1 }, /* F2 */ 131 { 0, 0 }, { 0, 0 }, { 0, 0 } } }, 132 { "DH-F", { { 0x00040FF0, K8_SOCKET_AM2 }, /* F2 */ 133 { 0x00040FC0, K8_SOCKET_S1 }, /* F2 */ 134 { 0x00050FF0, K8_SOCKET_AM2 }, /* F2, F3 */ 135 { 0, 0 }, { 0, 0 } } }, 136 { "JH-F", { { 0x00040F10, K8_SOCKET_F }, /* F2, F3 */ 137 { 0x00040F30, K8_SOCKET_AM2 }, /* F2, F3 */ 138 { 0x000C0F10, K8_SOCKET_F }, /* F3 */ 139 { 0, 0 }, { 0, 0 } } }, 140 { "BH-G", { { 0x00060FB0, K8_SOCKET_AM2 }, /* G1, G2 */ 141 { 0x00060F80, K8_SOCKET_S1 }, /* G1, G2 */ 142 { 0, 0 }, { 0, 0 }, { 0, 0 } } }, 143 { "DH-G", { { 0x00060FF0, K8_SOCKET_AM2 }, /* G1, G2 */ 144 { 0x00060FC0, K8_SOCKET_S1 }, /* G2 */ 145 { 0x00070FF0, K8_SOCKET_AM2 }, /* G1, G2 */ 146 { 0x00070FC0, K8_SOCKET_S1 }, /* G2 */ 147 { 0, 0 } } } 148 }; 149 150 151 struct amdtemp_softc { 152 pci_chipset_tag_t sc_pc; 153 pcitag_t sc_pcitag; 154 155 struct sysmon_envsys *sc_sme; 156 envsys_data_t *sc_sensor; 157 158 char sc_rev; 159 int8_t sc_numsensors; 160 uint32_t sc_family; 161 int32_t sc_adjustment; 162 }; 163 164 165 static int amdtemp_match(device_t, cfdata_t, void *); 166 static void amdtemp_attach(device_t, device_t, void *); 167 168 static void amdtemp_k8_init(struct amdtemp_softc *, pcireg_t); 169 static void amdtemp_k8_setup_sensors(struct amdtemp_softc *, int); 170 static void amdtemp_k8_refresh(struct sysmon_envsys *, envsys_data_t *); 171 172 static void amdtemp_family10_init(struct amdtemp_softc *); 173 static void amdtemp_family10_setup_sensors(struct amdtemp_softc *, int); 174 static void amdtemp_family10_refresh(struct sysmon_envsys *, envsys_data_t *); 175 176 CFATTACH_DECL_NEW(amdtemp, sizeof(struct amdtemp_softc), 177 amdtemp_match, amdtemp_attach, NULL, NULL); 178 179 static int 180 amdtemp_match(device_t parent, cfdata_t match, void *aux) 181 { 182 struct pci_attach_args *pa = aux; 183 pcireg_t cpu_signature; 184 uint32_t family; 185 186 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 187 return 0; 188 189 switch (PCI_PRODUCT(pa->pa_id)) { 190 case PCI_PRODUCT_AMD_AMD64_MISC: 191 case PCI_PRODUCT_AMD_AMD64_F10_MISC: 192 case PCI_PRODUCT_AMD_AMD64_F11_MISC: 193 break; 194 default: 195 return 0; 196 } 197 198 cpu_signature = pci_conf_read(pa->pa_pc, pa->pa_tag, 199 CPUID_FAMILY_MODEL_R); 200 201 /* This CPUID northbridge register has been introduced 202 * in Revision F */ 203 if (cpu_signature == 0x0) 204 return 0; 205 206 family = CPUID2FAMILY(cpu_signature); 207 if (family == 0xf) 208 family += CPUID2EXTFAMILY(cpu_signature); 209 210 /* Not yet supported CPUs */ 211 if (family >= 0x12) 212 return 0; 213 214 return 2; /* supercede pchb(4) */ 215 } 216 217 static void 218 amdtemp_attach(device_t parent, device_t self, void *aux) 219 { 220 struct amdtemp_softc *sc = device_private(self); 221 struct pci_attach_args *pa = aux; 222 pcireg_t cpu_signature; 223 size_t len; 224 int error; 225 uint8_t i; 226 227 aprint_naive("\n"); 228 aprint_normal(": AMD CPU Temperature Sensors"); 229 230 cpu_signature = pci_conf_read(pa->pa_pc, pa->pa_tag, 231 CPUID_FAMILY_MODEL_R); 232 233 /* If we hit this, then match routine is wrong. */ 234 KASSERT(cpu_signature != 0x0); 235 236 sc->sc_family = CPUID2FAMILY(cpu_signature) 237 + CPUID2EXTFAMILY(cpu_signature); 238 KASSERT(sc->sc_family >= 0xf); 239 240 sc->sc_pc = pa->pa_pc; 241 sc->sc_pcitag = pa->pa_tag; 242 sc->sc_adjustment = 0; 243 244 switch (sc->sc_family) { 245 case 0xf: /* AMD K8 NPT */ 246 amdtemp_k8_init(sc, cpu_signature); 247 break; 248 249 case 0x10: /* AMD Barcelona/Phenom */ 250 case 0x11: /* AMD Griffin */ 251 amdtemp_family10_init(sc); 252 break; 253 254 default: 255 aprint_normal(", family 0x%x not supported\n", 256 sc->sc_family); 257 return; 258 } 259 260 aprint_normal("\n"); 261 262 if (sc->sc_adjustment != 0) 263 aprint_debug_dev(self, "Workaround enabled\n"); 264 265 sc->sc_sme = sysmon_envsys_create(); 266 len = sizeof(envsys_data_t) * sc->sc_numsensors; 267 sc->sc_sensor = kmem_zalloc(len, KM_NOSLEEP); 268 if (!sc->sc_sensor) 269 goto bad2; 270 271 switch (sc->sc_family) { 272 case 0xf: 273 amdtemp_k8_setup_sensors(sc, device_unit(self)); 274 break; 275 case 0x10: 276 case 0x11: 277 amdtemp_family10_setup_sensors(sc, device_unit(self)); 278 break; 279 } 280 281 /* 282 * Set properties in sensors. 283 */ 284 for (i = 0; i < sc->sc_numsensors; i++) { 285 if (sysmon_envsys_sensor_attach(sc->sc_sme, 286 &sc->sc_sensor[i])) 287 goto bad; 288 } 289 290 /* 291 * Register the sysmon_envsys device. 292 */ 293 sc->sc_sme->sme_name = device_xname(self); 294 sc->sc_sme->sme_cookie = sc; 295 296 switch (sc->sc_family) { 297 case 0xf: 298 sc->sc_sme->sme_refresh = amdtemp_k8_refresh; 299 break; 300 case 0x10: 301 case 0x11: 302 sc->sc_sme->sme_refresh = amdtemp_family10_refresh; 303 break; 304 } 305 306 error = sysmon_envsys_register(sc->sc_sme); 307 if (error) { 308 aprint_error_dev(self, "unable to register with sysmon " 309 "(error=%d)\n", error); 310 goto bad; 311 } 312 313 if (!pmf_device_register(self, NULL, NULL)) 314 aprint_error_dev(self, "couldn't establish power handler\n"); 315 316 return; 317 318 bad: 319 kmem_free(sc->sc_sensor, len); 320 bad2: 321 sysmon_envsys_destroy(sc->sc_sme); 322 } 323 324 static void 325 amdtemp_k8_init(struct amdtemp_softc *sc, pcireg_t cpu_signature) 326 { 327 pcireg_t data; 328 uint32_t cmpcap; 329 uint8_t i, j; 330 331 aprint_normal(" (K8"); 332 333 for (i = 0; i < __arraycount(amdtemp_core) && sc->sc_rev == '\0'; i++) { 334 for (j = 0; amdtemp_core[i].cpu[j].cpuid != 0; j++) { 335 if ((cpu_signature & ~0xf) 336 != amdtemp_core[i].cpu[j].cpuid) 337 continue; 338 339 sc->sc_rev = amdtemp_core[i].rev[3]; 340 aprint_normal(": core rev %.4s%.1x", 341 amdtemp_core[i].rev, 342 CPUID2STEPPING(cpu_signature)); 343 344 switch (amdtemp_core[i].cpu[j].socket) { 345 case K8_SOCKET_AM2: 346 if (sc->sc_rev == 'G') 347 sc->sc_adjustment = 21000000; 348 aprint_normal(", socket AM2"); 349 break; 350 case K8_SOCKET_S1: 351 aprint_normal(", socket S1"); 352 break; 353 case K8_SOCKET_F: 354 aprint_normal(", socket F"); 355 break; 356 } 357 } 358 } 359 360 if (sc->sc_rev == '\0') { 361 /* CPUID Family Model Register was introduced in 362 * Revision F */ 363 sc->sc_rev = 'G'; /* newer than E, assume G */ 364 aprint_normal(": cpuid 0x%x", cpu_signature); 365 } 366 367 aprint_normal(")"); 368 369 data = pci_conf_read(sc->sc_pc, sc->sc_pcitag, NORTHBRIDGE_CAP_R); 370 cmpcap = (data >> 12) & 0x3; 371 372 sc->sc_numsensors = cmpcap ? 4 : 2; 373 } 374 375 376 static void 377 amdtemp_k8_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 378 { 379 uint8_t i; 380 381 /* There are two sensors per CPU core. So we use the 382 * device unit as socket counter to correctly enumerate 383 * the CPUs on multi-socket machines. 384 */ 385 dv_unit *= (sc->sc_numsensors / 2); 386 for (i = 0; i < sc->sc_numsensors; i++) { 387 sc->sc_sensor[i].units = ENVSYS_STEMP; 388 sc->sc_sensor[i].state = ENVSYS_SVALID; 389 390 snprintf(sc->sc_sensor[i].desc, sizeof(sc->sc_sensor[i].desc), 391 "CPU%u Sensor%u", dv_unit + (i / 2), i % 2); 392 } 393 } 394 395 396 static void 397 amdtemp_k8_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 398 { 399 struct amdtemp_softc *sc = sme->sme_cookie; 400 pcireg_t status, match, tmp; 401 uint32_t value; 402 403 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 404 405 switch(edata->sensor) { /* sensor number */ 406 case 0: /* Core 0 Sensor 0 */ 407 K8_T_SEL_C0(status); 408 K8_T_SEL_S0(status); 409 break; 410 case 1: /* Core 0 Sensor 1 */ 411 K8_T_SEL_C0(status); 412 K8_T_SEL_S1(status); 413 break; 414 case 2: /* Core 1 Sensor 0 */ 415 K8_T_SEL_C1(status); 416 K8_T_SEL_S0(status); 417 break; 418 case 3: /* Core 1 Sensor 1 */ 419 K8_T_SEL_C1(status); 420 K8_T_SEL_S1(status); 421 break; 422 } 423 424 match = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 425 pci_conf_write(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R, status); 426 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 427 tmp = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 428 429 value = 0x3ff & (status >> 14); 430 if (sc->sc_rev != 'G') 431 value &= ~0x3; 432 433 edata->state = ENVSYS_SINVALID; 434 if ((tmp == match) && ((value & ~0x3) != 0)) { 435 edata->state = ENVSYS_SVALID; 436 edata->value_cur = (value * 250000 - 49000000) + 273150000 437 + sc->sc_adjustment; 438 } 439 } 440 441 442 static void 443 amdtemp_family10_init(struct amdtemp_softc *sc) 444 { 445 aprint_normal(" (Family10h / Family11h)"); 446 447 sc->sc_numsensors = 1; 448 } 449 450 static void 451 amdtemp_family10_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 452 { 453 /* sanity check for future enhancements */ 454 KASSERT(sc->sc_numsensors == 1); 455 456 /* There's one sensor per memory controller (= socket) 457 * so we use the device unit as socket counter 458 * to correctly enumerate the CPUs 459 */ 460 sc->sc_sensor[0].units = ENVSYS_STEMP; 461 sc->sc_sensor[0].state = ENVSYS_SVALID; 462 463 snprintf(sc->sc_sensor[0].desc, sizeof(sc->sc_sensor[0].desc), 464 "CPU%u Sensor0", dv_unit); 465 } 466 467 468 static void 469 amdtemp_family10_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 470 { 471 struct amdtemp_softc *sc = sme->sme_cookie; 472 pcireg_t status; 473 uint32_t value; 474 475 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, F10_TEMPERATURE_CTL_R); 476 477 value = (status >> 21); 478 479 edata->state = ENVSYS_SVALID; 480 /* envsys(4) wants uK... convert from Celsius. */ 481 edata->value_cur = (value * 125000) + 273150000; 482 } 483
Indexes created Thu Oct 02 14:10:14 GMT 2025