amdtemp.c revision 1.9.10.1
1 /* $NetBSD: amdtemp.c,v 1.9.10.1 2011/06/23 14:19:48 cherry Exp $ */ 2 /* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */ 3 4 /* 5 * Copyright (c) 2008 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Christoph Egger. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 2008 Constantine A. Murenin <cnst+openbsd (at) bugmail.mojo.ru> 35 * 36 * Permission to use, copy, modify, and distribute this software for any 37 * purpose with or without fee is hereby granted, provided that the above 38 * copyright notice and this permission notice appear in all copies. 39 * 40 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 41 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 42 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 43 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 44 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 45 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 46 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 47 */ 48 49 50 #include <sys/cdefs.h> 51 __KERNEL_RCSID(0, "$NetBSD: amdtemp.c,v 1.9.10.1 2011/06/23 14:19:48 cherry Exp $ "); 52 53 #include <sys/param.h> 54 #include <sys/bus.h> 55 #include <sys/cpu.h> 56 #include <sys/systm.h> 57 #include <sys/device.h> 58 #include <sys/kmem.h> 59 #include <sys/module.h> 60 61 #include <machine/specialreg.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/sysmon/sysmonvar.h> 68 69 /* 70 * AMD K8: 71 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf 72 * AMD K8 Errata: #141 73 * http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf 74 * 75 * Family10h: 76 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF 77 * Family10h Errata: #319 78 * http://support.amd.com/de/Processor_TechDocs/41322.pdf 79 * 80 * Family11h: 81 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/41256.pdf 82 */ 83 84 /* AMD Proessors, Function 3 -- Miscellaneous Control 85 */ 86 87 /* Function 3 Registers */ 88 #define THERMTRIP_STAT_R 0xe4 89 #define NORTHBRIDGE_CAP_R 0xe8 90 #define CPUID_FAMILY_MODEL_R 0xfc 91 92 /* 93 * AMD NPT Family 0Fh Processors, Function 3 -- Miscellaneous Control 94 */ 95 96 /* Bits within Thermtrip Status Register */ 97 #define K8_THERM_SENSE_SEL (1 << 6) 98 #define K8_THERM_SENSE_CORE_SEL (1 << 2) 99 100 /* Flip core and sensor selection bits */ 101 #define K8_T_SEL_C0(v) (v |= K8_THERM_SENSE_CORE_SEL) 102 #define K8_T_SEL_C1(v) (v &= ~(K8_THERM_SENSE_CORE_SEL)) 103 #define K8_T_SEL_S0(v) (v &= ~(K8_THERM_SENSE_SEL)) 104 #define K8_T_SEL_S1(v) (v |= K8_THERM_SENSE_SEL) 105 106 107 108 /* 109 * AMD Family 10h Processorcs, Function 3 -- Miscellaneous Control 110 */ 111 112 /* Function 3 Registers */ 113 #define F10_TEMPERATURE_CTL_R 0xa4 114 115 /* Bits within Reported Temperature Control Register */ 116 #define F10_TEMP_CURTEMP (1 << 21) 117 118 /* 119 * Revision Guide for AMD NPT Family 0Fh Processors, 120 * Publication # 33610, Revision 3.30, February 2008 121 */ 122 #define K8_SOCKET_F 1 /* Server */ 123 #define K8_SOCKET_AM2 2 /* Desktop */ 124 #define K8_SOCKET_S1 3 /* Laptop */ 125 126 static const struct { 127 const char rev[5]; 128 const struct { 129 const pcireg_t cpuid; 130 const uint8_t socket; 131 } cpu[5]; 132 } amdtemp_core[] = { 133 { "BH-F", { { 0x00040FB0, K8_SOCKET_AM2 }, /* F2 */ 134 { 0x00040F80, K8_SOCKET_S1 }, /* F2 */ 135 { 0, 0 }, { 0, 0 }, { 0, 0 } } }, 136 { "DH-F", { { 0x00040FF0, K8_SOCKET_AM2 }, /* F2 */ 137 { 0x00040FC0, K8_SOCKET_S1 }, /* F2 */ 138 { 0x00050FF0, K8_SOCKET_AM2 }, /* F2, F3 */ 139 { 0, 0 }, { 0, 0 } } }, 140 { "JH-F", { { 0x00040F10, K8_SOCKET_F }, /* F2, F3 */ 141 { 0x00040F30, K8_SOCKET_AM2 }, /* F2, F3 */ 142 { 0x000C0F10, K8_SOCKET_F }, /* F3 */ 143 { 0, 0 }, { 0, 0 } } }, 144 { "BH-G", { { 0x00060FB0, K8_SOCKET_AM2 }, /* G1, G2 */ 145 { 0x00060F80, K8_SOCKET_S1 }, /* G1, G2 */ 146 { 0, 0 }, { 0, 0 }, { 0, 0 } } }, 147 { "DH-G", { { 0x00060FF0, K8_SOCKET_AM2 }, /* G1, G2 */ 148 { 0x00060FC0, K8_SOCKET_S1 }, /* G2 */ 149 { 0x00070FF0, K8_SOCKET_AM2 }, /* G1, G2 */ 150 { 0x00070FC0, K8_SOCKET_S1 }, /* G2 */ 151 { 0, 0 } } } 152 }; 153 154 155 struct amdtemp_softc { 156 pci_chipset_tag_t sc_pc; 157 pcitag_t sc_pcitag; 158 159 struct sysmon_envsys *sc_sme; 160 envsys_data_t *sc_sensor; 161 size_t sc_sensor_len; 162 163 char sc_rev; 164 int8_t sc_numsensors; 165 uint32_t sc_family; 166 int32_t sc_adjustment; 167 }; 168 169 170 static int amdtemp_match(device_t, cfdata_t, void *); 171 static void amdtemp_attach(device_t, device_t, void *); 172 static int amdtemp_detach(device_t, int); 173 174 static void amdtemp_k8_init(struct amdtemp_softc *, pcireg_t); 175 static void amdtemp_k8_setup_sensors(struct amdtemp_softc *, int); 176 static void amdtemp_k8_refresh(struct sysmon_envsys *, envsys_data_t *); 177 178 static void amdtemp_family10_init(struct amdtemp_softc *); 179 static void amdtemp_family10_setup_sensors(struct amdtemp_softc *, int); 180 static void amdtemp_family10_refresh(struct sysmon_envsys *, envsys_data_t *); 181 182 CFATTACH_DECL_NEW(amdtemp, sizeof(struct amdtemp_softc), 183 amdtemp_match, amdtemp_attach, amdtemp_detach, NULL); 184 185 static int 186 amdtemp_match(device_t parent, cfdata_t match, void *aux) 187 { 188 struct pci_attach_args *pa = aux; 189 pcireg_t cpu_signature; 190 uint32_t family; 191 192 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 193 return 0; 194 195 switch (PCI_PRODUCT(pa->pa_id)) { 196 case PCI_PRODUCT_AMD_AMD64_MISC: 197 case PCI_PRODUCT_AMD_AMD64_F10_MISC: 198 case PCI_PRODUCT_AMD_AMD64_F11_MISC: 199 break; 200 default: 201 return 0; 202 } 203 204 cpu_signature = pci_conf_read(pa->pa_pc, 205 pa->pa_tag, CPUID_FAMILY_MODEL_R); 206 207 /* This CPUID northbridge register has been introduced 208 * in Revision F */ 209 if (cpu_signature == 0x0) 210 return 0; 211 212 family = CPUID2FAMILY(cpu_signature); 213 if (family == 0xf) 214 family += CPUID2EXTFAMILY(cpu_signature); 215 216 /* Errata #319: This has been fixed in Revision C2. */ 217 if (family == 0x10) { 218 if (CPUID2MODEL(cpu_signature) < 4) 219 return 0; 220 if (CPUID2MODEL(cpu_signature) == 4 221 && CPUID2STEPPING(cpu_signature) < 2) 222 return 0; 223 } 224 225 226 /* Not yet supported CPUs */ 227 if (family >= 0x12) 228 return 0; 229 230 return 2; /* supercede pchb(4) */ 231 } 232 233 static void 234 amdtemp_attach(device_t parent, device_t self, void *aux) 235 { 236 struct amdtemp_softc *sc = device_private(self); 237 struct pci_attach_args *pa = aux; 238 pcireg_t cpu_signature; 239 int error; 240 uint8_t i; 241 242 aprint_naive("\n"); 243 aprint_normal(": AMD CPU Temperature Sensors"); 244 245 cpu_signature = pci_conf_read(pa->pa_pc, 246 pa->pa_tag, CPUID_FAMILY_MODEL_R); 247 248 /* If we hit this, then match routine is wrong. */ 249 KASSERT(cpu_signature != 0x0); 250 251 sc->sc_family = CPUID2FAMILY(cpu_signature); 252 sc->sc_family += CPUID2EXTFAMILY(cpu_signature); 253 254 KASSERT(sc->sc_family >= 0xf); 255 256 sc->sc_sme = NULL; 257 sc->sc_sensor = NULL; 258 259 sc->sc_pc = pa->pa_pc; 260 sc->sc_pcitag = pa->pa_tag; 261 sc->sc_adjustment = 0; 262 263 switch (sc->sc_family) { 264 case 0xf: /* AMD K8 NPT */ 265 amdtemp_k8_init(sc, cpu_signature); 266 break; 267 268 case 0x10: /* AMD Barcelona/Phenom */ 269 case 0x11: /* AMD Griffin */ 270 amdtemp_family10_init(sc); 271 break; 272 273 default: 274 aprint_normal(", family 0x%x not supported\n", 275 sc->sc_family); 276 return; 277 } 278 279 aprint_normal("\n"); 280 281 if (sc->sc_adjustment != 0) 282 aprint_debug_dev(self, "Workaround enabled\n"); 283 284 sc->sc_sme = sysmon_envsys_create(); 285 sc->sc_sensor_len = sizeof(envsys_data_t) * sc->sc_numsensors; 286 sc->sc_sensor = kmem_zalloc(sc->sc_sensor_len, KM_SLEEP); 287 288 if (sc->sc_sensor == NULL) 289 goto bad; 290 291 switch (sc->sc_family) { 292 case 0xf: 293 amdtemp_k8_setup_sensors(sc, device_unit(self)); 294 break; 295 case 0x10: 296 case 0x11: 297 amdtemp_family10_setup_sensors(sc, device_unit(self)); 298 break; 299 } 300 301 /* 302 * Set properties in sensors. 303 */ 304 for (i = 0; i < sc->sc_numsensors; i++) { 305 if (sysmon_envsys_sensor_attach(sc->sc_sme, 306 &sc->sc_sensor[i])) 307 goto bad; 308 } 309 310 /* 311 * Register the sysmon_envsys device. 312 */ 313 sc->sc_sme->sme_name = device_xname(self); 314 sc->sc_sme->sme_cookie = sc; 315 316 switch (sc->sc_family) { 317 case 0xf: 318 sc->sc_sme->sme_refresh = amdtemp_k8_refresh; 319 break; 320 case 0x10: 321 case 0x11: 322 sc->sc_sme->sme_refresh = amdtemp_family10_refresh; 323 break; 324 } 325 326 error = sysmon_envsys_register(sc->sc_sme); 327 if (error) { 328 aprint_error_dev(self, "unable to register with sysmon " 329 "(error=%d)\n", error); 330 goto bad; 331 } 332 333 (void)pmf_device_register(self, NULL, NULL); 334 335 return; 336 337 bad: 338 if (sc->sc_sme != NULL) { 339 sysmon_envsys_destroy(sc->sc_sme); 340 sc->sc_sme = NULL; 341 } 342 343 if (sc->sc_sensor != NULL) { 344 kmem_free(sc->sc_sensor, sc->sc_sensor_len); 345 sc->sc_sensor = NULL; 346 } 347 } 348 349 static int 350 amdtemp_detach(device_t self, int flags) 351 { 352 struct amdtemp_softc *sc = device_private(self); 353 354 if (sc->sc_sme != NULL) 355 sysmon_envsys_unregister(sc->sc_sme); 356 357 if (sc->sc_sensor != NULL) 358 kmem_free(sc->sc_sensor, sc->sc_sensor_len); 359 360 return 0; 361 } 362 363 static void 364 amdtemp_k8_init(struct amdtemp_softc *sc, pcireg_t cpu_signature) 365 { 366 pcireg_t data; 367 uint32_t cmpcap; 368 uint8_t i, j; 369 370 aprint_normal(" (K8"); 371 372 for (i = 0; i < __arraycount(amdtemp_core) && sc->sc_rev == '\0'; i++) { 373 for (j = 0; amdtemp_core[i].cpu[j].cpuid != 0; j++) { 374 if ((cpu_signature & ~0xf) 375 != amdtemp_core[i].cpu[j].cpuid) 376 continue; 377 378 sc->sc_rev = amdtemp_core[i].rev[3]; 379 aprint_normal(": core rev %.4s%.1x", 380 amdtemp_core[i].rev, 381 CPUID2STEPPING(cpu_signature)); 382 383 switch (amdtemp_core[i].cpu[j].socket) { 384 case K8_SOCKET_AM2: 385 if (sc->sc_rev == 'G') 386 sc->sc_adjustment = 21000000; 387 aprint_normal(", socket AM2"); 388 break; 389 case K8_SOCKET_S1: 390 aprint_normal(", socket S1"); 391 break; 392 case K8_SOCKET_F: 393 aprint_normal(", socket F"); 394 break; 395 } 396 } 397 } 398 399 if (sc->sc_rev == '\0') { 400 /* CPUID Family Model Register was introduced in 401 * Revision F */ 402 sc->sc_rev = 'G'; /* newer than E, assume G */ 403 aprint_normal(": cpuid 0x%x", cpu_signature); 404 } 405 406 aprint_normal(")"); 407 408 data = pci_conf_read(sc->sc_pc, sc->sc_pcitag, NORTHBRIDGE_CAP_R); 409 cmpcap = (data >> 12) & 0x3; 410 411 sc->sc_numsensors = cmpcap ? 4 : 2; 412 } 413 414 415 static void 416 amdtemp_k8_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 417 { 418 uint8_t i; 419 420 /* There are two sensors per CPU core. So we use the 421 * device unit as socket counter to correctly enumerate 422 * the CPUs on multi-socket machines. 423 */ 424 dv_unit *= (sc->sc_numsensors / 2); 425 for (i = 0; i < sc->sc_numsensors; i++) { 426 sc->sc_sensor[i].units = ENVSYS_STEMP; 427 sc->sc_sensor[i].state = ENVSYS_SVALID; 428 429 snprintf(sc->sc_sensor[i].desc, sizeof(sc->sc_sensor[i].desc), 430 "CPU%u Sensor%u", dv_unit + (i / 2), i % 2); 431 } 432 } 433 434 435 static void 436 amdtemp_k8_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 437 { 438 struct amdtemp_softc *sc = sme->sme_cookie; 439 pcireg_t status, match, tmp; 440 uint32_t value; 441 442 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 443 444 switch(edata->sensor) { /* sensor number */ 445 case 0: /* Core 0 Sensor 0 */ 446 K8_T_SEL_C0(status); 447 K8_T_SEL_S0(status); 448 break; 449 case 1: /* Core 0 Sensor 1 */ 450 K8_T_SEL_C0(status); 451 K8_T_SEL_S1(status); 452 break; 453 case 2: /* Core 1 Sensor 0 */ 454 K8_T_SEL_C1(status); 455 K8_T_SEL_S0(status); 456 break; 457 case 3: /* Core 1 Sensor 1 */ 458 K8_T_SEL_C1(status); 459 K8_T_SEL_S1(status); 460 break; 461 } 462 463 match = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 464 pci_conf_write(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R, status); 465 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 466 tmp = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 467 468 value = 0x3ff & (status >> 14); 469 if (sc->sc_rev != 'G') 470 value &= ~0x3; 471 472 edata->state = ENVSYS_SINVALID; 473 if ((tmp == match) && ((value & ~0x3) != 0)) { 474 edata->state = ENVSYS_SVALID; 475 edata->value_cur = (value * 250000 - 49000000) + 273150000 476 + sc->sc_adjustment; 477 } 478 } 479 480 481 static void 482 amdtemp_family10_init(struct amdtemp_softc *sc) 483 { 484 aprint_normal(" (Family10h / Family11h)"); 485 486 sc->sc_numsensors = 1; 487 } 488 489 static void 490 amdtemp_family10_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 491 { 492 /* sanity check for future enhancements */ 493 KASSERT(sc->sc_numsensors == 1); 494 495 /* There's one sensor per memory controller (= socket) 496 * so we use the device unit as socket counter 497 * to correctly enumerate the CPUs 498 */ 499 sc->sc_sensor[0].units = ENVSYS_STEMP; 500 sc->sc_sensor[0].state = ENVSYS_SVALID; 501 502 snprintf(sc->sc_sensor[0].desc, sizeof(sc->sc_sensor[0].desc), 503 "CPU%u Sensor0", dv_unit); 504 } 505 506 507 static void 508 amdtemp_family10_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 509 { 510 struct amdtemp_softc *sc = sme->sme_cookie; 511 pcireg_t status; 512 uint32_t value; 513 514 status = pci_conf_read(sc->sc_pc, 515 sc->sc_pcitag, F10_TEMPERATURE_CTL_R); 516 517 value = (status >> 21); 518 519 edata->state = ENVSYS_SVALID; 520 edata->value_cur = (value * 125000) + 273150000; /* From C to uK. */ 521 } 522 523 MODULE(MODULE_CLASS_DRIVER, amdtemp, NULL); 524 525 #ifdef _MODULE 526 #include "ioconf.c" 527 #endif 528 529 static int 530 amdtemp_modcmd(modcmd_t cmd, void *aux) 531 { 532 int error = 0; 533 534 switch (cmd) { 535 case MODULE_CMD_INIT: 536 #ifdef _MODULE 537 error = config_init_component(cfdriver_ioconf_amdtemp, 538 cfattach_ioconf_amdtemp, cfdata_ioconf_amdtemp); 539 #endif 540 return error; 541 case MODULE_CMD_FINI: 542 #ifdef _MODULE 543 error = config_fini_component(cfdriver_ioconf_amdtemp, 544 cfattach_ioconf_amdtemp, cfdata_ioconf_amdtemp); 545 #endif 546 return error; 547 default: 548 return ENOTTY; 549 } 550 } 551
Indexes created Thu Oct 02 14:10:14 GMT 2025