dwiic_pci.c revision 1.4
1 /* $NetBSD: dwiic_pci.c,v 1.4 2021/04/24 23:36:51 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Manuel Bouyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /* 32 * Synopsys DesignWare I2C controller, PCI front-end 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: dwiic_pci.c,v 1.4 2021/04/24 23:36:51 thorpej Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcidevs.h> 44 45 #include <dev/acpi/acpivar.h> 46 #include <dev/acpi/acpi_pci.h> 47 #include <dev/acpi/acpi_util.h> 48 #include <dev/acpi/acpi_i2c.h> 49 50 #include <dev/ic/dwiic_var.h> 51 #include <arch/x86/pci/lpssreg.h> 52 53 //#define DWIIC_DEBUG 54 55 #ifdef DWIIC_DEBUG 56 #define DPRINTF(x) printf x 57 #else 58 #define DPRINTF(x) 59 #endif 60 61 struct pci_dwiic_softc { 62 struct dwiic_softc sc_dwiic; 63 pci_chipset_tag_t sc_pc; 64 pcitag_t sc_ptag; 65 struct acpi_devnode *sc_acpinode; 66 }; 67 68 static uint32_t 69 lpss_read(struct pci_dwiic_softc *sc, int offset) 70 { 71 u_int32_t b = bus_space_read_4(sc->sc_dwiic.sc_iot, sc->sc_dwiic.sc_ioh, 72 offset); 73 return b; 74 } 75 76 static void 77 lpss_write(struct pci_dwiic_softc *sc, int offset, uint32_t val) 78 { 79 bus_space_write_4(sc->sc_dwiic.sc_iot, sc->sc_dwiic.sc_ioh, 80 offset, val); 81 } 82 83 static int pci_dwiic_match(device_t, cfdata_t, void *); 84 static void pci_dwiic_attach(device_t, device_t, void *); 85 static bool dwiic_pci_power(struct dwiic_softc *, bool); 86 87 CFATTACH_DECL_NEW(pcidwiic, sizeof(struct pci_dwiic_softc), 88 pci_dwiic_match, pci_dwiic_attach, dwiic_detach, NULL); 89 90 91 int 92 pci_dwiic_match(device_t parent, cfdata_t match, void *aux) 93 { 94 struct pci_attach_args *pa = aux; 95 96 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 97 return 0; 98 99 if (PCI_PRODUCT(pa->pa_id) < PCI_PRODUCT_INTEL_100SERIES_LP_I2C_0 || 100 PCI_PRODUCT(pa->pa_id) > PCI_PRODUCT_INTEL_100SERIES_LP_I2C_3) 101 return 0; 102 103 return 1; 104 } 105 106 void 107 pci_dwiic_attach(device_t parent, device_t self, void *aux) 108 { 109 struct pci_dwiic_softc *sc = device_private(self); 110 struct pci_attach_args *pa = aux; 111 const char *intrstr; 112 pci_intr_handle_t intrhandle; 113 char intrbuf[PCI_INTRSTR_LEN]; 114 pcireg_t memtype; 115 pcireg_t csr; 116 uint32_t caps; 117 118 sc->sc_dwiic.sc_dev = self; 119 sc->sc_dwiic.sc_power = dwiic_pci_power; 120 sc->sc_dwiic.sc_type = dwiic_type_sunrisepoint; 121 122 sc->sc_pc = pa->pa_pc; 123 sc->sc_ptag = pa->pa_tag; 124 125 /* register access not enabled by BIOS */ 126 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 127 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 128 csr | PCI_COMMAND_MEM_ENABLE); 129 130 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_BAR0); 131 if (pci_mapreg_map(pa, PCI_BAR0, memtype, 0, &sc->sc_dwiic.sc_iot, 132 &sc->sc_dwiic.sc_ioh, NULL, NULL) != 0) { 133 aprint_error(": can't map register space\n"); 134 goto out; 135 } 136 dwiic_pci_power(&sc->sc_dwiic, 1); 137 138 caps = lpss_read(sc, LPSS_CAP); 139 140 aprint_naive(": I2C controller\n"); 141 aprint_normal(": I2C controller instance %d\n", 142 (int)(caps & LPSS_CAP_INSTANCE)); 143 144 if (pci_intr_map(pa, &intrhandle)) { 145 aprint_error_dev(self, "can't map interrupt\n"); 146 goto out; 147 } 148 intrstr = pci_intr_string(pa->pa_pc, intrhandle, 149 intrbuf, sizeof(intrbuf)); 150 151 sc->sc_dwiic.sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, 152 IPL_VM, dwiic_intr, sc); 153 if (sc->sc_dwiic.sc_ih == NULL) { 154 aprint_error_dev(self, "couldn't establish interrupt"); 155 if (intrstr != NULL) 156 aprint_error(" at %s", intrstr); 157 aprint_error("\n"); 158 goto out; 159 } 160 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 161 162 lpss_write(sc, LPSS_RESET, LPSS_RESET_CTRL_REL); 163 lpss_write(sc, LPSS_REMAP_LO, 164 pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_BAR0)); 165 lpss_write(sc, LPSS_REMAP_HI, 166 pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_BAR0 + 0x4)); 167 168 sc->sc_acpinode = acpi_pcidev_find(0 /*XXX segment*/, 169 pa->pa_bus, pa->pa_device, pa->pa_function); 170 171 if (sc->sc_acpinode) { 172 sc->sc_dwiic.sc_iba.iba_child_devices = 173 acpi_enter_i2c_devs(NULL, sc->sc_acpinode); 174 } else { 175 aprint_verbose_dev(self, "no matching ACPI node\n"); 176 } 177 178 dwiic_attach(&sc->sc_dwiic); 179 180 config_found(self, &sc->sc_dwiic.sc_iba, iicbus_print, CFARG_EOL); 181 182 pmf_device_register(self, dwiic_suspend, dwiic_resume); 183 184 out: 185 return; 186 } 187 188 static bool 189 dwiic_pci_power(struct dwiic_softc *dwsc, bool power) 190 { 191 struct pci_dwiic_softc *sc = (void *)dwsc; 192 pcireg_t pmreg; 193 194 printf("status 0x%x\n", pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_COMMAND_STATUS_REG)); 195 printf("reset 0x%x\n", lpss_read(sc, LPSS_RESET)); 196 printf("rlo 0x%x\n", lpss_read(sc, LPSS_REMAP_LO)); 197 printf("rho 0x%x\n", lpss_read(sc, LPSS_REMAP_HI)); 198 199 if (!power) 200 lpss_write(sc, LPSS_CLKGATE, LPSS_CLKGATE_CTRL_OFF); 201 if (pci_get_capability(sc->sc_pc, sc->sc_ptag, PCI_CAP_PWRMGMT, 202 &pmreg, NULL)) { 203 DPRINTF(("%s: power status 0x%x", device_xname(dwsc->sc_dev), 204 pci_conf_read(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR))); 205 pci_conf_write(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR, 206 power ? PCI_PMCSR_STATE_D0 : PCI_PMCSR_STATE_D3); 207 DELAY(10000); /* 10 milliseconds */ 208 DPRINTF((" -> 0x%x\n", 209 pci_conf_read(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR))); 210 } 211 if (power) { 212 lpss_write(sc, LPSS_CLKGATE, LPSS_CLKGATE_CTRL_ON); 213 } 214 return true; 215 } 216
Indexes created Wed Oct 01 12:09:54 GMT 2025