dwiic_pci.c revision 1.4.2.2
1 /* $NetBSD: dwiic_pci.c,v 1.4.2.2 2021/04/25 22:02:59 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Manuel Bouyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /* 32 * Synopsys DesignWare I2C controller, PCI front-end 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: dwiic_pci.c,v 1.4.2.2 2021/04/25 22:02:59 thorpej Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcidevs.h> 44 45 #include <dev/ic/dwiic_var.h> 46 #include <arch/x86/pci/lpssreg.h> 47 48 //#define DWIIC_DEBUG 49 50 #ifdef DWIIC_DEBUG 51 #define DPRINTF(x) printf x 52 #else 53 #define DPRINTF(x) 54 #endif 55 56 struct pci_dwiic_softc { 57 struct dwiic_softc sc_dwiic; 58 pci_chipset_tag_t sc_pc; 59 pcitag_t sc_ptag; 60 }; 61 62 static uint32_t 63 lpss_read(struct pci_dwiic_softc *sc, int offset) 64 { 65 u_int32_t b = bus_space_read_4(sc->sc_dwiic.sc_iot, sc->sc_dwiic.sc_ioh, 66 offset); 67 return b; 68 } 69 70 static void 71 lpss_write(struct pci_dwiic_softc *sc, int offset, uint32_t val) 72 { 73 bus_space_write_4(sc->sc_dwiic.sc_iot, sc->sc_dwiic.sc_ioh, 74 offset, val); 75 } 76 77 static int pci_dwiic_match(device_t, cfdata_t, void *); 78 static void pci_dwiic_attach(device_t, device_t, void *); 79 static bool dwiic_pci_power(struct dwiic_softc *, bool); 80 81 CFATTACH_DECL_NEW(pcidwiic, sizeof(struct pci_dwiic_softc), 82 pci_dwiic_match, pci_dwiic_attach, dwiic_detach, NULL); 83 84 85 int 86 pci_dwiic_match(device_t parent, cfdata_t match, void *aux) 87 { 88 struct pci_attach_args *pa = aux; 89 90 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 91 return 0; 92 93 if (PCI_PRODUCT(pa->pa_id) < PCI_PRODUCT_INTEL_100SERIES_LP_I2C_0 || 94 PCI_PRODUCT(pa->pa_id) > PCI_PRODUCT_INTEL_100SERIES_LP_I2C_3) 95 return 0; 96 97 return 1; 98 } 99 100 void 101 pci_dwiic_attach(device_t parent, device_t self, void *aux) 102 { 103 struct pci_dwiic_softc *sc = device_private(self); 104 struct pci_attach_args *pa = aux; 105 const char *intrstr; 106 pci_intr_handle_t intrhandle; 107 char intrbuf[PCI_INTRSTR_LEN]; 108 pcireg_t memtype; 109 pcireg_t csr; 110 uint32_t caps; 111 112 sc->sc_dwiic.sc_dev = self; 113 sc->sc_dwiic.sc_power = dwiic_pci_power; 114 sc->sc_dwiic.sc_type = dwiic_type_sunrisepoint; 115 116 sc->sc_pc = pa->pa_pc; 117 sc->sc_ptag = pa->pa_tag; 118 119 /* register access not enabled by BIOS */ 120 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 121 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 122 csr | PCI_COMMAND_MEM_ENABLE); 123 124 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_BAR0); 125 if (pci_mapreg_map(pa, PCI_BAR0, memtype, 0, &sc->sc_dwiic.sc_iot, 126 &sc->sc_dwiic.sc_ioh, NULL, NULL) != 0) { 127 aprint_error(": can't map register space\n"); 128 goto out; 129 } 130 dwiic_pci_power(&sc->sc_dwiic, 1); 131 132 caps = lpss_read(sc, LPSS_CAP); 133 134 aprint_naive(": I2C controller\n"); 135 aprint_normal(": I2C controller instance %d\n", 136 (int)(caps & LPSS_CAP_INSTANCE)); 137 138 if (pci_intr_map(pa, &intrhandle)) { 139 aprint_error_dev(self, "can't map interrupt\n"); 140 goto out; 141 } 142 intrstr = pci_intr_string(pa->pa_pc, intrhandle, 143 intrbuf, sizeof(intrbuf)); 144 145 sc->sc_dwiic.sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, 146 IPL_VM, dwiic_intr, sc); 147 if (sc->sc_dwiic.sc_ih == NULL) { 148 aprint_error_dev(self, "couldn't establish interrupt"); 149 if (intrstr != NULL) 150 aprint_error(" at %s", intrstr); 151 aprint_error("\n"); 152 goto out; 153 } 154 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 155 156 lpss_write(sc, LPSS_RESET, LPSS_RESET_CTRL_REL); 157 lpss_write(sc, LPSS_REMAP_LO, 158 pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_BAR0)); 159 lpss_write(sc, LPSS_REMAP_HI, 160 pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_BAR0 + 0x4)); 161 162 dwiic_attach(&sc->sc_dwiic); 163 164 config_found(self, &sc->sc_dwiic.sc_iba, iicbus_print, 165 CFARG_DEVHANDLE, device_handle(self), 166 CFARG_EOL); 167 168 pmf_device_register(self, dwiic_suspend, dwiic_resume); 169 170 out: 171 return; 172 } 173 174 static bool 175 dwiic_pci_power(struct dwiic_softc *dwsc, bool power) 176 { 177 struct pci_dwiic_softc *sc = (void *)dwsc; 178 pcireg_t pmreg; 179 180 printf("status 0x%x\n", pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_COMMAND_STATUS_REG)); 181 printf("reset 0x%x\n", lpss_read(sc, LPSS_RESET)); 182 printf("rlo 0x%x\n", lpss_read(sc, LPSS_REMAP_LO)); 183 printf("rho 0x%x\n", lpss_read(sc, LPSS_REMAP_HI)); 184 185 if (!power) 186 lpss_write(sc, LPSS_CLKGATE, LPSS_CLKGATE_CTRL_OFF); 187 if (pci_get_capability(sc->sc_pc, sc->sc_ptag, PCI_CAP_PWRMGMT, 188 &pmreg, NULL)) { 189 DPRINTF(("%s: power status 0x%x", device_xname(dwsc->sc_dev), 190 pci_conf_read(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR))); 191 pci_conf_write(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR, 192 power ? PCI_PMCSR_STATE_D0 : PCI_PMCSR_STATE_D3); 193 DELAY(10000); /* 10 milliseconds */ 194 DPRINTF((" -> 0x%x\n", 195 pci_conf_read(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR))); 196 } 197 if (power) { 198 lpss_write(sc, LPSS_CLKGATE, LPSS_CLKGATE_CTRL_ON); 199 } 200 return true; 201 } 202
Indexes created Wed Oct 15 16:09:53 GMT 2025