ichlpcib.c revision 1.1
1 /* $NetBSD: ichlpcib.c,v 1.1 2007/08/26 16:49:47 xtraeme Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 41 * 42 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 43 * some power management and monitoring functions. 44 * Currently we support the watchdog timer, SpeedStep (on some systems) 45 * and the power management timer. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.1 2007/08/26 16:49:47 xtraeme Exp $"); 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/sysctl.h> 56 #include <machine/bus.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/sysmon/sysmonvar.h> 63 64 #include <dev/ic/i82801lpcreg.h> 65 #include <dev/ic/acpipmtimer.h> 66 67 struct lpcib_softc { 68 /* Device object. */ 69 struct device sc_dev; 70 71 pci_chipset_tag_t sc_pc; 72 pcitag_t sc_pcitag; 73 74 /* Watchdog variables. */ 75 struct sysmon_wdog sc_smw; 76 bus_space_tag_t sc_iot; 77 bus_space_handle_t sc_ioh; 78 79 /* Power management */ 80 void *sc_powerhook; 81 struct pci_conf_state sc_pciconf; 82 pcireg_t sc_pirq[8]; 83 }; 84 85 static int lpcibmatch(struct device *, struct cfdata *, void *); 86 static void lpcibattach(struct device *, struct device *, void *); 87 static void lpcib_powerhook(int, void *); 88 89 static void pmtimer_configure(struct lpcib_softc *, struct pci_attach_args *); 90 91 static void tcotimer_configure(struct lpcib_softc *, struct pci_attach_args *); 92 static int tcotimer_setmode(struct sysmon_wdog *); 93 static int tcotimer_tickle(struct sysmon_wdog *); 94 static void tcotimer_stop(struct lpcib_softc *); 95 static void tcotimer_start(struct lpcib_softc *); 96 static void tcotimer_status_reset(struct lpcib_softc *); 97 static int tcotimer_disable_noreboot(struct lpcib_softc *, bus_space_tag_t, 98 bus_space_handle_t); 99 100 static void speedstep_configure(struct lpcib_softc *, struct pci_attach_args *); 101 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 102 103 struct lpcib_softc *speedstep_cookie; /* XXX */ 104 static int lpcib_ich6 = 0; 105 106 /* Defined in arch/.../pci/pcib.c. */ 107 extern void pcibattach(struct device *, struct device *, void *); 108 109 CFATTACH_DECL(ichlpcib, sizeof(struct lpcib_softc), 110 lpcibmatch, lpcibattach, NULL, NULL); 111 112 /* 113 * Autoconf callbacks. 114 */ 115 static int 116 lpcibmatch(struct device *parent, struct cfdata *match, void *aux) 117 { 118 struct pci_attach_args *pa = aux; 119 120 /* We are ISA bridge, of course */ 121 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 122 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 123 return 0; 124 125 /* Matches only Intel ICH */ 126 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 127 switch (PCI_PRODUCT(pa->pa_id)) { 128 case PCI_PRODUCT_INTEL_82801AA_LPC: /* ICH */ 129 case PCI_PRODUCT_INTEL_82801AB_LPC: /* ICH0 */ 130 case PCI_PRODUCT_INTEL_82801BA_LPC: /* ICH2 */ 131 case PCI_PRODUCT_INTEL_82801BAM_LPC: /* ICH2-M */ 132 case PCI_PRODUCT_INTEL_82801CA_LPC: /* ICH3-S */ 133 case PCI_PRODUCT_INTEL_82801CAM_LPC: /* ICH3-M */ 134 case PCI_PRODUCT_INTEL_82801DB_LPC: /* ICH4 */ 135 case PCI_PRODUCT_INTEL_82801DB_ISA: /* ICH4-M */ 136 case PCI_PRODUCT_INTEL_82801EB_LPC: /* ICH5 */ 137 return 10; 138 case PCI_PRODUCT_INTEL_82801FB_LPC: /* ICH6 */ 139 case PCI_PRODUCT_INTEL_82801FBM_LPC: /* ICH6-M */ 140 case PCI_PRODUCT_INTEL_82801G_LPC: /* ICH7 */ 141 case PCI_PRODUCT_INTEL_82801GBM_LPC: /* ICH7-M */ 142 case PCI_PRODUCT_INTEL_82801GHM_LPC: /* ICH7-M DH */ 143 case PCI_PRODUCT_INTEL_82801H_LPC: /* ICH8 */ 144 case PCI_PRODUCT_INTEL_82801HH_LPC: /* ICH8 DH */ 145 case PCI_PRODUCT_INTEL_82801HO_LPC: /* ICH8 DO */ 146 lpcib_ich6 = 1; 147 return 10; /* prior to pcib */ 148 } 149 } 150 151 return 0; 152 } 153 154 static void 155 lpcibattach(struct device *parent, struct device *self, void *aux) 156 { 157 struct pci_attach_args *pa = aux; 158 struct lpcib_softc *sc = (void*) self; 159 160 sc->sc_pc = pa->pa_pc; 161 sc->sc_pcitag = pa->pa_tag; 162 163 pcibattach(parent, self, aux); 164 165 /* 166 * Part of our I/O registers are used as ACPI PM regs. 167 * Since our ACPI subsystem accesses the I/O space directly so far, 168 * we do not have to bother bus_space I/O map confliction. 169 */ 170 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 171 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 172 aprint_error("%s: can't map power management i/o space", 173 sc->sc_dev.dv_xname); 174 return; 175 } 176 177 /* Set up the power management timer. */ 178 pmtimer_configure(sc, pa); 179 180 /* Set up the TCO (watchdog). */ 181 tcotimer_configure(sc, pa); 182 183 /* Set up SpeedStep. */ 184 speedstep_configure(sc, pa); 185 186 /* Install powerhook */ 187 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 188 lpcib_powerhook, sc); 189 if (sc->sc_powerhook == NULL) 190 aprint_error("%s: can't establish powerhook\n", 191 sc->sc_dev.dv_xname); 192 } 193 194 static void 195 lpcib_powerhook(int why, void *opaque) 196 { 197 struct lpcib_softc *sc; 198 pci_chipset_tag_t pc; 199 pcitag_t tag; 200 201 sc = (struct lpcib_softc *)opaque; 202 pc = sc->sc_pc; 203 tag = sc->sc_pcitag; 204 205 switch (why) { 206 case PWR_SUSPEND: 207 pci_conf_capture(pc, tag, &sc->sc_pciconf); 208 209 /* capture PIRQ routing control registers */ 210 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 211 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQB_ROUT); 212 sc->sc_pirq[2] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQC_ROUT); 213 sc->sc_pirq[3] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQD_ROUT); 214 sc->sc_pirq[4] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 215 sc->sc_pirq[5] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQF_ROUT); 216 sc->sc_pirq[6] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQG_ROUT); 217 sc->sc_pirq[7] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQH_ROUT); 218 219 break; 220 221 case PWR_RESUME: 222 pci_conf_restore(pc, tag, &sc->sc_pciconf); 223 224 /* restore PIRQ routing control registers */ 225 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 226 pci_conf_write(pc, tag, LPCIB_PCI_PIRQB_ROUT, sc->sc_pirq[1]); 227 pci_conf_write(pc, tag, LPCIB_PCI_PIRQC_ROUT, sc->sc_pirq[2]); 228 pci_conf_write(pc, tag, LPCIB_PCI_PIRQD_ROUT, sc->sc_pirq[3]); 229 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[4]); 230 pci_conf_write(pc, tag, LPCIB_PCI_PIRQF_ROUT, sc->sc_pirq[5]); 231 pci_conf_write(pc, tag, LPCIB_PCI_PIRQG_ROUT, sc->sc_pirq[6]); 232 pci_conf_write(pc, tag, LPCIB_PCI_PIRQH_ROUT, sc->sc_pirq[7]); 233 234 break; 235 } 236 } 237 238 /* 239 * Initialize the power management timer. 240 */ 241 static void 242 pmtimer_configure(struct lpcib_softc *sc, struct pci_attach_args *pa) 243 { 244 pcireg_t control; 245 246 /* 247 * Check if power management I/O space is enabled and enable the ACPI_EN 248 * bit if it's disabled. 249 */ 250 control = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_PCI_ACPI_CNTL); 251 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 252 control |= LPCIB_PCI_ACPI_CNTL_EN; 253 pci_conf_write(pa->pa_pc, pa->pa_tag, LPCIB_PCI_ACPI_CNTL, 254 control); 255 } 256 257 /* Attach our PM timer with the generic acpipmtimer function */ 258 acpipmtimer_attach(&sc->sc_dev, sc->sc_iot, sc->sc_ioh, 259 LPCIB_PM1_TMR, 0); 260 } 261 262 /* 263 * Initialize the watchdog timer. 264 */ 265 static void 266 tcotimer_configure(struct lpcib_softc *sc, struct pci_attach_args *pa) 267 { 268 bus_space_handle_t gcs_memh; 269 pcireg_t pcireg; 270 uint32_t ioreg; 271 unsigned int period; 272 273 /* 274 * Map the memory space necessary for the GCS register. 275 * This is only used for ICH6 or newer, to clear the NO_REBOOT 276 * bit. 277 */ 278 if (lpcib_ich6) { 279 pcireg = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_RCBA); 280 pcireg &= 0xffffc000; 281 if (bus_space_map(pa->pa_memt, pcireg + LPCIB_GCS_OFFSET, 282 LPCIB_GCS_SIZE, 0, &gcs_memh)) { 283 aprint_error("%s: can't map GCS memory space; " 284 "TCO timer disabled\n", sc->sc_dev.dv_xname); 285 return; 286 } 287 } 288 289 /* 290 * Clear the NO_REBOOT bit. If this fails, enabling the TCO_EN bit 291 * in the SMI_EN register is the last chance. 292 */ 293 if (tcotimer_disable_noreboot(sc, pa->pa_memt, gcs_memh)) { 294 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 295 ioreg |= LPCIB_SMI_EN_TCO_EN; 296 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 297 } 298 299 /* Reset the watchdog status registers. */ 300 tcotimer_status_reset(sc); 301 302 /* Explicitly stop the TCO timer. */ 303 tcotimer_stop(sc); 304 305 /* 306 * Register the driver with the sysmon watchdog framework. 307 */ 308 sc->sc_smw.smw_name = sc->sc_dev.dv_xname; 309 sc->sc_smw.smw_cookie = sc; 310 sc->sc_smw.smw_setmode = tcotimer_setmode; 311 sc->sc_smw.smw_tickle = tcotimer_tickle; 312 if (lpcib_ich6) 313 period = LPCIB_TCOTIMER2_MAX_TICK; 314 else 315 period = LPCIB_TCOTIMER_MAX_TICK; 316 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 317 318 if (sysmon_wdog_register(&sc->sc_smw)) { 319 aprint_error("%s: unable to register TCO timer" 320 "as a sysmon watchdog device.\n", 321 sc->sc_dev.dv_xname); 322 return; 323 } 324 325 aprint_verbose("%s: TCO (watchdog) timer configured.\n", 326 sc->sc_dev.dv_xname); 327 } 328 329 /* 330 * Sysmon watchdog callbacks. 331 */ 332 static int 333 tcotimer_setmode(struct sysmon_wdog *smw) 334 { 335 struct lpcib_softc *sc = smw->smw_cookie; 336 unsigned int period; 337 uint16_t ich6period = 0; 338 339 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 340 /* Stop the TCO timer. */ 341 tcotimer_stop(sc); 342 } else { 343 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 344 /* 345 * ICH5 or older are limited to 4s min and 39s max. 346 * ICH6 or newer are limited to 2s min and 613s max. 347 */ 348 if (!lpcib_ich6) { 349 if (period < LPCIB_TCOTIMER_MIN_TICK || 350 period > LPCIB_TCOTIMER_MAX_TICK) 351 return EINVAL; 352 } else { 353 if (period < LPCIB_TCOTIMER2_MIN_TICK || 354 period > LPCIB_TCOTIMER2_MAX_TICK) 355 return EINVAL; 356 } 357 358 /* Stop the TCO timer, */ 359 tcotimer_stop(sc); 360 361 /* set the timeout, */ 362 if (lpcib_ich6) { 363 /* ICH6 or newer */ 364 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 365 LPCIB_TCO_TMR2); 366 ich6period &= 0xfc00; 367 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 368 LPCIB_TCO_TMR2, ich6period | period); 369 } else { 370 /* ICH5 or older */ 371 period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, 372 LPCIB_TCO_TMR); 373 period &= 0xc0; 374 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 375 LPCIB_TCO_TMR, period); 376 } 377 378 /* and start/reload the timer. */ 379 tcotimer_start(sc); 380 tcotimer_tickle(smw); 381 } 382 383 return 0; 384 } 385 386 static int 387 tcotimer_tickle(struct sysmon_wdog *smw) 388 { 389 struct lpcib_softc *sc = smw->smw_cookie; 390 391 /* any value is allowed */ 392 if (!lpcib_ich6) 393 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 394 else 395 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 396 397 return 0; 398 } 399 400 static void 401 tcotimer_stop(struct lpcib_softc *sc) 402 { 403 uint16_t ioreg; 404 405 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 406 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 407 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 408 } 409 410 static void 411 tcotimer_start(struct lpcib_softc *sc) 412 { 413 uint16_t ioreg; 414 415 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 416 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 417 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 418 } 419 420 static void 421 tcotimer_status_reset(struct lpcib_softc *sc) 422 { 423 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 424 LPCIB_TCO1_STS_TIMEOUT); 425 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 426 LPCIB_TCO2_STS_BOOT_STS); 427 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 428 LPCIB_TCO2_STS_SECONDS_TO_STS); 429 } 430 431 /* 432 * Clear the NO_REBOOT bit, this enables reboots. 433 */ 434 static int 435 tcotimer_disable_noreboot(struct lpcib_softc *sc, bus_space_tag_t gcs_memt, 436 bus_space_handle_t gcs_memh) 437 { 438 pcireg_t pcireg; 439 uint16_t status = 0; 440 441 if (!lpcib_ich6) { 442 pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 443 LPCIB_PCI_GEN_STA); 444 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 445 /* TCO timeout reset is disabled; try to enable it */ 446 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 447 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 448 LPCIB_PCI_GEN_STA, pcireg); 449 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 450 goto error; 451 } 452 } else { 453 status = bus_space_read_4(gcs_memt, gcs_memh, 0); 454 status &= ~LPCIB_GCS_NO_REBOOT; 455 bus_space_write_4(gcs_memt, gcs_memh, 0, status); 456 status = bus_space_read_4(gcs_memt, gcs_memh, 0); 457 bus_space_unmap(gcs_memt, gcs_memh, LPCIB_GCS_SIZE); 458 if (status & LPCIB_GCS_NO_REBOOT) 459 goto error; 460 } 461 462 return 0; 463 error: 464 aprint_error("%s: TCO timer reboot disabled by hardware; " 465 "hope SMBIOS properly handles it.\n", sc->sc_dev.dv_xname); 466 return EINVAL; 467 } 468 469 470 /* 471 * Intel ICH SpeedStep support. 472 */ 473 #define SS_READ(sc, reg) \ 474 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 475 #define SS_WRITE(sc, reg, val) \ 476 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 477 478 /* 479 * Linux driver says that SpeedStep on older chipsets cause 480 * lockups on Dell Inspiron 8000 and 8100. 481 */ 482 static int 483 speedstep_bad_hb_check(struct pci_attach_args *pa) 484 { 485 486 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 487 PCI_REVISION(pa->pa_class) < 5) 488 return 1; 489 490 return 0; 491 } 492 493 static void 494 speedstep_configure(struct lpcib_softc *sc, struct pci_attach_args *pa) 495 { 496 const struct sysctlnode *node, *ssnode; 497 int rv; 498 499 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 500 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 501 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 502 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 503 pci_find_device(pa, speedstep_bad_hb_check) == 0)) { 504 uint8_t pmcon; 505 506 /* Enable SpeedStep if it isn't already enabled. */ 507 pmcon = pci_conf_read(pa->pa_pc, pa->pa_tag, 508 LPCIB_PCI_GEN_PMCON_1); 509 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 510 pci_conf_write(pa->pa_pc, pa->pa_tag, 511 LPCIB_PCI_GEN_PMCON_1, 512 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 513 514 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 515 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 516 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 517 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 518 goto err; 519 520 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 521 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 522 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 523 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 524 CTL_EOL)) != 0) 525 goto err; 526 527 /* XXX save the sc for IO tag/handle */ 528 speedstep_cookie = sc; 529 aprint_verbose("%s: SpeedStep enabled\n", sc->sc_dev.dv_xname); 530 } 531 532 return; 533 534 err: 535 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 536 } 537 538 /* 539 * get/set the SpeedStep state: 0 == low power, 1 == high power. 540 */ 541 static int 542 speedstep_sysctl_helper(SYSCTLFN_ARGS) 543 { 544 struct sysctlnode node; 545 struct lpcib_softc *sc = speedstep_cookie; 546 uint8_t state, state2; 547 int ostate, nstate, s, error = 0; 548 549 /* 550 * We do the dance with spl's to avoid being at high ipl during 551 * sysctl_lookup() which can both copyin and copyout. 552 */ 553 s = splserial(); 554 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 555 splx(s); 556 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 557 ostate = 1; 558 else 559 ostate = 0; 560 nstate = ostate; 561 562 node = *rnode; 563 node.sysctl_data = &nstate; 564 565 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 566 if (error || newp == NULL) 567 goto out; 568 569 /* Only two states are available */ 570 if (nstate != 0 && nstate != 1) { 571 error = EINVAL; 572 goto out; 573 } 574 575 s = splserial(); 576 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 577 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 578 ostate = 1; 579 else 580 ostate = 0; 581 582 if (ostate != nstate) { 583 uint8_t cntl; 584 585 if (nstate == 0) 586 state2 |= LPCIB_PM_SS_STATE_LOW; 587 else 588 state2 &= ~LPCIB_PM_SS_STATE_LOW; 589 590 /* 591 * Must disable bus master arbitration during the change. 592 */ 593 cntl = SS_READ(sc, LPCIB_PM_CTRL); 594 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 595 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 596 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 597 } 598 splx(s); 599 out: 600 return error; 601 } 602
Indexes created Tue Sep 30 20:09:53 GMT 2025