ichlpcib.c revision 1.10
1 /* $NetBSD: ichlpcib.c,v 1.10 2008/04/16 16:06:51 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 41 * 42 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 43 * some power management and monitoring functions. 44 * Currently we support the watchdog timer, SpeedStep (on some systems) 45 * and the power management timer. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.10 2008/04/16 16:06:51 cegger Exp $"); 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/sysctl.h> 56 #include <sys/timetc.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/sysmon/sysmonvar.h> 64 65 #include <dev/ic/acpipmtimer.h> 66 #include <dev/ic/i82801lpcreg.h> 67 #include <dev/ic/hpetreg.h> 68 #include <dev/ic/hpetvar.h> 69 70 #include "hpet.h" 71 72 struct lpcib_softc { 73 pci_chipset_tag_t sc_pc; 74 pcitag_t sc_pcitag; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 90 #if NHPET > 0 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 #endif 94 95 /* Power management */ 96 pcireg_t sc_pirq[2]; 97 pcireg_t sc_pmcon; 98 pcireg_t sc_fwhsel2; 99 }; 100 101 static int lpcibmatch(device_t, cfdata_t, void *); 102 static void lpcibattach(device_t, device_t, void *); 103 static bool lpcib_suspend(device_t PMF_FN_PROTO); 104 static bool lpcib_resume(device_t PMF_FN_PROTO); 105 106 static void pmtimer_configure(device_t); 107 108 static void tcotimer_configure(device_t); 109 static int tcotimer_setmode(struct sysmon_wdog *); 110 static int tcotimer_tickle(struct sysmon_wdog *); 111 static void tcotimer_stop(struct lpcib_softc *); 112 static void tcotimer_start(struct lpcib_softc *); 113 static void tcotimer_status_reset(struct lpcib_softc *); 114 static int tcotimer_disable_noreboot(device_t); 115 116 static void speedstep_configure(device_t); 117 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 118 119 #if NHPET > 0 120 static void lpcib_hpet_configure(device_t); 121 #endif 122 123 struct lpcib_softc *speedstep_cookie; /* XXX */ 124 125 /* Defined in arch/.../pci/pcib.c. */ 126 extern void pcibattach(device_t, device_t, void *); 127 128 CFATTACH_DECL_NEW(ichlpcib, sizeof(struct lpcib_softc), 129 lpcibmatch, lpcibattach, NULL, NULL); 130 131 static struct lpcib_device { 132 pcireg_t vendor, product; 133 int has_rcba; 134 int has_ich5_hpet; 135 } lpcib_devices[] = { 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 0, 0 }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 158 { 0, 0, 0, 0 }, 159 }; 160 161 /* 162 * Autoconf callbacks. 163 */ 164 static int 165 lpcibmatch(device_t parent, cfdata_t match, void *aux) 166 { 167 struct pci_attach_args *pa = aux; 168 struct lpcib_device *lpcib_dev; 169 170 /* We are ISA bridge, of course */ 171 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 172 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 173 return 0; 174 175 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 176 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 177 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 178 return 10; 179 } 180 181 return 0; 182 } 183 184 static void 185 lpcibattach(device_t parent, device_t self, void *aux) 186 { 187 struct pci_attach_args *pa = aux; 188 struct lpcib_softc *sc = device_private(self); 189 struct lpcib_device *lpcib_dev; 190 191 sc->sc_pc = pa->pa_pc; 192 sc->sc_pcitag = pa->pa_tag; 193 sc->sc_pa = *pa; 194 195 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 196 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 197 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 198 continue; 199 sc->sc_has_rcba = lpcib_dev->has_rcba; 200 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 201 break; 202 } 203 204 pcibattach(parent, self, aux); 205 206 /* 207 * Part of our I/O registers are used as ACPI PM regs. 208 * Since our ACPI subsystem accesses the I/O space directly so far, 209 * we do not have to bother bus_space I/O map confliction. 210 */ 211 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 212 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 213 aprint_error_dev(self, "can't map power management i/o space"); 214 return; 215 } 216 217 /* For ICH6 and later, always enable RCBA */ 218 if (sc->sc_has_rcba) { 219 pcireg_t rcba; 220 221 sc->sc_rcbat = sc->sc_pa.pa_memt; 222 223 rcba = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_RCBA); 224 if ((rcba & LPCIB_RCBA_EN) == 0) { 225 aprint_error_dev(self, "RCBA is not enabled"); 226 return; 227 } 228 rcba &= ~LPCIB_RCBA_EN; 229 230 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 231 &sc->sc_rcbah)) { 232 aprint_error_dev(self, "RCBA could not be mapped"); 233 return; 234 } 235 } 236 237 /* Set up the power management timer. */ 238 pmtimer_configure(self); 239 240 /* Set up the TCO (watchdog). */ 241 tcotimer_configure(self); 242 243 /* Set up SpeedStep. */ 244 speedstep_configure(self); 245 246 #if NHPET > 0 247 /* Set up HPET. */ 248 lpcib_hpet_configure(self); 249 #endif 250 251 /* Install power handler */ 252 if (!pmf_device_register(self, lpcib_suspend, lpcib_resume)) 253 aprint_error_dev(self, "couldn't establish power handler\n"); 254 } 255 256 static bool 257 lpcib_suspend(device_t dv PMF_FN_ARGS) 258 { 259 struct lpcib_softc *sc = device_private(dv); 260 pci_chipset_tag_t pc = sc->sc_pc; 261 pcitag_t tag = sc->sc_pcitag; 262 263 /* capture PIRQ routing control registers */ 264 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 265 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 266 267 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 268 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 269 270 if (sc->sc_has_rcba) { 271 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 272 #if NHPET > 0 273 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 274 LPCIB_RCBA_HPTC); 275 #endif 276 } else if (sc->sc_has_ich5_hpet) { 277 #if NHPET > 0 278 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 279 #endif 280 } 281 282 return true; 283 } 284 285 static bool 286 lpcib_resume(device_t dv PMF_FN_ARGS) 287 { 288 struct lpcib_softc *sc = device_private(dv); 289 pci_chipset_tag_t pc = sc->sc_pc; 290 pcitag_t tag = sc->sc_pcitag; 291 292 /* restore PIRQ routing control registers */ 293 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 294 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 295 296 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 297 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 298 299 if (sc->sc_has_rcba) { 300 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 301 #if NHPET > 0 302 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 303 sc->sc_hpet_reg); 304 #endif 305 } else if (sc->sc_has_ich5_hpet) { 306 #if NHPET > 0 307 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 308 #endif 309 } 310 311 return true; 312 } 313 314 /* 315 * Initialize the power management timer. 316 */ 317 static void 318 pmtimer_configure(device_t self) 319 { 320 struct lpcib_softc *sc = device_private(self); 321 pcireg_t control; 322 323 /* 324 * Check if power management I/O space is enabled and enable the ACPI_EN 325 * bit if it's disabled. 326 */ 327 control = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL); 328 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 329 control |= LPCIB_PCI_ACPI_CNTL_EN; 330 pci_conf_write(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL, 331 control); 332 } 333 334 /* Attach our PM timer with the generic acpipmtimer function */ 335 acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 336 LPCIB_PM1_TMR, 0); 337 } 338 339 /* 340 * Initialize the watchdog timer. 341 */ 342 static void 343 tcotimer_configure(device_t self) 344 { 345 struct lpcib_softc *sc = device_private(self); 346 uint32_t ioreg; 347 unsigned int period; 348 349 /* 350 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 351 * in the SMI_EN register is the last chance. 352 */ 353 if (tcotimer_disable_noreboot(self)) { 354 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 355 ioreg |= LPCIB_SMI_EN_TCO_EN; 356 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 357 } 358 359 /* Reset the watchdog status registers. */ 360 tcotimer_status_reset(sc); 361 362 /* Explicitly stop the TCO timer. */ 363 tcotimer_stop(sc); 364 365 /* 366 * Register the driver with the sysmon watchdog framework. 367 */ 368 sc->sc_smw.smw_name = device_xname(self); 369 sc->sc_smw.smw_cookie = sc; 370 sc->sc_smw.smw_setmode = tcotimer_setmode; 371 sc->sc_smw.smw_tickle = tcotimer_tickle; 372 if (sc->sc_has_rcba) 373 period = LPCIB_TCOTIMER2_MAX_TICK; 374 else 375 period = LPCIB_TCOTIMER_MAX_TICK; 376 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 377 378 if (sysmon_wdog_register(&sc->sc_smw)) { 379 aprint_error_dev(self, "unable to register TCO timer" 380 "as a sysmon watchdog device.\n"); 381 return; 382 } 383 384 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 385 } 386 387 /* 388 * Sysmon watchdog callbacks. 389 */ 390 static int 391 tcotimer_setmode(struct sysmon_wdog *smw) 392 { 393 struct lpcib_softc *sc = smw->smw_cookie; 394 unsigned int period; 395 uint16_t ich6period = 0; 396 397 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 398 /* Stop the TCO timer. */ 399 tcotimer_stop(sc); 400 } else { 401 /* 402 * ICH6 or newer are limited to 2s min and 613s max. 403 * ICH5 or older are limited to 4s min and 39s max. 404 */ 405 if (sc->sc_has_rcba) { 406 if (smw->smw_period < LPCIB_TCOTIMER2_MIN_TICK || 407 smw->smw_period > LPCIB_TCOTIMER2_MAX_TICK) 408 return EINVAL; 409 } else { 410 if (smw->smw_period < LPCIB_TCOTIMER_MIN_TICK || 411 smw->smw_period > LPCIB_TCOTIMER_MAX_TICK) 412 return EINVAL; 413 } 414 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 415 416 /* Stop the TCO timer, */ 417 tcotimer_stop(sc); 418 419 /* set the timeout, */ 420 if (sc->sc_has_rcba) { 421 /* ICH6 or newer */ 422 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 423 LPCIB_TCO_TMR2); 424 ich6period &= 0xfc00; 425 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 426 LPCIB_TCO_TMR2, ich6period | period); 427 } else { 428 /* ICH5 or older */ 429 period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, 430 LPCIB_TCO_TMR); 431 period &= 0xc0; 432 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 433 LPCIB_TCO_TMR, period); 434 } 435 436 /* and start/reload the timer. */ 437 tcotimer_start(sc); 438 tcotimer_tickle(smw); 439 } 440 441 return 0; 442 } 443 444 static int 445 tcotimer_tickle(struct sysmon_wdog *smw) 446 { 447 struct lpcib_softc *sc = smw->smw_cookie; 448 449 /* any value is allowed */ 450 if (sc->sc_has_rcba) 451 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 452 else 453 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 454 455 return 0; 456 } 457 458 static void 459 tcotimer_stop(struct lpcib_softc *sc) 460 { 461 uint16_t ioreg; 462 463 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 464 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 465 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 466 } 467 468 static void 469 tcotimer_start(struct lpcib_softc *sc) 470 { 471 uint16_t ioreg; 472 473 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 474 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 475 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 476 } 477 478 static void 479 tcotimer_status_reset(struct lpcib_softc *sc) 480 { 481 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 482 LPCIB_TCO1_STS_TIMEOUT); 483 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 484 LPCIB_TCO2_STS_BOOT_STS); 485 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 486 LPCIB_TCO2_STS_SECONDS_TO_STS); 487 } 488 489 /* 490 * Clear the No Reboot (NR) bit, this enables reboots when the timer 491 * reaches the timeout for the second time. 492 */ 493 static int 494 tcotimer_disable_noreboot(device_t self) 495 { 496 struct lpcib_softc *sc = device_private(self); 497 498 if (sc->sc_has_rcba) { 499 uint32_t status; 500 501 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 502 LPCIB_GCS_OFFSET); 503 status &= ~LPCIB_GCS_NO_REBOOT; 504 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 505 LPCIB_GCS_OFFSET, status); 506 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 507 LPCIB_GCS_OFFSET); 508 if (status & LPCIB_GCS_NO_REBOOT) 509 goto error; 510 } else { 511 pcireg_t pcireg; 512 513 pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 514 LPCIB_PCI_GEN_STA); 515 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 516 /* TCO timeout reset is disabled; try to enable it */ 517 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 518 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 519 LPCIB_PCI_GEN_STA, pcireg); 520 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 521 goto error; 522 } 523 } 524 525 return 0; 526 error: 527 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 528 "hope SMBIOS properly handles it.\n"); 529 return EINVAL; 530 } 531 532 533 /* 534 * Intel ICH SpeedStep support. 535 */ 536 #define SS_READ(sc, reg) \ 537 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 538 #define SS_WRITE(sc, reg, val) \ 539 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 540 541 /* 542 * Linux driver says that SpeedStep on older chipsets cause 543 * lockups on Dell Inspiron 8000 and 8100. 544 */ 545 static int 546 speedstep_bad_hb_check(struct pci_attach_args *pa) 547 { 548 549 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 550 PCI_REVISION(pa->pa_class) < 5) 551 return 1; 552 553 return 0; 554 } 555 556 static void 557 speedstep_configure(device_t self) 558 { 559 struct lpcib_softc *sc = device_private(self); 560 const struct sysctlnode *node, *ssnode; 561 int rv; 562 563 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 564 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 565 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 566 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 567 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 568 uint8_t pmcon; 569 570 /* Enable SpeedStep if it isn't already enabled. */ 571 pmcon = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 572 LPCIB_PCI_GEN_PMCON_1); 573 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 574 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 575 LPCIB_PCI_GEN_PMCON_1, 576 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 577 578 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 579 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 580 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 581 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 582 goto err; 583 584 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 585 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 586 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 587 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 588 CTL_EOL)) != 0) 589 goto err; 590 591 /* XXX save the sc for IO tag/handle */ 592 speedstep_cookie = sc; 593 aprint_verbose_dev(self, "SpeedStep enabled\n"); 594 } 595 596 return; 597 598 err: 599 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 600 } 601 602 /* 603 * get/set the SpeedStep state: 0 == low power, 1 == high power. 604 */ 605 static int 606 speedstep_sysctl_helper(SYSCTLFN_ARGS) 607 { 608 struct sysctlnode node; 609 struct lpcib_softc *sc = speedstep_cookie; 610 uint8_t state, state2; 611 int ostate, nstate, s, error = 0; 612 613 /* 614 * We do the dance with spl's to avoid being at high ipl during 615 * sysctl_lookup() which can both copyin and copyout. 616 */ 617 s = splserial(); 618 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 619 splx(s); 620 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 621 ostate = 1; 622 else 623 ostate = 0; 624 nstate = ostate; 625 626 node = *rnode; 627 node.sysctl_data = &nstate; 628 629 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 630 if (error || newp == NULL) 631 goto out; 632 633 /* Only two states are available */ 634 if (nstate != 0 && nstate != 1) { 635 error = EINVAL; 636 goto out; 637 } 638 639 s = splserial(); 640 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 641 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 642 ostate = 1; 643 else 644 ostate = 0; 645 646 if (ostate != nstate) { 647 uint8_t cntl; 648 649 if (nstate == 0) 650 state2 |= LPCIB_PM_SS_STATE_LOW; 651 else 652 state2 &= ~LPCIB_PM_SS_STATE_LOW; 653 654 /* 655 * Must disable bus master arbitration during the change. 656 */ 657 cntl = SS_READ(sc, LPCIB_PM_CTRL); 658 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 659 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 660 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 661 } 662 splx(s); 663 out: 664 return error; 665 } 666 667 #if NHPET > 0 668 struct lpcib_hpet_attach_arg { 669 bus_space_tag_t hpet_mem_t; 670 uint32_t hpet_reg; 671 }; 672 673 static int 674 lpcib_hpet_match(device_t parent, cfdata_t match, void *aux) 675 { 676 struct lpcib_hpet_attach_arg *arg = aux; 677 bus_space_tag_t tag; 678 bus_space_handle_t handle; 679 680 tag = arg->hpet_mem_t; 681 682 if (bus_space_map(tag, arg->hpet_reg, HPET_WINDOW_SIZE, 0, &handle)) { 683 aprint_verbose_dev(parent, "HPET window not mapped, skipping\n"); 684 return 0; 685 } 686 bus_space_unmap(tag, handle, HPET_WINDOW_SIZE); 687 688 return 1; 689 } 690 691 static void 692 lpcib_hpet_attach(device_t parent, device_t self, void *aux) 693 { 694 struct hpet_softc *sc = device_private(self); 695 struct lpcib_hpet_attach_arg *arg = aux; 696 697 aprint_naive("\n"); 698 aprint_normal("\n"); 699 700 sc->sc_memt = arg->hpet_mem_t; 701 702 if (bus_space_map(sc->sc_memt, arg->hpet_reg, HPET_WINDOW_SIZE, 0, 703 &sc->sc_memh)) { 704 aprint_error_dev(self, 705 "HPET memory window could not be mapped"); 706 return; 707 } 708 709 hpet_attach_subr(self); 710 } 711 712 CFATTACH_DECL_NEW(ichlpcib_hpet, sizeof(struct hpet_softc), lpcib_hpet_match, 713 lpcib_hpet_attach, NULL, NULL); 714 715 static void 716 lpcib_hpet_configure(device_t self) 717 { 718 struct lpcib_softc *sc = device_private(self); 719 struct lpcib_hpet_attach_arg arg; 720 uint32_t hpet_reg, val; 721 722 if (sc->sc_has_ich5_hpet) { 723 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 724 LPCIB_PCI_GEN_CNTL); 725 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 726 case LPCIB_ICH5_HPTC_0000: 727 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 728 break; 729 case LPCIB_ICH5_HPTC_1000: 730 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 731 break; 732 case LPCIB_ICH5_HPTC_2000: 733 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 734 break; 735 case LPCIB_ICH5_HPTC_3000: 736 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 737 break; 738 default: 739 return; 740 } 741 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 742 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 743 LPCIB_PCI_GEN_CNTL, val); 744 } else if (sc->sc_has_rcba) { 745 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 746 LPCIB_RCBA_HPTC); 747 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 748 case LPCIB_RCBA_HPTC_0000: 749 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 750 break; 751 case LPCIB_RCBA_HPTC_1000: 752 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 753 break; 754 case LPCIB_RCBA_HPTC_2000: 755 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 756 break; 757 case LPCIB_RCBA_HPTC_3000: 758 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 759 break; 760 default: 761 return; 762 } 763 val |= LPCIB_RCBA_HPTC_EN; 764 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 765 val); 766 } else { 767 /* No HPET here */ 768 return; 769 } 770 771 arg.hpet_mem_t = sc->sc_pa.pa_memt; 772 arg.hpet_reg = hpet_reg; 773 774 config_found_ia(self, "hpetichbus", &arg, NULL); 775 } 776 #endif 777
Indexes created Tue Sep 30 17:09:57 GMT 2025