ichlpcib.c revision 1.10.2.1
1 /* $NetBSD: ichlpcib.c,v 1.10.2.1 2008/05/18 12:33:04 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.10.2.1 2008/05/18 12:33:04 yamt Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <machine/bus.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <dev/sysmon/sysmonvar.h> 57 58 #include <dev/ic/acpipmtimer.h> 59 #include <dev/ic/i82801lpcreg.h> 60 #include <dev/ic/hpetreg.h> 61 #include <dev/ic/hpetvar.h> 62 63 #include "hpet.h" 64 65 struct lpcib_softc { 66 pci_chipset_tag_t sc_pc; 67 pcitag_t sc_pcitag; 68 69 struct pci_attach_args sc_pa; 70 int sc_has_rcba; 71 int sc_has_ich5_hpet; 72 73 /* RCBA */ 74 bus_space_tag_t sc_rcbat; 75 bus_space_handle_t sc_rcbah; 76 pcireg_t sc_rcba_reg; 77 78 /* Watchdog variables. */ 79 struct sysmon_wdog sc_smw; 80 bus_space_tag_t sc_iot; 81 bus_space_handle_t sc_ioh; 82 83 #if NHPET > 0 84 /* HPET variables. */ 85 uint32_t sc_hpet_reg; 86 #endif 87 88 /* Power management */ 89 pcireg_t sc_pirq[2]; 90 pcireg_t sc_pmcon; 91 pcireg_t sc_fwhsel2; 92 }; 93 94 static int lpcibmatch(device_t, cfdata_t, void *); 95 static void lpcibattach(device_t, device_t, void *); 96 static bool lpcib_suspend(device_t PMF_FN_PROTO); 97 static bool lpcib_resume(device_t PMF_FN_PROTO); 98 99 static void pmtimer_configure(device_t); 100 101 static void tcotimer_configure(device_t); 102 static int tcotimer_setmode(struct sysmon_wdog *); 103 static int tcotimer_tickle(struct sysmon_wdog *); 104 static void tcotimer_stop(struct lpcib_softc *); 105 static void tcotimer_start(struct lpcib_softc *); 106 static void tcotimer_status_reset(struct lpcib_softc *); 107 static int tcotimer_disable_noreboot(device_t); 108 109 static void speedstep_configure(device_t); 110 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 111 112 #if NHPET > 0 113 static void lpcib_hpet_configure(device_t); 114 #endif 115 116 struct lpcib_softc *speedstep_cookie; /* XXX */ 117 118 /* Defined in arch/.../pci/pcib.c. */ 119 extern void pcibattach(device_t, device_t, void *); 120 121 CFATTACH_DECL_NEW(ichlpcib, sizeof(struct lpcib_softc), 122 lpcibmatch, lpcibattach, NULL, NULL); 123 124 static struct lpcib_device { 125 pcireg_t vendor, product; 126 int has_rcba; 127 int has_ich5_hpet; 128 } lpcib_devices[] = { 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 0, 0 }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 151 { 0, 0, 0, 0 }, 152 }; 153 154 /* 155 * Autoconf callbacks. 156 */ 157 static int 158 lpcibmatch(device_t parent, cfdata_t match, void *aux) 159 { 160 struct pci_attach_args *pa = aux; 161 struct lpcib_device *lpcib_dev; 162 163 /* We are ISA bridge, of course */ 164 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 165 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 166 return 0; 167 168 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 169 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 170 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 171 return 10; 172 } 173 174 return 0; 175 } 176 177 static void 178 lpcibattach(device_t parent, device_t self, void *aux) 179 { 180 struct pci_attach_args *pa = aux; 181 struct lpcib_softc *sc = device_private(self); 182 struct lpcib_device *lpcib_dev; 183 184 sc->sc_pc = pa->pa_pc; 185 sc->sc_pcitag = pa->pa_tag; 186 sc->sc_pa = *pa; 187 188 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 189 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 190 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 191 continue; 192 sc->sc_has_rcba = lpcib_dev->has_rcba; 193 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 194 break; 195 } 196 197 pcibattach(parent, self, aux); 198 199 /* 200 * Part of our I/O registers are used as ACPI PM regs. 201 * Since our ACPI subsystem accesses the I/O space directly so far, 202 * we do not have to bother bus_space I/O map confliction. 203 */ 204 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 205 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 206 aprint_error_dev(self, "can't map power management i/o space"); 207 return; 208 } 209 210 /* For ICH6 and later, always enable RCBA */ 211 if (sc->sc_has_rcba) { 212 pcireg_t rcba; 213 214 sc->sc_rcbat = sc->sc_pa.pa_memt; 215 216 rcba = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_RCBA); 217 if ((rcba & LPCIB_RCBA_EN) == 0) { 218 aprint_error_dev(self, "RCBA is not enabled"); 219 return; 220 } 221 rcba &= ~LPCIB_RCBA_EN; 222 223 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 224 &sc->sc_rcbah)) { 225 aprint_error_dev(self, "RCBA could not be mapped"); 226 return; 227 } 228 } 229 230 /* Set up the power management timer. */ 231 pmtimer_configure(self); 232 233 /* Set up the TCO (watchdog). */ 234 tcotimer_configure(self); 235 236 /* Set up SpeedStep. */ 237 speedstep_configure(self); 238 239 #if NHPET > 0 240 /* Set up HPET. */ 241 lpcib_hpet_configure(self); 242 #endif 243 244 /* Install power handler */ 245 if (!pmf_device_register(self, lpcib_suspend, lpcib_resume)) 246 aprint_error_dev(self, "couldn't establish power handler\n"); 247 } 248 249 static bool 250 lpcib_suspend(device_t dv PMF_FN_ARGS) 251 { 252 struct lpcib_softc *sc = device_private(dv); 253 pci_chipset_tag_t pc = sc->sc_pc; 254 pcitag_t tag = sc->sc_pcitag; 255 256 /* capture PIRQ routing control registers */ 257 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 258 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 259 260 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 261 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 262 263 if (sc->sc_has_rcba) { 264 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 265 #if NHPET > 0 266 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 267 LPCIB_RCBA_HPTC); 268 #endif 269 } else if (sc->sc_has_ich5_hpet) { 270 #if NHPET > 0 271 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 272 #endif 273 } 274 275 return true; 276 } 277 278 static bool 279 lpcib_resume(device_t dv PMF_FN_ARGS) 280 { 281 struct lpcib_softc *sc = device_private(dv); 282 pci_chipset_tag_t pc = sc->sc_pc; 283 pcitag_t tag = sc->sc_pcitag; 284 285 /* restore PIRQ routing control registers */ 286 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 287 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 288 289 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 290 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 291 292 if (sc->sc_has_rcba) { 293 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 294 #if NHPET > 0 295 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 296 sc->sc_hpet_reg); 297 #endif 298 } else if (sc->sc_has_ich5_hpet) { 299 #if NHPET > 0 300 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 301 #endif 302 } 303 304 return true; 305 } 306 307 /* 308 * Initialize the power management timer. 309 */ 310 static void 311 pmtimer_configure(device_t self) 312 { 313 struct lpcib_softc *sc = device_private(self); 314 pcireg_t control; 315 316 /* 317 * Check if power management I/O space is enabled and enable the ACPI_EN 318 * bit if it's disabled. 319 */ 320 control = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL); 321 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 322 control |= LPCIB_PCI_ACPI_CNTL_EN; 323 pci_conf_write(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL, 324 control); 325 } 326 327 /* Attach our PM timer with the generic acpipmtimer function */ 328 acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 329 LPCIB_PM1_TMR, 0); 330 } 331 332 /* 333 * Initialize the watchdog timer. 334 */ 335 static void 336 tcotimer_configure(device_t self) 337 { 338 struct lpcib_softc *sc = device_private(self); 339 uint32_t ioreg; 340 unsigned int period; 341 342 /* 343 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 344 * in the SMI_EN register is the last chance. 345 */ 346 if (tcotimer_disable_noreboot(self)) { 347 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 348 ioreg |= LPCIB_SMI_EN_TCO_EN; 349 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 350 } 351 352 /* Reset the watchdog status registers. */ 353 tcotimer_status_reset(sc); 354 355 /* Explicitly stop the TCO timer. */ 356 tcotimer_stop(sc); 357 358 /* 359 * Register the driver with the sysmon watchdog framework. 360 */ 361 sc->sc_smw.smw_name = device_xname(self); 362 sc->sc_smw.smw_cookie = sc; 363 sc->sc_smw.smw_setmode = tcotimer_setmode; 364 sc->sc_smw.smw_tickle = tcotimer_tickle; 365 if (sc->sc_has_rcba) 366 period = LPCIB_TCOTIMER2_MAX_TICK; 367 else 368 period = LPCIB_TCOTIMER_MAX_TICK; 369 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 370 371 if (sysmon_wdog_register(&sc->sc_smw)) { 372 aprint_error_dev(self, "unable to register TCO timer" 373 "as a sysmon watchdog device.\n"); 374 return; 375 } 376 377 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 378 } 379 380 /* 381 * Sysmon watchdog callbacks. 382 */ 383 static int 384 tcotimer_setmode(struct sysmon_wdog *smw) 385 { 386 struct lpcib_softc *sc = smw->smw_cookie; 387 unsigned int period; 388 uint16_t ich6period = 0; 389 390 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 391 /* Stop the TCO timer. */ 392 tcotimer_stop(sc); 393 } else { 394 /* 395 * ICH6 or newer are limited to 2s min and 613s max. 396 * ICH5 or older are limited to 4s min and 39s max. 397 */ 398 if (sc->sc_has_rcba) { 399 if (smw->smw_period < LPCIB_TCOTIMER2_MIN_TICK || 400 smw->smw_period > LPCIB_TCOTIMER2_MAX_TICK) 401 return EINVAL; 402 } else { 403 if (smw->smw_period < LPCIB_TCOTIMER_MIN_TICK || 404 smw->smw_period > LPCIB_TCOTIMER_MAX_TICK) 405 return EINVAL; 406 } 407 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 408 409 /* Stop the TCO timer, */ 410 tcotimer_stop(sc); 411 412 /* set the timeout, */ 413 if (sc->sc_has_rcba) { 414 /* ICH6 or newer */ 415 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 416 LPCIB_TCO_TMR2); 417 ich6period &= 0xfc00; 418 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 419 LPCIB_TCO_TMR2, ich6period | period); 420 } else { 421 /* ICH5 or older */ 422 period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, 423 LPCIB_TCO_TMR); 424 period &= 0xc0; 425 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 426 LPCIB_TCO_TMR, period); 427 } 428 429 /* and start/reload the timer. */ 430 tcotimer_start(sc); 431 tcotimer_tickle(smw); 432 } 433 434 return 0; 435 } 436 437 static int 438 tcotimer_tickle(struct sysmon_wdog *smw) 439 { 440 struct lpcib_softc *sc = smw->smw_cookie; 441 442 /* any value is allowed */ 443 if (sc->sc_has_rcba) 444 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 445 else 446 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 447 448 return 0; 449 } 450 451 static void 452 tcotimer_stop(struct lpcib_softc *sc) 453 { 454 uint16_t ioreg; 455 456 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 457 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 458 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 459 } 460 461 static void 462 tcotimer_start(struct lpcib_softc *sc) 463 { 464 uint16_t ioreg; 465 466 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 467 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 468 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 469 } 470 471 static void 472 tcotimer_status_reset(struct lpcib_softc *sc) 473 { 474 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 475 LPCIB_TCO1_STS_TIMEOUT); 476 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 477 LPCIB_TCO2_STS_BOOT_STS); 478 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 479 LPCIB_TCO2_STS_SECONDS_TO_STS); 480 } 481 482 /* 483 * Clear the No Reboot (NR) bit, this enables reboots when the timer 484 * reaches the timeout for the second time. 485 */ 486 static int 487 tcotimer_disable_noreboot(device_t self) 488 { 489 struct lpcib_softc *sc = device_private(self); 490 491 if (sc->sc_has_rcba) { 492 uint32_t status; 493 494 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 495 LPCIB_GCS_OFFSET); 496 status &= ~LPCIB_GCS_NO_REBOOT; 497 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 498 LPCIB_GCS_OFFSET, status); 499 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 500 LPCIB_GCS_OFFSET); 501 if (status & LPCIB_GCS_NO_REBOOT) 502 goto error; 503 } else { 504 pcireg_t pcireg; 505 506 pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 507 LPCIB_PCI_GEN_STA); 508 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 509 /* TCO timeout reset is disabled; try to enable it */ 510 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 511 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 512 LPCIB_PCI_GEN_STA, pcireg); 513 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 514 goto error; 515 } 516 } 517 518 return 0; 519 error: 520 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 521 "hope SMBIOS properly handles it.\n"); 522 return EINVAL; 523 } 524 525 526 /* 527 * Intel ICH SpeedStep support. 528 */ 529 #define SS_READ(sc, reg) \ 530 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 531 #define SS_WRITE(sc, reg, val) \ 532 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 533 534 /* 535 * Linux driver says that SpeedStep on older chipsets cause 536 * lockups on Dell Inspiron 8000 and 8100. 537 */ 538 static int 539 speedstep_bad_hb_check(struct pci_attach_args *pa) 540 { 541 542 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 543 PCI_REVISION(pa->pa_class) < 5) 544 return 1; 545 546 return 0; 547 } 548 549 static void 550 speedstep_configure(device_t self) 551 { 552 struct lpcib_softc *sc = device_private(self); 553 const struct sysctlnode *node, *ssnode; 554 int rv; 555 556 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 557 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 558 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 559 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 560 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 561 uint8_t pmcon; 562 563 /* Enable SpeedStep if it isn't already enabled. */ 564 pmcon = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 565 LPCIB_PCI_GEN_PMCON_1); 566 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 567 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 568 LPCIB_PCI_GEN_PMCON_1, 569 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 570 571 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 572 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 573 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 574 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 575 goto err; 576 577 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 578 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 579 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 580 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 581 CTL_EOL)) != 0) 582 goto err; 583 584 /* XXX save the sc for IO tag/handle */ 585 speedstep_cookie = sc; 586 aprint_verbose_dev(self, "SpeedStep enabled\n"); 587 } 588 589 return; 590 591 err: 592 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 593 } 594 595 /* 596 * get/set the SpeedStep state: 0 == low power, 1 == high power. 597 */ 598 static int 599 speedstep_sysctl_helper(SYSCTLFN_ARGS) 600 { 601 struct sysctlnode node; 602 struct lpcib_softc *sc = speedstep_cookie; 603 uint8_t state, state2; 604 int ostate, nstate, s, error = 0; 605 606 /* 607 * We do the dance with spl's to avoid being at high ipl during 608 * sysctl_lookup() which can both copyin and copyout. 609 */ 610 s = splserial(); 611 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 612 splx(s); 613 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 614 ostate = 1; 615 else 616 ostate = 0; 617 nstate = ostate; 618 619 node = *rnode; 620 node.sysctl_data = &nstate; 621 622 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 623 if (error || newp == NULL) 624 goto out; 625 626 /* Only two states are available */ 627 if (nstate != 0 && nstate != 1) { 628 error = EINVAL; 629 goto out; 630 } 631 632 s = splserial(); 633 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 634 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 635 ostate = 1; 636 else 637 ostate = 0; 638 639 if (ostate != nstate) { 640 uint8_t cntl; 641 642 if (nstate == 0) 643 state2 |= LPCIB_PM_SS_STATE_LOW; 644 else 645 state2 &= ~LPCIB_PM_SS_STATE_LOW; 646 647 /* 648 * Must disable bus master arbitration during the change. 649 */ 650 cntl = SS_READ(sc, LPCIB_PM_CTRL); 651 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 652 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 653 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 654 } 655 splx(s); 656 out: 657 return error; 658 } 659 660 #if NHPET > 0 661 struct lpcib_hpet_attach_arg { 662 bus_space_tag_t hpet_mem_t; 663 uint32_t hpet_reg; 664 }; 665 666 static int 667 lpcib_hpet_match(device_t parent, cfdata_t match, void *aux) 668 { 669 struct lpcib_hpet_attach_arg *arg = aux; 670 bus_space_tag_t tag; 671 bus_space_handle_t handle; 672 673 tag = arg->hpet_mem_t; 674 675 if (bus_space_map(tag, arg->hpet_reg, HPET_WINDOW_SIZE, 0, &handle)) { 676 aprint_verbose_dev(parent, "HPET window not mapped, skipping\n"); 677 return 0; 678 } 679 bus_space_unmap(tag, handle, HPET_WINDOW_SIZE); 680 681 return 1; 682 } 683 684 static void 685 lpcib_hpet_attach(device_t parent, device_t self, void *aux) 686 { 687 struct hpet_softc *sc = device_private(self); 688 struct lpcib_hpet_attach_arg *arg = aux; 689 690 aprint_naive("\n"); 691 aprint_normal("\n"); 692 693 sc->sc_memt = arg->hpet_mem_t; 694 695 if (bus_space_map(sc->sc_memt, arg->hpet_reg, HPET_WINDOW_SIZE, 0, 696 &sc->sc_memh)) { 697 aprint_error_dev(self, 698 "HPET memory window could not be mapped"); 699 return; 700 } 701 702 hpet_attach_subr(self); 703 } 704 705 CFATTACH_DECL_NEW(ichlpcib_hpet, sizeof(struct hpet_softc), lpcib_hpet_match, 706 lpcib_hpet_attach, NULL, NULL); 707 708 static void 709 lpcib_hpet_configure(device_t self) 710 { 711 struct lpcib_softc *sc = device_private(self); 712 struct lpcib_hpet_attach_arg arg; 713 uint32_t hpet_reg, val; 714 715 if (sc->sc_has_ich5_hpet) { 716 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 717 LPCIB_PCI_GEN_CNTL); 718 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 719 case LPCIB_ICH5_HPTC_0000: 720 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 721 break; 722 case LPCIB_ICH5_HPTC_1000: 723 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 724 break; 725 case LPCIB_ICH5_HPTC_2000: 726 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 727 break; 728 case LPCIB_ICH5_HPTC_3000: 729 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 730 break; 731 default: 732 return; 733 } 734 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 735 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 736 LPCIB_PCI_GEN_CNTL, val); 737 } else if (sc->sc_has_rcba) { 738 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 739 LPCIB_RCBA_HPTC); 740 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 741 case LPCIB_RCBA_HPTC_0000: 742 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 743 break; 744 case LPCIB_RCBA_HPTC_1000: 745 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 746 break; 747 case LPCIB_RCBA_HPTC_2000: 748 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 749 break; 750 case LPCIB_RCBA_HPTC_3000: 751 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 752 break; 753 default: 754 return; 755 } 756 val |= LPCIB_RCBA_HPTC_EN; 757 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 758 val); 759 } else { 760 /* No HPET here */ 761 return; 762 } 763 764 arg.hpet_mem_t = sc->sc_pa.pa_memt; 765 arg.hpet_reg = hpet_reg; 766 767 config_found_ia(self, "hpetichbus", &arg, NULL); 768 } 769 #endif 770
Indexes created Wed Oct 01 18:09:54 GMT 2025