ichlpcib.c revision 1.10.4.3
1 /* $NetBSD: ichlpcib.c,v 1.10.4.3 2009/08/19 18:46:50 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.10.4.3 2009/08/19 18:46:50 yamt Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <machine/bus.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <dev/sysmon/sysmonvar.h> 57 58 #include <dev/ic/acpipmtimer.h> 59 #include <dev/ic/i82801lpcreg.h> 60 #include <dev/ic/hpetreg.h> 61 #include <dev/ic/hpetvar.h> 62 63 #include "hpet.h" 64 #include "pcibvar.h" 65 66 struct lpcib_softc { 67 /* we call pcibattach() which assumes this starts like this: */ 68 struct pcib_softc sc_pcib; 69 70 struct pci_attach_args sc_pa; 71 int sc_has_rcba; 72 int sc_has_ich5_hpet; 73 74 /* RCBA */ 75 bus_space_tag_t sc_rcbat; 76 bus_space_handle_t sc_rcbah; 77 pcireg_t sc_rcba_reg; 78 79 /* Watchdog variables. */ 80 struct sysmon_wdog sc_smw; 81 bus_space_tag_t sc_iot; 82 bus_space_handle_t sc_ioh; 83 bus_size_t sc_iosize; 84 85 #if NHPET > 0 86 /* HPET variables. */ 87 uint32_t sc_hpet_reg; 88 #endif 89 90 /* Speedstep */ 91 pcireg_t sc_pmcon_orig; 92 93 /* Power management */ 94 pcireg_t sc_pirq[2]; 95 pcireg_t sc_pmcon; 96 pcireg_t sc_fwhsel2; 97 98 /* Child devices */ 99 device_t sc_hpetbus; 100 acpipmtimer_t sc_pmtimer; 101 pcireg_t sc_acpi_cntl; 102 103 struct sysctllog *sc_log; 104 }; 105 106 static int lpcibmatch(device_t, cfdata_t, void *); 107 static void lpcibattach(device_t, device_t, void *); 108 static int lpcibdetach(device_t, int); 109 static void lpcibchilddet(device_t, device_t); 110 static int lpcibrescan(device_t, const char *, const int *); 111 static bool lpcib_suspend(device_t PMF_FN_PROTO); 112 static bool lpcib_resume(device_t PMF_FN_PROTO); 113 static bool lpcib_shutdown(device_t, int); 114 115 static void pmtimer_configure(device_t); 116 static int pmtimer_unconfigure(device_t, int); 117 118 static void tcotimer_configure(device_t); 119 static int tcotimer_unconfigure(device_t, int); 120 static int tcotimer_setmode(struct sysmon_wdog *); 121 static int tcotimer_tickle(struct sysmon_wdog *); 122 static void tcotimer_stop(struct lpcib_softc *); 123 static void tcotimer_start(struct lpcib_softc *); 124 static void tcotimer_status_reset(struct lpcib_softc *); 125 static int tcotimer_disable_noreboot(device_t); 126 127 static void speedstep_configure(device_t); 128 static void speedstep_unconfigure(device_t); 129 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 130 131 #if NHPET > 0 132 static void lpcib_hpet_configure(device_t); 133 static int lpcib_hpet_unconfigure(device_t, int); 134 #endif 135 136 struct lpcib_softc *speedstep_cookie; /* XXX */ 137 138 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 139 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 140 141 static struct lpcib_device { 142 pcireg_t vendor, product; 143 int has_rcba; 144 int has_ich5_hpet; 145 } lpcib_devices[] = { 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 0, 0 }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 158 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 161 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 162 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 163 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 164 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 165 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 166 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 167 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 168 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 169 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 170 171 { 0, 0, 0, 0 }, 172 }; 173 174 /* 175 * Autoconf callbacks. 176 */ 177 static int 178 lpcibmatch(device_t parent, cfdata_t match, void *aux) 179 { 180 struct pci_attach_args *pa = aux; 181 struct lpcib_device *lpcib_dev; 182 183 /* We are ISA bridge, of course */ 184 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 185 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 186 return 0; 187 188 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 189 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 190 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 191 return 10; 192 } 193 194 return 0; 195 } 196 197 static void 198 lpcibattach(device_t parent, device_t self, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 struct lpcib_softc *sc = device_private(self); 202 struct lpcib_device *lpcib_dev; 203 204 sc->sc_pa = *pa; 205 206 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 207 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 208 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 209 continue; 210 sc->sc_has_rcba = lpcib_dev->has_rcba; 211 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 212 break; 213 } 214 215 pcibattach(parent, self, aux); 216 217 /* 218 * Part of our I/O registers are used as ACPI PM regs. 219 * Since our ACPI subsystem accesses the I/O space directly so far, 220 * we do not have to bother bus_space I/O map confliction. 221 */ 222 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 223 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_iosize)) { 224 aprint_error_dev(self, "can't map power management i/o space"); 225 return; 226 } 227 228 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 229 LPCIB_PCI_GEN_PMCON_1); 230 231 /* For ICH6 and later, always enable RCBA */ 232 if (sc->sc_has_rcba) { 233 pcireg_t rcba; 234 235 sc->sc_rcbat = sc->sc_pa.pa_memt; 236 237 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 238 LPCIB_RCBA); 239 if ((rcba & LPCIB_RCBA_EN) == 0) { 240 aprint_error_dev(self, "RCBA is not enabled"); 241 return; 242 } 243 rcba &= ~LPCIB_RCBA_EN; 244 245 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 246 &sc->sc_rcbah)) { 247 aprint_error_dev(self, "RCBA could not be mapped"); 248 return; 249 } 250 } 251 252 /* Set up the power management timer. */ 253 pmtimer_configure(self); 254 255 /* Set up the TCO (watchdog). */ 256 tcotimer_configure(self); 257 258 /* Set up SpeedStep. */ 259 speedstep_configure(self); 260 261 #if NHPET > 0 262 /* Set up HPET. */ 263 lpcib_hpet_configure(self); 264 #endif 265 266 /* Install power handler */ 267 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 268 lpcib_shutdown)) 269 aprint_error_dev(self, "couldn't establish power handler\n"); 270 } 271 272 static void 273 lpcibchilddet(device_t self, device_t child) 274 { 275 struct lpcib_softc *sc = device_private(self); 276 uint32_t val; 277 278 if (sc->sc_hpetbus != child) { 279 pcibchilddet(self, child); 280 return; 281 } 282 sc->sc_hpetbus = NULL; 283 if (sc->sc_has_ich5_hpet) { 284 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 285 LPCIB_PCI_GEN_CNTL); 286 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 287 case LPCIB_ICH5_HPTC_0000: 288 case LPCIB_ICH5_HPTC_1000: 289 case LPCIB_ICH5_HPTC_2000: 290 case LPCIB_ICH5_HPTC_3000: 291 break; 292 default: 293 return; 294 } 295 val &= ~LPCIB_ICH5_HPTC_EN; 296 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 297 LPCIB_PCI_GEN_CNTL, val); 298 } else if (sc->sc_has_rcba) { 299 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 300 LPCIB_RCBA_HPTC); 301 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 302 case LPCIB_RCBA_HPTC_0000: 303 case LPCIB_RCBA_HPTC_1000: 304 case LPCIB_RCBA_HPTC_2000: 305 case LPCIB_RCBA_HPTC_3000: 306 break; 307 default: 308 return; 309 } 310 val &= ~LPCIB_RCBA_HPTC_EN; 311 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 312 val); 313 } 314 } 315 316 #if NHPET > 0 317 /* XXX share this with sys/arch/i386/pci/elan520.c */ 318 static bool 319 ifattr_match(const char *snull, const char *t) 320 { 321 return (snull == NULL) || strcmp(snull, t) == 0; 322 } 323 #endif 324 325 static int 326 lpcibrescan(device_t self, const char *ifattr, const int *locators) 327 { 328 #if NHPET > 0 329 struct lpcib_softc *sc = device_private(self); 330 331 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 332 lpcib_hpet_configure(self); 333 #endif 334 335 return pcibrescan(self, ifattr, locators); 336 } 337 338 static int 339 lpcibdetach(device_t self, int flags) 340 { 341 struct lpcib_softc *sc = device_private(self); 342 int rc; 343 344 pmf_device_deregister(self); 345 346 #if NHPET > 0 347 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 348 return rc; 349 #endif 350 351 /* Set up SpeedStep. */ 352 speedstep_unconfigure(self); 353 354 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 355 return rc; 356 357 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 358 return rc; 359 360 if (sc->sc_has_rcba) 361 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 362 363 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 364 365 return pcibdetach(self, flags); 366 } 367 368 static bool 369 lpcib_shutdown(device_t dv, int howto) 370 { 371 struct lpcib_softc *sc = device_private(dv); 372 373 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 374 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 375 376 return true; 377 } 378 379 static bool 380 lpcib_suspend(device_t dv PMF_FN_ARGS) 381 { 382 struct lpcib_softc *sc = device_private(dv); 383 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 384 pcitag_t tag = sc->sc_pcib.sc_tag; 385 386 /* capture PIRQ routing control registers */ 387 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 388 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 389 390 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 391 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 392 393 if (sc->sc_has_rcba) { 394 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 395 #if NHPET > 0 396 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 397 LPCIB_RCBA_HPTC); 398 #endif 399 } else if (sc->sc_has_ich5_hpet) { 400 #if NHPET > 0 401 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 402 #endif 403 } 404 405 return true; 406 } 407 408 static bool 409 lpcib_resume(device_t dv PMF_FN_ARGS) 410 { 411 struct lpcib_softc *sc = device_private(dv); 412 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 413 pcitag_t tag = sc->sc_pcib.sc_tag; 414 415 /* restore PIRQ routing control registers */ 416 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 417 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 418 419 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 420 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 421 422 if (sc->sc_has_rcba) { 423 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 424 #if NHPET > 0 425 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 426 sc->sc_hpet_reg); 427 #endif 428 } else if (sc->sc_has_ich5_hpet) { 429 #if NHPET > 0 430 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 431 #endif 432 } 433 434 return true; 435 } 436 437 /* 438 * Initialize the power management timer. 439 */ 440 static void 441 pmtimer_configure(device_t self) 442 { 443 struct lpcib_softc *sc = device_private(self); 444 pcireg_t control; 445 446 /* 447 * Check if power management I/O space is enabled and enable the ACPI_EN 448 * bit if it's disabled. 449 */ 450 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 451 LPCIB_PCI_ACPI_CNTL); 452 sc->sc_acpi_cntl = control; 453 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 454 control |= LPCIB_PCI_ACPI_CNTL_EN; 455 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 456 LPCIB_PCI_ACPI_CNTL, control); 457 } 458 459 /* Attach our PM timer with the generic acpipmtimer function */ 460 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 461 LPCIB_PM1_TMR, 0); 462 } 463 464 static int 465 pmtimer_unconfigure(device_t self, int flags) 466 { 467 struct lpcib_softc *sc = device_private(self); 468 int rc; 469 470 if (sc->sc_pmtimer != NULL && 471 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 472 return rc; 473 474 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 475 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 476 477 return 0; 478 } 479 480 /* 481 * Initialize the watchdog timer. 482 */ 483 static void 484 tcotimer_configure(device_t self) 485 { 486 struct lpcib_softc *sc = device_private(self); 487 uint32_t ioreg; 488 unsigned int period; 489 490 /* Explicitly stop the TCO timer. */ 491 tcotimer_stop(sc); 492 493 /* 494 * Enable TCO timeout SMI only if the hardware reset does not 495 * work. We don't know what the SMBIOS does. 496 */ 497 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 498 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 499 500 /* 501 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 502 * in the SMI_EN register is the last chance. 503 */ 504 if (tcotimer_disable_noreboot(self)) { 505 ioreg |= LPCIB_SMI_EN_TCO_EN; 506 } 507 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 508 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 509 } 510 511 /* Reset the watchdog status registers. */ 512 tcotimer_status_reset(sc); 513 514 /* 515 * Register the driver with the sysmon watchdog framework. 516 */ 517 sc->sc_smw.smw_name = device_xname(self); 518 sc->sc_smw.smw_cookie = sc; 519 sc->sc_smw.smw_setmode = tcotimer_setmode; 520 sc->sc_smw.smw_tickle = tcotimer_tickle; 521 if (sc->sc_has_rcba) 522 period = LPCIB_TCOTIMER2_MAX_TICK; 523 else 524 period = LPCIB_TCOTIMER_MAX_TICK; 525 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 526 527 if (sysmon_wdog_register(&sc->sc_smw)) { 528 aprint_error_dev(self, "unable to register TCO timer" 529 "as a sysmon watchdog device.\n"); 530 return; 531 } 532 533 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 534 } 535 536 static int 537 tcotimer_unconfigure(device_t self, int flags) 538 { 539 struct lpcib_softc *sc = device_private(self); 540 int rc; 541 542 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 543 if (rc == ERESTART) 544 rc = EINTR; 545 return rc; 546 } 547 548 /* Explicitly stop the TCO timer. */ 549 tcotimer_stop(sc); 550 551 /* XXX Set No Reboot? */ 552 553 return 0; 554 } 555 556 557 /* 558 * Sysmon watchdog callbacks. 559 */ 560 static int 561 tcotimer_setmode(struct sysmon_wdog *smw) 562 { 563 struct lpcib_softc *sc = smw->smw_cookie; 564 unsigned int period; 565 uint16_t ich6period = 0; 566 uint8_t ich5period = 0; 567 568 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 569 /* Stop the TCO timer. */ 570 tcotimer_stop(sc); 571 } else { 572 /* 573 * ICH6 or newer are limited to 2s min and 613s max. 574 * ICH5 or older are limited to 4s min and 39s max. 575 */ 576 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 577 if (sc->sc_has_rcba) { 578 if (period < LPCIB_TCOTIMER2_MIN_TICK || 579 period > LPCIB_TCOTIMER2_MAX_TICK) 580 return EINVAL; 581 } else { 582 if (period < LPCIB_TCOTIMER_MIN_TICK || 583 period > LPCIB_TCOTIMER_MAX_TICK) 584 return EINVAL; 585 } 586 587 /* Stop the TCO timer, */ 588 tcotimer_stop(sc); 589 590 /* set the timeout, */ 591 if (sc->sc_has_rcba) { 592 /* ICH6 or newer */ 593 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 594 LPCIB_TCO_TMR2); 595 ich6period &= 0xfc00; 596 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 597 LPCIB_TCO_TMR2, ich6period | period); 598 } else { 599 /* ICH5 or older */ 600 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 601 LPCIB_TCO_TMR); 602 ich5period &= 0xc0; 603 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 604 LPCIB_TCO_TMR, ich5period | period); 605 } 606 607 /* and start/reload the timer. */ 608 tcotimer_start(sc); 609 tcotimer_tickle(smw); 610 } 611 612 return 0; 613 } 614 615 static int 616 tcotimer_tickle(struct sysmon_wdog *smw) 617 { 618 struct lpcib_softc *sc = smw->smw_cookie; 619 620 /* any value is allowed */ 621 if (sc->sc_has_rcba) 622 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 623 else 624 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 625 626 return 0; 627 } 628 629 static void 630 tcotimer_stop(struct lpcib_softc *sc) 631 { 632 uint16_t ioreg; 633 634 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 635 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 636 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 637 } 638 639 static void 640 tcotimer_start(struct lpcib_softc *sc) 641 { 642 uint16_t ioreg; 643 644 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 645 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 646 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 647 } 648 649 static void 650 tcotimer_status_reset(struct lpcib_softc *sc) 651 { 652 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 653 LPCIB_TCO1_STS_TIMEOUT); 654 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 655 LPCIB_TCO2_STS_BOOT_STS); 656 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 657 LPCIB_TCO2_STS_SECONDS_TO_STS); 658 } 659 660 /* 661 * Clear the No Reboot (NR) bit, this enables reboots when the timer 662 * reaches the timeout for the second time. 663 */ 664 static int 665 tcotimer_disable_noreboot(device_t self) 666 { 667 struct lpcib_softc *sc = device_private(self); 668 669 if (sc->sc_has_rcba) { 670 uint32_t status; 671 672 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 673 LPCIB_GCS_OFFSET); 674 status &= ~LPCIB_GCS_NO_REBOOT; 675 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 676 LPCIB_GCS_OFFSET, status); 677 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 678 LPCIB_GCS_OFFSET); 679 if (status & LPCIB_GCS_NO_REBOOT) 680 goto error; 681 } else { 682 pcireg_t pcireg; 683 684 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 685 LPCIB_PCI_GEN_STA); 686 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 687 /* TCO timeout reset is disabled; try to enable it */ 688 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 689 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 690 LPCIB_PCI_GEN_STA, pcireg); 691 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 692 goto error; 693 } 694 } 695 696 return 0; 697 error: 698 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 699 "hope SMBIOS properly handles it.\n"); 700 return EINVAL; 701 } 702 703 704 /* 705 * Intel ICH SpeedStep support. 706 */ 707 #define SS_READ(sc, reg) \ 708 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 709 #define SS_WRITE(sc, reg, val) \ 710 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 711 712 /* 713 * Linux driver says that SpeedStep on older chipsets cause 714 * lockups on Dell Inspiron 8000 and 8100. 715 * It should also not be enabled on systems with the 82855GM 716 * Hub, which typically have an EST-enabled CPU. 717 */ 718 static int 719 speedstep_bad_hb_check(struct pci_attach_args *pa) 720 { 721 722 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 723 PCI_REVISION(pa->pa_class) < 5) 724 return 1; 725 726 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 727 return 1; 728 729 return 0; 730 } 731 732 static void 733 speedstep_configure(device_t self) 734 { 735 struct lpcib_softc *sc = device_private(self); 736 const struct sysctlnode *node, *ssnode; 737 int rv; 738 739 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 740 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 741 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 742 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 743 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 744 pcireg_t pmcon; 745 746 /* Enable SpeedStep if it isn't already enabled. */ 747 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 748 LPCIB_PCI_GEN_PMCON_1); 749 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 750 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 751 LPCIB_PCI_GEN_PMCON_1, 752 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 753 754 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 755 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 756 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 757 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 758 goto err; 759 760 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 761 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 762 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 763 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 764 CTL_EOL)) != 0) 765 goto err; 766 767 /* XXX save the sc for IO tag/handle */ 768 speedstep_cookie = sc; 769 aprint_verbose_dev(self, "SpeedStep enabled\n"); 770 } 771 772 return; 773 774 err: 775 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 776 } 777 778 static void 779 speedstep_unconfigure(device_t self) 780 { 781 struct lpcib_softc *sc = device_private(self); 782 783 sysctl_teardown(&sc->sc_log); 784 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 785 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 786 787 speedstep_cookie = NULL; 788 } 789 790 /* 791 * get/set the SpeedStep state: 0 == low power, 1 == high power. 792 */ 793 static int 794 speedstep_sysctl_helper(SYSCTLFN_ARGS) 795 { 796 struct sysctlnode node; 797 struct lpcib_softc *sc = speedstep_cookie; 798 uint8_t state, state2; 799 int ostate, nstate, s, error = 0; 800 801 /* 802 * We do the dance with spl's to avoid being at high ipl during 803 * sysctl_lookup() which can both copyin and copyout. 804 */ 805 s = splserial(); 806 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 807 splx(s); 808 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 809 ostate = 1; 810 else 811 ostate = 0; 812 nstate = ostate; 813 814 node = *rnode; 815 node.sysctl_data = &nstate; 816 817 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 818 if (error || newp == NULL) 819 goto out; 820 821 /* Only two states are available */ 822 if (nstate != 0 && nstate != 1) { 823 error = EINVAL; 824 goto out; 825 } 826 827 s = splserial(); 828 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 829 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 830 ostate = 1; 831 else 832 ostate = 0; 833 834 if (ostate != nstate) { 835 uint8_t cntl; 836 837 if (nstate == 0) 838 state2 |= LPCIB_PM_SS_STATE_LOW; 839 else 840 state2 &= ~LPCIB_PM_SS_STATE_LOW; 841 842 /* 843 * Must disable bus master arbitration during the change. 844 */ 845 cntl = SS_READ(sc, LPCIB_PM_CTRL); 846 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 847 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 848 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 849 } 850 splx(s); 851 out: 852 return error; 853 } 854 855 #if NHPET > 0 856 struct lpcib_hpet_attach_arg { 857 bus_space_tag_t hpet_mem_t; 858 uint32_t hpet_reg; 859 }; 860 861 static int 862 lpcib_hpet_match(device_t parent, cfdata_t match, void *aux) 863 { 864 struct lpcib_hpet_attach_arg *arg = aux; 865 bus_space_tag_t tag; 866 bus_space_handle_t handle; 867 868 tag = arg->hpet_mem_t; 869 870 if (bus_space_map(tag, arg->hpet_reg, HPET_WINDOW_SIZE, 0, &handle)) { 871 aprint_verbose_dev(parent, "HPET window not mapped, skipping\n"); 872 return 0; 873 } 874 bus_space_unmap(tag, handle, HPET_WINDOW_SIZE); 875 876 return 1; 877 } 878 879 static int 880 lpcib_hpet_detach(device_t self, int flags) 881 { 882 struct hpet_softc *sc = device_private(self); 883 int rc; 884 885 if ((rc = hpet_detach(self, flags)) != 0) 886 return rc; 887 888 bus_space_unmap(sc->sc_memt, sc->sc_memh, HPET_WINDOW_SIZE); 889 890 return 0; 891 } 892 893 static void 894 lpcib_hpet_attach(device_t parent, device_t self, void *aux) 895 { 896 struct hpet_softc *sc = device_private(self); 897 struct lpcib_hpet_attach_arg *arg = aux; 898 899 aprint_naive("\n"); 900 aprint_normal("\n"); 901 902 sc->sc_memt = arg->hpet_mem_t; 903 904 if (bus_space_map(sc->sc_memt, arg->hpet_reg, HPET_WINDOW_SIZE, 0, 905 &sc->sc_memh)) { 906 aprint_error_dev(self, 907 "HPET memory window could not be mapped"); 908 return; 909 } 910 911 hpet_attach_subr(self); 912 } 913 914 CFATTACH_DECL_NEW(ichlpcib_hpet, sizeof(struct hpet_softc), lpcib_hpet_match, 915 lpcib_hpet_attach, lpcib_hpet_detach, NULL); 916 917 static void 918 lpcib_hpet_configure(device_t self) 919 { 920 struct lpcib_softc *sc = device_private(self); 921 struct lpcib_hpet_attach_arg arg; 922 uint32_t hpet_reg, val; 923 924 if (sc->sc_has_ich5_hpet) { 925 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 926 LPCIB_PCI_GEN_CNTL); 927 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 928 case LPCIB_ICH5_HPTC_0000: 929 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 930 break; 931 case LPCIB_ICH5_HPTC_1000: 932 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 933 break; 934 case LPCIB_ICH5_HPTC_2000: 935 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 936 break; 937 case LPCIB_ICH5_HPTC_3000: 938 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 939 break; 940 default: 941 return; 942 } 943 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 944 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 945 LPCIB_PCI_GEN_CNTL, val); 946 } else if (sc->sc_has_rcba) { 947 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 948 LPCIB_RCBA_HPTC); 949 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 950 case LPCIB_RCBA_HPTC_0000: 951 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 952 break; 953 case LPCIB_RCBA_HPTC_1000: 954 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 955 break; 956 case LPCIB_RCBA_HPTC_2000: 957 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 958 break; 959 case LPCIB_RCBA_HPTC_3000: 960 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 961 break; 962 default: 963 return; 964 } 965 val |= LPCIB_RCBA_HPTC_EN; 966 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 967 val); 968 } else { 969 /* No HPET here */ 970 return; 971 } 972 973 arg.hpet_mem_t = sc->sc_pa.pa_memt; 974 arg.hpet_reg = hpet_reg; 975 976 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 977 } 978 979 static int 980 lpcib_hpet_unconfigure(device_t self, int flags) 981 { 982 struct lpcib_softc *sc = device_private(self); 983 int rc; 984 985 if (sc->sc_hpetbus != NULL && 986 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 987 return rc; 988 989 return 0; 990 } 991 #endif 992
Indexes created Wed Oct 01 18:09:54 GMT 2025