ichlpcib.c revision 1.14.2.1
1 /* $NetBSD: ichlpcib.c,v 1.14.2.1 2009/03/03 18:29:37 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.14.2.1 2009/03/03 18:29:37 skrll Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <machine/bus.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <dev/sysmon/sysmonvar.h> 57 58 #include <dev/ic/acpipmtimer.h> 59 #include <dev/ic/i82801lpcreg.h> 60 #include <dev/ic/hpetreg.h> 61 #include <dev/ic/hpetvar.h> 62 63 #include "hpet.h" 64 #include "pcibvar.h" 65 66 struct lpcib_softc { 67 /* we call pcibattach() which assumes this starts like this: */ 68 struct pcib_softc sc_pcib; 69 70 struct pci_attach_args sc_pa; 71 int sc_has_rcba; 72 int sc_has_ich5_hpet; 73 74 /* RCBA */ 75 bus_space_tag_t sc_rcbat; 76 bus_space_handle_t sc_rcbah; 77 pcireg_t sc_rcba_reg; 78 79 /* Watchdog variables. */ 80 struct sysmon_wdog sc_smw; 81 bus_space_tag_t sc_iot; 82 bus_space_handle_t sc_ioh; 83 84 #if NHPET > 0 85 /* HPET variables. */ 86 uint32_t sc_hpet_reg; 87 #endif 88 89 /* Power management */ 90 pcireg_t sc_pirq[2]; 91 pcireg_t sc_pmcon; 92 pcireg_t sc_fwhsel2; 93 }; 94 95 static int lpcibmatch(device_t, cfdata_t, void *); 96 static void lpcibattach(device_t, device_t, void *); 97 static bool lpcib_suspend(device_t PMF_FN_PROTO); 98 static bool lpcib_resume(device_t PMF_FN_PROTO); 99 100 static void pmtimer_configure(device_t); 101 102 static void tcotimer_configure(device_t); 103 static int tcotimer_setmode(struct sysmon_wdog *); 104 static int tcotimer_tickle(struct sysmon_wdog *); 105 static void tcotimer_stop(struct lpcib_softc *); 106 static void tcotimer_start(struct lpcib_softc *); 107 static void tcotimer_status_reset(struct lpcib_softc *); 108 static int tcotimer_disable_noreboot(device_t); 109 110 static void speedstep_configure(device_t); 111 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 112 113 #if NHPET > 0 114 static void lpcib_hpet_configure(device_t); 115 #endif 116 117 struct lpcib_softc *speedstep_cookie; /* XXX */ 118 119 CFATTACH_DECL_NEW(ichlpcib, sizeof(struct lpcib_softc), 120 lpcibmatch, lpcibattach, NULL, NULL); 121 122 static struct lpcib_device { 123 pcireg_t vendor, product; 124 int has_rcba; 125 int has_ich5_hpet; 126 } lpcib_devices[] = { 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 0, 0 }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 150 151 { 0, 0, 0, 0 }, 152 }; 153 154 /* 155 * Autoconf callbacks. 156 */ 157 static int 158 lpcibmatch(device_t parent, cfdata_t match, void *aux) 159 { 160 struct pci_attach_args *pa = aux; 161 struct lpcib_device *lpcib_dev; 162 163 /* We are ISA bridge, of course */ 164 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 165 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 166 return 0; 167 168 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 169 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 170 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 171 return 10; 172 } 173 174 return 0; 175 } 176 177 static void 178 lpcibattach(device_t parent, device_t self, void *aux) 179 { 180 struct pci_attach_args *pa = aux; 181 struct lpcib_softc *sc = device_private(self); 182 struct lpcib_device *lpcib_dev; 183 184 sc->sc_pa = *pa; 185 186 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 187 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 188 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 189 continue; 190 sc->sc_has_rcba = lpcib_dev->has_rcba; 191 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 192 break; 193 } 194 195 pcibattach(parent, self, aux); 196 197 /* 198 * Part of our I/O registers are used as ACPI PM regs. 199 * Since our ACPI subsystem accesses the I/O space directly so far, 200 * we do not have to bother bus_space I/O map confliction. 201 */ 202 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 203 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 204 aprint_error_dev(self, "can't map power management i/o space"); 205 return; 206 } 207 208 /* For ICH6 and later, always enable RCBA */ 209 if (sc->sc_has_rcba) { 210 pcireg_t rcba; 211 212 sc->sc_rcbat = sc->sc_pa.pa_memt; 213 214 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 215 LPCIB_RCBA); 216 if ((rcba & LPCIB_RCBA_EN) == 0) { 217 aprint_error_dev(self, "RCBA is not enabled"); 218 return; 219 } 220 rcba &= ~LPCIB_RCBA_EN; 221 222 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 223 &sc->sc_rcbah)) { 224 aprint_error_dev(self, "RCBA could not be mapped"); 225 return; 226 } 227 } 228 229 /* Set up the power management timer. */ 230 pmtimer_configure(self); 231 232 /* Set up the TCO (watchdog). */ 233 tcotimer_configure(self); 234 235 /* Set up SpeedStep. */ 236 speedstep_configure(self); 237 238 #if NHPET > 0 239 /* Set up HPET. */ 240 lpcib_hpet_configure(self); 241 #endif 242 243 /* Install power handler */ 244 if (!pmf_device_register(self, lpcib_suspend, lpcib_resume)) 245 aprint_error_dev(self, "couldn't establish power handler\n"); 246 } 247 248 static bool 249 lpcib_suspend(device_t dv PMF_FN_ARGS) 250 { 251 struct lpcib_softc *sc = device_private(dv); 252 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 253 pcitag_t tag = sc->sc_pcib.sc_tag; 254 255 /* capture PIRQ routing control registers */ 256 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 257 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 258 259 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 260 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 261 262 if (sc->sc_has_rcba) { 263 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 264 #if NHPET > 0 265 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 266 LPCIB_RCBA_HPTC); 267 #endif 268 } else if (sc->sc_has_ich5_hpet) { 269 #if NHPET > 0 270 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 271 #endif 272 } 273 274 return true; 275 } 276 277 static bool 278 lpcib_resume(device_t dv PMF_FN_ARGS) 279 { 280 struct lpcib_softc *sc = device_private(dv); 281 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 282 pcitag_t tag = sc->sc_pcib.sc_tag; 283 284 /* restore PIRQ routing control registers */ 285 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 286 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 287 288 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 289 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 290 291 if (sc->sc_has_rcba) { 292 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 293 #if NHPET > 0 294 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 295 sc->sc_hpet_reg); 296 #endif 297 } else if (sc->sc_has_ich5_hpet) { 298 #if NHPET > 0 299 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 300 #endif 301 } 302 303 return true; 304 } 305 306 /* 307 * Initialize the power management timer. 308 */ 309 static void 310 pmtimer_configure(device_t self) 311 { 312 struct lpcib_softc *sc = device_private(self); 313 pcireg_t control; 314 315 /* 316 * Check if power management I/O space is enabled and enable the ACPI_EN 317 * bit if it's disabled. 318 */ 319 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 320 LPCIB_PCI_ACPI_CNTL); 321 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 322 control |= LPCIB_PCI_ACPI_CNTL_EN; 323 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 324 LPCIB_PCI_ACPI_CNTL, control); 325 } 326 327 /* Attach our PM timer with the generic acpipmtimer function */ 328 acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 329 LPCIB_PM1_TMR, 0); 330 } 331 332 /* 333 * Initialize the watchdog timer. 334 */ 335 static void 336 tcotimer_configure(device_t self) 337 { 338 struct lpcib_softc *sc = device_private(self); 339 uint32_t ioreg; 340 unsigned int period; 341 342 /* Explicitly stop the TCO timer. */ 343 tcotimer_stop(sc); 344 345 /* 346 * Enable TCO timeout SMI only if the hardware reset does not 347 * work. We don't know what the SMBIOS does. 348 */ 349 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 350 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 351 352 /* 353 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 354 * in the SMI_EN register is the last chance. 355 */ 356 if (tcotimer_disable_noreboot(self)) { 357 ioreg |= LPCIB_SMI_EN_TCO_EN; 358 } 359 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 360 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 361 } 362 363 /* Reset the watchdog status registers. */ 364 tcotimer_status_reset(sc); 365 366 /* 367 * Register the driver with the sysmon watchdog framework. 368 */ 369 sc->sc_smw.smw_name = device_xname(self); 370 sc->sc_smw.smw_cookie = sc; 371 sc->sc_smw.smw_setmode = tcotimer_setmode; 372 sc->sc_smw.smw_tickle = tcotimer_tickle; 373 if (sc->sc_has_rcba) 374 period = LPCIB_TCOTIMER2_MAX_TICK; 375 else 376 period = LPCIB_TCOTIMER_MAX_TICK; 377 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 378 379 if (sysmon_wdog_register(&sc->sc_smw)) { 380 aprint_error_dev(self, "unable to register TCO timer" 381 "as a sysmon watchdog device.\n"); 382 return; 383 } 384 385 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 386 } 387 388 /* 389 * Sysmon watchdog callbacks. 390 */ 391 static int 392 tcotimer_setmode(struct sysmon_wdog *smw) 393 { 394 struct lpcib_softc *sc = smw->smw_cookie; 395 unsigned int period; 396 uint16_t ich6period = 0; 397 398 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 399 /* Stop the TCO timer. */ 400 tcotimer_stop(sc); 401 } else { 402 /* 403 * ICH6 or newer are limited to 2s min and 613s max. 404 * ICH5 or older are limited to 4s min and 39s max. 405 */ 406 if (sc->sc_has_rcba) { 407 if (smw->smw_period < LPCIB_TCOTIMER2_MIN_TICK || 408 smw->smw_period > LPCIB_TCOTIMER2_MAX_TICK) 409 return EINVAL; 410 } else { 411 if (smw->smw_period < LPCIB_TCOTIMER_MIN_TICK || 412 smw->smw_period > LPCIB_TCOTIMER_MAX_TICK) 413 return EINVAL; 414 } 415 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 416 417 /* Stop the TCO timer, */ 418 tcotimer_stop(sc); 419 420 /* set the timeout, */ 421 if (sc->sc_has_rcba) { 422 /* ICH6 or newer */ 423 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 424 LPCIB_TCO_TMR2); 425 ich6period &= 0xfc00; 426 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 427 LPCIB_TCO_TMR2, ich6period | period); 428 } else { 429 /* ICH5 or older */ 430 period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, 431 LPCIB_TCO_TMR); 432 period &= 0xc0; 433 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 434 LPCIB_TCO_TMR, period); 435 } 436 437 /* and start/reload the timer. */ 438 tcotimer_start(sc); 439 tcotimer_tickle(smw); 440 } 441 442 return 0; 443 } 444 445 static int 446 tcotimer_tickle(struct sysmon_wdog *smw) 447 { 448 struct lpcib_softc *sc = smw->smw_cookie; 449 450 /* any value is allowed */ 451 if (sc->sc_has_rcba) 452 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 453 else 454 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 455 456 return 0; 457 } 458 459 static void 460 tcotimer_stop(struct lpcib_softc *sc) 461 { 462 uint16_t ioreg; 463 464 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 465 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 466 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 467 } 468 469 static void 470 tcotimer_start(struct lpcib_softc *sc) 471 { 472 uint16_t ioreg; 473 474 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 475 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 476 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 477 } 478 479 static void 480 tcotimer_status_reset(struct lpcib_softc *sc) 481 { 482 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 483 LPCIB_TCO1_STS_TIMEOUT); 484 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 485 LPCIB_TCO2_STS_BOOT_STS); 486 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 487 LPCIB_TCO2_STS_SECONDS_TO_STS); 488 } 489 490 /* 491 * Clear the No Reboot (NR) bit, this enables reboots when the timer 492 * reaches the timeout for the second time. 493 */ 494 static int 495 tcotimer_disable_noreboot(device_t self) 496 { 497 struct lpcib_softc *sc = device_private(self); 498 499 if (sc->sc_has_rcba) { 500 uint32_t status; 501 502 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 503 LPCIB_GCS_OFFSET); 504 status &= ~LPCIB_GCS_NO_REBOOT; 505 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 506 LPCIB_GCS_OFFSET, status); 507 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 508 LPCIB_GCS_OFFSET); 509 if (status & LPCIB_GCS_NO_REBOOT) 510 goto error; 511 } else { 512 pcireg_t pcireg; 513 514 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 515 LPCIB_PCI_GEN_STA); 516 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 517 /* TCO timeout reset is disabled; try to enable it */ 518 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 519 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 520 LPCIB_PCI_GEN_STA, pcireg); 521 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 522 goto error; 523 } 524 } 525 526 return 0; 527 error: 528 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 529 "hope SMBIOS properly handles it.\n"); 530 return EINVAL; 531 } 532 533 534 /* 535 * Intel ICH SpeedStep support. 536 */ 537 #define SS_READ(sc, reg) \ 538 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 539 #define SS_WRITE(sc, reg, val) \ 540 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 541 542 /* 543 * Linux driver says that SpeedStep on older chipsets cause 544 * lockups on Dell Inspiron 8000 and 8100. 545 * It should also not be enabled on systems with the 82855GM 546 * Hub, which typically have an EST-enabled CPU. 547 */ 548 static int 549 speedstep_bad_hb_check(struct pci_attach_args *pa) 550 { 551 552 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 553 PCI_REVISION(pa->pa_class) < 5) 554 return 1; 555 556 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 557 return 1; 558 559 return 0; 560 } 561 562 static void 563 speedstep_configure(device_t self) 564 { 565 struct lpcib_softc *sc = device_private(self); 566 const struct sysctlnode *node, *ssnode; 567 int rv; 568 569 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 570 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 571 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 572 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 573 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 574 uint8_t pmcon; 575 576 /* Enable SpeedStep if it isn't already enabled. */ 577 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 578 LPCIB_PCI_GEN_PMCON_1); 579 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 580 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 581 LPCIB_PCI_GEN_PMCON_1, 582 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 583 584 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 585 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 586 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 587 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 588 goto err; 589 590 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 591 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 592 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 593 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 594 CTL_EOL)) != 0) 595 goto err; 596 597 /* XXX save the sc for IO tag/handle */ 598 speedstep_cookie = sc; 599 aprint_verbose_dev(self, "SpeedStep enabled\n"); 600 } 601 602 return; 603 604 err: 605 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 606 } 607 608 /* 609 * get/set the SpeedStep state: 0 == low power, 1 == high power. 610 */ 611 static int 612 speedstep_sysctl_helper(SYSCTLFN_ARGS) 613 { 614 struct sysctlnode node; 615 struct lpcib_softc *sc = speedstep_cookie; 616 uint8_t state, state2; 617 int ostate, nstate, s, error = 0; 618 619 /* 620 * We do the dance with spl's to avoid being at high ipl during 621 * sysctl_lookup() which can both copyin and copyout. 622 */ 623 s = splserial(); 624 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 625 splx(s); 626 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 627 ostate = 1; 628 else 629 ostate = 0; 630 nstate = ostate; 631 632 node = *rnode; 633 node.sysctl_data = &nstate; 634 635 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 636 if (error || newp == NULL) 637 goto out; 638 639 /* Only two states are available */ 640 if (nstate != 0 && nstate != 1) { 641 error = EINVAL; 642 goto out; 643 } 644 645 s = splserial(); 646 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 647 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 648 ostate = 1; 649 else 650 ostate = 0; 651 652 if (ostate != nstate) { 653 uint8_t cntl; 654 655 if (nstate == 0) 656 state2 |= LPCIB_PM_SS_STATE_LOW; 657 else 658 state2 &= ~LPCIB_PM_SS_STATE_LOW; 659 660 /* 661 * Must disable bus master arbitration during the change. 662 */ 663 cntl = SS_READ(sc, LPCIB_PM_CTRL); 664 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 665 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 666 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 667 } 668 splx(s); 669 out: 670 return error; 671 } 672 673 #if NHPET > 0 674 struct lpcib_hpet_attach_arg { 675 bus_space_tag_t hpet_mem_t; 676 uint32_t hpet_reg; 677 }; 678 679 static int 680 lpcib_hpet_match(device_t parent, cfdata_t match, void *aux) 681 { 682 struct lpcib_hpet_attach_arg *arg = aux; 683 bus_space_tag_t tag; 684 bus_space_handle_t handle; 685 686 tag = arg->hpet_mem_t; 687 688 if (bus_space_map(tag, arg->hpet_reg, HPET_WINDOW_SIZE, 0, &handle)) { 689 aprint_verbose_dev(parent, "HPET window not mapped, skipping\n"); 690 return 0; 691 } 692 bus_space_unmap(tag, handle, HPET_WINDOW_SIZE); 693 694 return 1; 695 } 696 697 static void 698 lpcib_hpet_attach(device_t parent, device_t self, void *aux) 699 { 700 struct hpet_softc *sc = device_private(self); 701 struct lpcib_hpet_attach_arg *arg = aux; 702 703 aprint_naive("\n"); 704 aprint_normal("\n"); 705 706 sc->sc_memt = arg->hpet_mem_t; 707 708 if (bus_space_map(sc->sc_memt, arg->hpet_reg, HPET_WINDOW_SIZE, 0, 709 &sc->sc_memh)) { 710 aprint_error_dev(self, 711 "HPET memory window could not be mapped"); 712 return; 713 } 714 715 hpet_attach_subr(self); 716 } 717 718 CFATTACH_DECL_NEW(ichlpcib_hpet, sizeof(struct hpet_softc), lpcib_hpet_match, 719 lpcib_hpet_attach, NULL, NULL); 720 721 static void 722 lpcib_hpet_configure(device_t self) 723 { 724 struct lpcib_softc *sc = device_private(self); 725 struct lpcib_hpet_attach_arg arg; 726 uint32_t hpet_reg, val; 727 728 if (sc->sc_has_ich5_hpet) { 729 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 730 LPCIB_PCI_GEN_CNTL); 731 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 732 case LPCIB_ICH5_HPTC_0000: 733 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 734 break; 735 case LPCIB_ICH5_HPTC_1000: 736 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 737 break; 738 case LPCIB_ICH5_HPTC_2000: 739 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 740 break; 741 case LPCIB_ICH5_HPTC_3000: 742 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 743 break; 744 default: 745 return; 746 } 747 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 748 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 749 LPCIB_PCI_GEN_CNTL, val); 750 } else if (sc->sc_has_rcba) { 751 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 752 LPCIB_RCBA_HPTC); 753 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 754 case LPCIB_RCBA_HPTC_0000: 755 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 756 break; 757 case LPCIB_RCBA_HPTC_1000: 758 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 759 break; 760 case LPCIB_RCBA_HPTC_2000: 761 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 762 break; 763 case LPCIB_RCBA_HPTC_3000: 764 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 765 break; 766 default: 767 return; 768 } 769 val |= LPCIB_RCBA_HPTC_EN; 770 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 771 val); 772 } else { 773 /* No HPET here */ 774 return; 775 } 776 777 arg.hpet_mem_t = sc->sc_pa.pa_memt; 778 arg.hpet_reg = hpet_reg; 779 780 config_found_ia(self, "hpetichbus", &arg, NULL); 781 } 782 #endif 783
Indexes created Wed Oct 01 18:09:54 GMT 2025