ichlpcib.c revision 1.14.4.2
1 /* $NetBSD: ichlpcib.c,v 1.14.4.2 2009/08/16 00:16:28 snj Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.14.4.2 2009/08/16 00:16:28 snj Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <machine/bus.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <dev/sysmon/sysmonvar.h> 57 58 #include <dev/ic/acpipmtimer.h> 59 #include <dev/ic/i82801lpcreg.h> 60 #include <dev/ic/hpetreg.h> 61 #include <dev/ic/hpetvar.h> 62 63 #include "hpet.h" 64 #include "pcibvar.h" 65 66 struct lpcib_softc { 67 /* we call pcibattach() which assumes this starts like this: */ 68 struct pcib_softc sc_pcib; 69 70 struct pci_attach_args sc_pa; 71 int sc_has_rcba; 72 int sc_has_ich5_hpet; 73 74 /* RCBA */ 75 bus_space_tag_t sc_rcbat; 76 bus_space_handle_t sc_rcbah; 77 pcireg_t sc_rcba_reg; 78 79 /* Watchdog variables. */ 80 struct sysmon_wdog sc_smw; 81 bus_space_tag_t sc_iot; 82 bus_space_handle_t sc_ioh; 83 84 #if NHPET > 0 85 /* HPET variables. */ 86 uint32_t sc_hpet_reg; 87 #endif 88 89 /* Speedstep */ 90 pcireg_t sc_pmcon_orig; 91 92 /* Power management */ 93 pcireg_t sc_pirq[2]; 94 pcireg_t sc_pmcon; 95 pcireg_t sc_fwhsel2; 96 }; 97 98 static int lpcibmatch(device_t, cfdata_t, void *); 99 static void lpcibattach(device_t, device_t, void *); 100 static bool lpcib_suspend(device_t PMF_FN_PROTO); 101 static bool lpcib_resume(device_t PMF_FN_PROTO); 102 static bool lpcib_shutdown(device_t, int); 103 104 static void pmtimer_configure(device_t); 105 106 static void tcotimer_configure(device_t); 107 static int tcotimer_setmode(struct sysmon_wdog *); 108 static int tcotimer_tickle(struct sysmon_wdog *); 109 static void tcotimer_stop(struct lpcib_softc *); 110 static void tcotimer_start(struct lpcib_softc *); 111 static void tcotimer_status_reset(struct lpcib_softc *); 112 static int tcotimer_disable_noreboot(device_t); 113 114 static void speedstep_configure(device_t); 115 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 116 117 #if NHPET > 0 118 static void lpcib_hpet_configure(device_t); 119 #endif 120 121 struct lpcib_softc *speedstep_cookie; /* XXX */ 122 123 CFATTACH_DECL_NEW(ichlpcib, sizeof(struct lpcib_softc), 124 lpcibmatch, lpcibattach, NULL, NULL); 125 126 static struct lpcib_device { 127 pcireg_t vendor, product; 128 int has_rcba; 129 int has_ich5_hpet; 130 } lpcib_devices[] = { 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 0, 0 }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 154 155 { 0, 0, 0, 0 }, 156 }; 157 158 /* 159 * Autoconf callbacks. 160 */ 161 static int 162 lpcibmatch(device_t parent, cfdata_t match, void *aux) 163 { 164 struct pci_attach_args *pa = aux; 165 struct lpcib_device *lpcib_dev; 166 167 /* We are ISA bridge, of course */ 168 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 169 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 170 return 0; 171 172 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 173 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 174 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 175 return 10; 176 } 177 178 return 0; 179 } 180 181 static void 182 lpcibattach(device_t parent, device_t self, void *aux) 183 { 184 struct pci_attach_args *pa = aux; 185 struct lpcib_softc *sc = device_private(self); 186 struct lpcib_device *lpcib_dev; 187 188 sc->sc_pa = *pa; 189 190 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 191 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 192 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 193 continue; 194 sc->sc_has_rcba = lpcib_dev->has_rcba; 195 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 196 break; 197 } 198 199 pcibattach(parent, self, aux); 200 201 /* 202 * Part of our I/O registers are used as ACPI PM regs. 203 * Since our ACPI subsystem accesses the I/O space directly so far, 204 * we do not have to bother bus_space I/O map confliction. 205 */ 206 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 207 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 208 aprint_error_dev(self, "can't map power management i/o space"); 209 return; 210 } 211 212 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 213 LPCIB_PCI_GEN_PMCON_1); 214 215 /* For ICH6 and later, always enable RCBA */ 216 if (sc->sc_has_rcba) { 217 pcireg_t rcba; 218 219 sc->sc_rcbat = sc->sc_pa.pa_memt; 220 221 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 222 LPCIB_RCBA); 223 if ((rcba & LPCIB_RCBA_EN) == 0) { 224 aprint_error_dev(self, "RCBA is not enabled"); 225 return; 226 } 227 rcba &= ~LPCIB_RCBA_EN; 228 229 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 230 &sc->sc_rcbah)) { 231 aprint_error_dev(self, "RCBA could not be mapped"); 232 return; 233 } 234 } 235 236 /* Set up the power management timer. */ 237 pmtimer_configure(self); 238 239 /* Set up the TCO (watchdog). */ 240 tcotimer_configure(self); 241 242 /* Set up SpeedStep. */ 243 speedstep_configure(self); 244 245 #if NHPET > 0 246 /* Set up HPET. */ 247 lpcib_hpet_configure(self); 248 #endif 249 250 /* Install power handler */ 251 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 252 lpcib_shutdown)) 253 aprint_error_dev(self, "couldn't establish power handler\n"); 254 } 255 256 static bool 257 lpcib_shutdown(device_t dv, int howto) 258 { 259 struct lpcib_softc *sc = device_private(dv); 260 261 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 262 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 263 264 return true; 265 } 266 267 static bool 268 lpcib_suspend(device_t dv PMF_FN_ARGS) 269 { 270 struct lpcib_softc *sc = device_private(dv); 271 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 272 pcitag_t tag = sc->sc_pcib.sc_tag; 273 274 /* capture PIRQ routing control registers */ 275 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 276 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 277 278 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 279 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 280 281 if (sc->sc_has_rcba) { 282 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 283 #if NHPET > 0 284 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 285 LPCIB_RCBA_HPTC); 286 #endif 287 } else if (sc->sc_has_ich5_hpet) { 288 #if NHPET > 0 289 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 290 #endif 291 } 292 293 return true; 294 } 295 296 static bool 297 lpcib_resume(device_t dv PMF_FN_ARGS) 298 { 299 struct lpcib_softc *sc = device_private(dv); 300 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 301 pcitag_t tag = sc->sc_pcib.sc_tag; 302 303 /* restore PIRQ routing control registers */ 304 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 305 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 306 307 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 308 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 309 310 if (sc->sc_has_rcba) { 311 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 312 #if NHPET > 0 313 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 314 sc->sc_hpet_reg); 315 #endif 316 } else if (sc->sc_has_ich5_hpet) { 317 #if NHPET > 0 318 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 319 #endif 320 } 321 322 return true; 323 } 324 325 /* 326 * Initialize the power management timer. 327 */ 328 static void 329 pmtimer_configure(device_t self) 330 { 331 struct lpcib_softc *sc = device_private(self); 332 pcireg_t control; 333 334 /* 335 * Check if power management I/O space is enabled and enable the ACPI_EN 336 * bit if it's disabled. 337 */ 338 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 339 LPCIB_PCI_ACPI_CNTL); 340 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 341 control |= LPCIB_PCI_ACPI_CNTL_EN; 342 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 343 LPCIB_PCI_ACPI_CNTL, control); 344 } 345 346 /* Attach our PM timer with the generic acpipmtimer function */ 347 acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 348 LPCIB_PM1_TMR, 0); 349 } 350 351 /* 352 * Initialize the watchdog timer. 353 */ 354 static void 355 tcotimer_configure(device_t self) 356 { 357 struct lpcib_softc *sc = device_private(self); 358 uint32_t ioreg; 359 unsigned int period; 360 361 /* Explicitly stop the TCO timer. */ 362 tcotimer_stop(sc); 363 364 /* 365 * Enable TCO timeout SMI only if the hardware reset does not 366 * work. We don't know what the SMBIOS does. 367 */ 368 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 369 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 370 371 /* 372 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 373 * in the SMI_EN register is the last chance. 374 */ 375 if (tcotimer_disable_noreboot(self)) { 376 ioreg |= LPCIB_SMI_EN_TCO_EN; 377 } 378 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 379 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 380 } 381 382 /* Reset the watchdog status registers. */ 383 tcotimer_status_reset(sc); 384 385 /* 386 * Register the driver with the sysmon watchdog framework. 387 */ 388 sc->sc_smw.smw_name = device_xname(self); 389 sc->sc_smw.smw_cookie = sc; 390 sc->sc_smw.smw_setmode = tcotimer_setmode; 391 sc->sc_smw.smw_tickle = tcotimer_tickle; 392 if (sc->sc_has_rcba) 393 period = LPCIB_TCOTIMER2_MAX_TICK; 394 else 395 period = LPCIB_TCOTIMER_MAX_TICK; 396 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 397 398 if (sysmon_wdog_register(&sc->sc_smw)) { 399 aprint_error_dev(self, "unable to register TCO timer" 400 "as a sysmon watchdog device.\n"); 401 return; 402 } 403 404 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 405 } 406 407 /* 408 * Sysmon watchdog callbacks. 409 */ 410 static int 411 tcotimer_setmode(struct sysmon_wdog *smw) 412 { 413 struct lpcib_softc *sc = smw->smw_cookie; 414 unsigned int period; 415 uint16_t ich6period = 0; 416 uint8_t ich5period = 0; 417 418 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 419 /* Stop the TCO timer. */ 420 tcotimer_stop(sc); 421 } else { 422 /* 423 * ICH6 or newer are limited to 2s min and 613s max. 424 * ICH5 or older are limited to 4s min and 39s max. 425 */ 426 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 427 if (sc->sc_has_rcba) { 428 if (period < LPCIB_TCOTIMER2_MIN_TICK || 429 period > LPCIB_TCOTIMER2_MAX_TICK) 430 return EINVAL; 431 } else { 432 if (period < LPCIB_TCOTIMER_MIN_TICK || 433 period > LPCIB_TCOTIMER_MAX_TICK) 434 return EINVAL; 435 } 436 437 /* Stop the TCO timer, */ 438 tcotimer_stop(sc); 439 440 /* set the timeout, */ 441 if (sc->sc_has_rcba) { 442 /* ICH6 or newer */ 443 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 444 LPCIB_TCO_TMR2); 445 ich6period &= 0xfc00; 446 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 447 LPCIB_TCO_TMR2, ich6period | period); 448 } else { 449 /* ICH5 or older */ 450 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 451 LPCIB_TCO_TMR); 452 ich5period &= 0xc0; 453 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 454 LPCIB_TCO_TMR, ich5period | period); 455 } 456 457 /* and start/reload the timer. */ 458 tcotimer_start(sc); 459 tcotimer_tickle(smw); 460 } 461 462 return 0; 463 } 464 465 static int 466 tcotimer_tickle(struct sysmon_wdog *smw) 467 { 468 struct lpcib_softc *sc = smw->smw_cookie; 469 470 /* any value is allowed */ 471 if (sc->sc_has_rcba) 472 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 473 else 474 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 475 476 return 0; 477 } 478 479 static void 480 tcotimer_stop(struct lpcib_softc *sc) 481 { 482 uint16_t ioreg; 483 484 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 485 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 486 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 487 } 488 489 static void 490 tcotimer_start(struct lpcib_softc *sc) 491 { 492 uint16_t ioreg; 493 494 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 495 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 496 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 497 } 498 499 static void 500 tcotimer_status_reset(struct lpcib_softc *sc) 501 { 502 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 503 LPCIB_TCO1_STS_TIMEOUT); 504 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 505 LPCIB_TCO2_STS_BOOT_STS); 506 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 507 LPCIB_TCO2_STS_SECONDS_TO_STS); 508 } 509 510 /* 511 * Clear the No Reboot (NR) bit, this enables reboots when the timer 512 * reaches the timeout for the second time. 513 */ 514 static int 515 tcotimer_disable_noreboot(device_t self) 516 { 517 struct lpcib_softc *sc = device_private(self); 518 519 if (sc->sc_has_rcba) { 520 uint32_t status; 521 522 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 523 LPCIB_GCS_OFFSET); 524 status &= ~LPCIB_GCS_NO_REBOOT; 525 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 526 LPCIB_GCS_OFFSET, status); 527 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 528 LPCIB_GCS_OFFSET); 529 if (status & LPCIB_GCS_NO_REBOOT) 530 goto error; 531 } else { 532 pcireg_t pcireg; 533 534 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 535 LPCIB_PCI_GEN_STA); 536 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 537 /* TCO timeout reset is disabled; try to enable it */ 538 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 539 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 540 LPCIB_PCI_GEN_STA, pcireg); 541 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 542 goto error; 543 } 544 } 545 546 return 0; 547 error: 548 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 549 "hope SMBIOS properly handles it.\n"); 550 return EINVAL; 551 } 552 553 554 /* 555 * Intel ICH SpeedStep support. 556 */ 557 #define SS_READ(sc, reg) \ 558 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 559 #define SS_WRITE(sc, reg, val) \ 560 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 561 562 /* 563 * Linux driver says that SpeedStep on older chipsets cause 564 * lockups on Dell Inspiron 8000 and 8100. 565 */ 566 static int 567 speedstep_bad_hb_check(struct pci_attach_args *pa) 568 { 569 570 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 571 PCI_REVISION(pa->pa_class) < 5) 572 return 1; 573 574 return 0; 575 } 576 577 static void 578 speedstep_configure(device_t self) 579 { 580 struct lpcib_softc *sc = device_private(self); 581 const struct sysctlnode *node, *ssnode; 582 int rv; 583 584 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 585 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 586 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 587 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 588 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 589 uint8_t pmcon; 590 591 /* Enable SpeedStep if it isn't already enabled. */ 592 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 593 LPCIB_PCI_GEN_PMCON_1); 594 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 595 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 596 LPCIB_PCI_GEN_PMCON_1, 597 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 598 599 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 600 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 601 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 602 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 603 goto err; 604 605 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 606 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 607 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 608 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 609 CTL_EOL)) != 0) 610 goto err; 611 612 /* XXX save the sc for IO tag/handle */ 613 speedstep_cookie = sc; 614 aprint_verbose_dev(self, "SpeedStep enabled\n"); 615 } 616 617 return; 618 619 err: 620 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 621 } 622 623 /* 624 * get/set the SpeedStep state: 0 == low power, 1 == high power. 625 */ 626 static int 627 speedstep_sysctl_helper(SYSCTLFN_ARGS) 628 { 629 struct sysctlnode node; 630 struct lpcib_softc *sc = speedstep_cookie; 631 uint8_t state, state2; 632 int ostate, nstate, s, error = 0; 633 634 /* 635 * We do the dance with spl's to avoid being at high ipl during 636 * sysctl_lookup() which can both copyin and copyout. 637 */ 638 s = splserial(); 639 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 640 splx(s); 641 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 642 ostate = 1; 643 else 644 ostate = 0; 645 nstate = ostate; 646 647 node = *rnode; 648 node.sysctl_data = &nstate; 649 650 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 651 if (error || newp == NULL) 652 goto out; 653 654 /* Only two states are available */ 655 if (nstate != 0 && nstate != 1) { 656 error = EINVAL; 657 goto out; 658 } 659 660 s = splserial(); 661 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 662 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 663 ostate = 1; 664 else 665 ostate = 0; 666 667 if (ostate != nstate) { 668 uint8_t cntl; 669 670 if (nstate == 0) 671 state2 |= LPCIB_PM_SS_STATE_LOW; 672 else 673 state2 &= ~LPCIB_PM_SS_STATE_LOW; 674 675 /* 676 * Must disable bus master arbitration during the change. 677 */ 678 cntl = SS_READ(sc, LPCIB_PM_CTRL); 679 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 680 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 681 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 682 } 683 splx(s); 684 out: 685 return error; 686 } 687 688 #if NHPET > 0 689 struct lpcib_hpet_attach_arg { 690 bus_space_tag_t hpet_mem_t; 691 uint32_t hpet_reg; 692 }; 693 694 static int 695 lpcib_hpet_match(device_t parent, cfdata_t match, void *aux) 696 { 697 struct lpcib_hpet_attach_arg *arg = aux; 698 bus_space_tag_t tag; 699 bus_space_handle_t handle; 700 701 tag = arg->hpet_mem_t; 702 703 if (bus_space_map(tag, arg->hpet_reg, HPET_WINDOW_SIZE, 0, &handle)) { 704 aprint_verbose_dev(parent, "HPET window not mapped, skipping\n"); 705 return 0; 706 } 707 bus_space_unmap(tag, handle, HPET_WINDOW_SIZE); 708 709 return 1; 710 } 711 712 static void 713 lpcib_hpet_attach(device_t parent, device_t self, void *aux) 714 { 715 struct hpet_softc *sc = device_private(self); 716 struct lpcib_hpet_attach_arg *arg = aux; 717 718 aprint_naive("\n"); 719 aprint_normal("\n"); 720 721 sc->sc_memt = arg->hpet_mem_t; 722 723 if (bus_space_map(sc->sc_memt, arg->hpet_reg, HPET_WINDOW_SIZE, 0, 724 &sc->sc_memh)) { 725 aprint_error_dev(self, 726 "HPET memory window could not be mapped"); 727 return; 728 } 729 730 hpet_attach_subr(self); 731 } 732 733 CFATTACH_DECL_NEW(ichlpcib_hpet, sizeof(struct hpet_softc), lpcib_hpet_match, 734 lpcib_hpet_attach, NULL, NULL); 735 736 static void 737 lpcib_hpet_configure(device_t self) 738 { 739 struct lpcib_softc *sc = device_private(self); 740 struct lpcib_hpet_attach_arg arg; 741 uint32_t hpet_reg, val; 742 743 if (sc->sc_has_ich5_hpet) { 744 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 745 LPCIB_PCI_GEN_CNTL); 746 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 747 case LPCIB_ICH5_HPTC_0000: 748 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 749 break; 750 case LPCIB_ICH5_HPTC_1000: 751 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 752 break; 753 case LPCIB_ICH5_HPTC_2000: 754 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 755 break; 756 case LPCIB_ICH5_HPTC_3000: 757 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 758 break; 759 default: 760 return; 761 } 762 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 763 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 764 LPCIB_PCI_GEN_CNTL, val); 765 } else if (sc->sc_has_rcba) { 766 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 767 LPCIB_RCBA_HPTC); 768 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 769 case LPCIB_RCBA_HPTC_0000: 770 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 771 break; 772 case LPCIB_RCBA_HPTC_1000: 773 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 774 break; 775 case LPCIB_RCBA_HPTC_2000: 776 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 777 break; 778 case LPCIB_RCBA_HPTC_3000: 779 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 780 break; 781 default: 782 return; 783 } 784 val |= LPCIB_RCBA_HPTC_EN; 785 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 786 val); 787 } else { 788 /* No HPET here */ 789 return; 790 } 791 792 arg.hpet_mem_t = sc->sc_pa.pa_memt; 793 arg.hpet_reg = hpet_reg; 794 795 config_found_ia(self, "hpetichbus", &arg, NULL); 796 } 797 #endif 798
Indexes created Wed Oct 01 18:09:54 GMT 2025