ichlpcib.c revision 1.14.4.4
1 /* $NetBSD: ichlpcib.c,v 1.14.4.4 2015/01/26 13:34:03 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.14.4.4 2015/01/26 13:34:03 martin Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <machine/bus.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <dev/sysmon/sysmonvar.h> 57 58 #include <dev/ic/acpipmtimer.h> 59 #include <dev/ic/i82801lpcreg.h> 60 #include <dev/ic/hpetreg.h> 61 #include <dev/ic/hpetvar.h> 62 63 #include "hpet.h" 64 #include "pcibvar.h" 65 66 struct lpcib_softc { 67 /* we call pcibattach() which assumes this starts like this: */ 68 struct pcib_softc sc_pcib; 69 70 struct pci_attach_args sc_pa; 71 int sc_has_rcba; 72 int sc_has_ich5_hpet; 73 74 /* RCBA */ 75 bus_space_tag_t sc_rcbat; 76 bus_space_handle_t sc_rcbah; 77 pcireg_t sc_rcba_reg; 78 79 /* Watchdog variables. */ 80 struct sysmon_wdog sc_smw; 81 bus_space_tag_t sc_iot; 82 bus_space_handle_t sc_ioh; 83 84 #if NHPET > 0 85 /* HPET variables. */ 86 uint32_t sc_hpet_reg; 87 #endif 88 89 /* Speedstep */ 90 pcireg_t sc_pmcon_orig; 91 92 /* Power management */ 93 pcireg_t sc_pirq[2]; 94 pcireg_t sc_pmcon; 95 pcireg_t sc_fwhsel2; 96 }; 97 98 static int lpcibmatch(device_t, cfdata_t, void *); 99 static void lpcibattach(device_t, device_t, void *); 100 static bool lpcib_suspend(device_t PMF_FN_PROTO); 101 static bool lpcib_resume(device_t PMF_FN_PROTO); 102 static bool lpcib_shutdown(device_t, int); 103 104 static void pmtimer_configure(device_t); 105 106 static void tcotimer_configure(device_t); 107 static int tcotimer_setmode(struct sysmon_wdog *); 108 static int tcotimer_tickle(struct sysmon_wdog *); 109 static void tcotimer_stop(struct lpcib_softc *); 110 static void tcotimer_start(struct lpcib_softc *); 111 static void tcotimer_status_reset(struct lpcib_softc *); 112 static int tcotimer_disable_noreboot(device_t); 113 114 static void speedstep_configure(device_t); 115 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 116 117 #if NHPET > 0 118 static void lpcib_hpet_configure(device_t); 119 #endif 120 121 struct lpcib_softc *speedstep_cookie; /* XXX */ 122 123 CFATTACH_DECL_NEW(ichlpcib, sizeof(struct lpcib_softc), 124 lpcibmatch, lpcibattach, NULL, NULL); 125 126 static struct lpcib_device { 127 pcireg_t vendor, product; 128 int has_rcba; 129 int has_ich5_hpet; 130 } lpcib_devices[] = { 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 0, 0 }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 154 155 { 0, 0, 0, 0 }, 156 }; 157 158 /* 159 * Autoconf callbacks. 160 */ 161 static int 162 lpcibmatch(device_t parent, cfdata_t match, void *aux) 163 { 164 struct pci_attach_args *pa = aux; 165 struct lpcib_device *lpcib_dev; 166 167 /* We are ISA bridge, of course */ 168 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 169 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 170 return 0; 171 172 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 173 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 174 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 175 return 10; 176 } 177 178 return 0; 179 } 180 181 static void 182 lpcibattach(device_t parent, device_t self, void *aux) 183 { 184 struct pci_attach_args *pa = aux; 185 struct lpcib_softc *sc = device_private(self); 186 struct lpcib_device *lpcib_dev; 187 pcireg_t pmbase; 188 189 sc->sc_pa = *pa; 190 191 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 192 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 193 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 194 continue; 195 sc->sc_has_rcba = lpcib_dev->has_rcba; 196 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 197 break; 198 } 199 200 pcibattach(parent, self, aux); 201 202 /* 203 * Part of our I/O registers are used as ACPI PM regs. 204 * Since our ACPI subsystem accesses the I/O space directly so far, 205 * we do not have to bother bus_space I/O map confliction. 206 * 207 * The PMBASE register is alike PCI BAR but not completely compatible 208 * with it. The PMBASE define the base address and the type but 209 * not describe the size. The value of the register may be lower 210 * than LPCIB_PCI_PM_SIZE. It makes impossible to use 211 * pci_mapreg_submap() because the function does range check. 212 */ 213 sc->sc_iot = pa->pa_iot; 214 pmbase = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_PCI_PMBASE); 215 if (bus_space_map(sc->sc_iot, PCI_MAPREG_IO_ADDR(pmbase), 216 LPCIB_PCI_PM_SIZE, 0, &sc->sc_ioh) != 0) { 217 aprint_error_dev(self, 218 "can't map power management i/o space\n"); 219 return; 220 } 221 222 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 223 LPCIB_PCI_GEN_PMCON_1); 224 225 /* For ICH6 and later, always enable RCBA */ 226 if (sc->sc_has_rcba) { 227 pcireg_t rcba; 228 229 sc->sc_rcbat = sc->sc_pa.pa_memt; 230 231 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 232 LPCIB_RCBA); 233 if ((rcba & LPCIB_RCBA_EN) == 0) { 234 aprint_error_dev(self, "RCBA is not enabled\n"); 235 return; 236 } 237 rcba &= ~LPCIB_RCBA_EN; 238 239 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 240 &sc->sc_rcbah)) { 241 aprint_error_dev(self, "RCBA could not be mapped\n"); 242 return; 243 } 244 } 245 246 /* Set up the power management timer. */ 247 pmtimer_configure(self); 248 249 /* Set up the TCO (watchdog). */ 250 tcotimer_configure(self); 251 252 /* Set up SpeedStep. */ 253 speedstep_configure(self); 254 255 #if NHPET > 0 256 /* Set up HPET. */ 257 lpcib_hpet_configure(self); 258 #endif 259 260 /* Install power handler */ 261 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 262 lpcib_shutdown)) 263 aprint_error_dev(self, "couldn't establish power handler\n"); 264 } 265 266 static bool 267 lpcib_shutdown(device_t dv, int howto) 268 { 269 struct lpcib_softc *sc = device_private(dv); 270 271 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 272 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 273 274 return true; 275 } 276 277 static bool 278 lpcib_suspend(device_t dv PMF_FN_ARGS) 279 { 280 struct lpcib_softc *sc = device_private(dv); 281 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 282 pcitag_t tag = sc->sc_pcib.sc_tag; 283 284 /* capture PIRQ routing control registers */ 285 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 286 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 287 288 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 289 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 290 291 if (sc->sc_has_rcba) { 292 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 293 #if NHPET > 0 294 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 295 LPCIB_RCBA_HPTC); 296 #endif 297 } else if (sc->sc_has_ich5_hpet) { 298 #if NHPET > 0 299 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 300 #endif 301 } 302 303 return true; 304 } 305 306 static bool 307 lpcib_resume(device_t dv PMF_FN_ARGS) 308 { 309 struct lpcib_softc *sc = device_private(dv); 310 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 311 pcitag_t tag = sc->sc_pcib.sc_tag; 312 313 /* restore PIRQ routing control registers */ 314 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 315 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 316 317 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 318 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 319 320 if (sc->sc_has_rcba) { 321 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 322 #if NHPET > 0 323 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 324 sc->sc_hpet_reg); 325 #endif 326 } else if (sc->sc_has_ich5_hpet) { 327 #if NHPET > 0 328 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 329 #endif 330 } 331 332 return true; 333 } 334 335 /* 336 * Initialize the power management timer. 337 */ 338 static void 339 pmtimer_configure(device_t self) 340 { 341 struct lpcib_softc *sc = device_private(self); 342 pcireg_t control; 343 344 /* 345 * Check if power management I/O space is enabled and enable the ACPI_EN 346 * bit if it's disabled. 347 */ 348 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 349 LPCIB_PCI_ACPI_CNTL); 350 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 351 control |= LPCIB_PCI_ACPI_CNTL_EN; 352 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 353 LPCIB_PCI_ACPI_CNTL, control); 354 } 355 356 /* Attach our PM timer with the generic acpipmtimer function */ 357 acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 358 LPCIB_PM1_TMR, 0); 359 } 360 361 /* 362 * Initialize the watchdog timer. 363 */ 364 static void 365 tcotimer_configure(device_t self) 366 { 367 struct lpcib_softc *sc = device_private(self); 368 uint32_t ioreg; 369 unsigned int period; 370 371 /* Explicitly stop the TCO timer. */ 372 tcotimer_stop(sc); 373 374 /* 375 * Enable TCO timeout SMI only if the hardware reset does not 376 * work. We don't know what the SMBIOS does. 377 */ 378 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 379 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 380 381 /* 382 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 383 * in the SMI_EN register is the last chance. 384 */ 385 if (tcotimer_disable_noreboot(self)) { 386 ioreg |= LPCIB_SMI_EN_TCO_EN; 387 } 388 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 389 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 390 } 391 392 /* Reset the watchdog status registers. */ 393 tcotimer_status_reset(sc); 394 395 /* 396 * Register the driver with the sysmon watchdog framework. 397 */ 398 sc->sc_smw.smw_name = device_xname(self); 399 sc->sc_smw.smw_cookie = sc; 400 sc->sc_smw.smw_setmode = tcotimer_setmode; 401 sc->sc_smw.smw_tickle = tcotimer_tickle; 402 if (sc->sc_has_rcba) 403 period = LPCIB_TCOTIMER2_MAX_TICK; 404 else 405 period = LPCIB_TCOTIMER_MAX_TICK; 406 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 407 408 if (sysmon_wdog_register(&sc->sc_smw)) { 409 aprint_error_dev(self, "unable to register TCO timer" 410 "as a sysmon watchdog device.\n"); 411 return; 412 } 413 414 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 415 } 416 417 /* 418 * Sysmon watchdog callbacks. 419 */ 420 static int 421 tcotimer_setmode(struct sysmon_wdog *smw) 422 { 423 struct lpcib_softc *sc = smw->smw_cookie; 424 unsigned int period; 425 uint16_t ich6period = 0; 426 uint8_t ich5period = 0; 427 428 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 429 /* Stop the TCO timer. */ 430 tcotimer_stop(sc); 431 } else { 432 /* 433 * ICH6 or newer are limited to 2s min and 613s max. 434 * ICH5 or older are limited to 4s min and 39s max. 435 */ 436 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 437 if (sc->sc_has_rcba) { 438 if (period < LPCIB_TCOTIMER2_MIN_TICK || 439 period > LPCIB_TCOTIMER2_MAX_TICK) 440 return EINVAL; 441 } else { 442 if (period < LPCIB_TCOTIMER_MIN_TICK || 443 period > LPCIB_TCOTIMER_MAX_TICK) 444 return EINVAL; 445 } 446 447 /* Stop the TCO timer, */ 448 tcotimer_stop(sc); 449 450 /* set the timeout, */ 451 if (sc->sc_has_rcba) { 452 /* ICH6 or newer */ 453 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 454 LPCIB_TCO_TMR2); 455 ich6period &= 0xfc00; 456 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 457 LPCIB_TCO_TMR2, ich6period | period); 458 } else { 459 /* ICH5 or older */ 460 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 461 LPCIB_TCO_TMR); 462 ich5period &= 0xc0; 463 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 464 LPCIB_TCO_TMR, ich5period | period); 465 } 466 467 /* and start/reload the timer. */ 468 tcotimer_start(sc); 469 tcotimer_tickle(smw); 470 } 471 472 return 0; 473 } 474 475 static int 476 tcotimer_tickle(struct sysmon_wdog *smw) 477 { 478 struct lpcib_softc *sc = smw->smw_cookie; 479 480 /* any value is allowed */ 481 if (sc->sc_has_rcba) 482 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 483 else 484 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 485 486 return 0; 487 } 488 489 static void 490 tcotimer_stop(struct lpcib_softc *sc) 491 { 492 uint16_t ioreg; 493 494 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 495 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 496 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 497 } 498 499 static void 500 tcotimer_start(struct lpcib_softc *sc) 501 { 502 uint16_t ioreg; 503 504 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 505 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 506 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 507 } 508 509 static void 510 tcotimer_status_reset(struct lpcib_softc *sc) 511 { 512 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 513 LPCIB_TCO1_STS_TIMEOUT); 514 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 515 LPCIB_TCO2_STS_BOOT_STS); 516 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 517 LPCIB_TCO2_STS_SECONDS_TO_STS); 518 } 519 520 /* 521 * Clear the No Reboot (NR) bit, this enables reboots when the timer 522 * reaches the timeout for the second time. 523 */ 524 static int 525 tcotimer_disable_noreboot(device_t self) 526 { 527 struct lpcib_softc *sc = device_private(self); 528 529 if (sc->sc_has_rcba) { 530 uint32_t status; 531 532 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 533 LPCIB_GCS_OFFSET); 534 status &= ~LPCIB_GCS_NO_REBOOT; 535 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 536 LPCIB_GCS_OFFSET, status); 537 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 538 LPCIB_GCS_OFFSET); 539 if (status & LPCIB_GCS_NO_REBOOT) 540 goto error; 541 } else { 542 pcireg_t pcireg; 543 544 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 545 LPCIB_PCI_GEN_STA); 546 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 547 /* TCO timeout reset is disabled; try to enable it */ 548 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 549 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 550 LPCIB_PCI_GEN_STA, pcireg); 551 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 552 goto error; 553 } 554 } 555 556 return 0; 557 error: 558 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 559 "hope SMBIOS properly handles it.\n"); 560 return EINVAL; 561 } 562 563 564 /* 565 * Intel ICH SpeedStep support. 566 */ 567 #define SS_READ(sc, reg) \ 568 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 569 #define SS_WRITE(sc, reg, val) \ 570 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 571 572 /* 573 * Linux driver says that SpeedStep on older chipsets cause 574 * lockups on Dell Inspiron 8000 and 8100. 575 */ 576 static int 577 speedstep_bad_hb_check(struct pci_attach_args *pa) 578 { 579 580 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 581 PCI_REVISION(pa->pa_class) < 5) 582 return 1; 583 584 return 0; 585 } 586 587 static void 588 speedstep_configure(device_t self) 589 { 590 struct lpcib_softc *sc = device_private(self); 591 const struct sysctlnode *node, *ssnode; 592 int rv; 593 594 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 595 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 596 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 597 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 598 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 599 uint8_t pmcon; 600 601 /* Enable SpeedStep if it isn't already enabled. */ 602 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 603 LPCIB_PCI_GEN_PMCON_1); 604 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 605 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 606 LPCIB_PCI_GEN_PMCON_1, 607 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 608 609 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 610 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 611 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 612 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 613 goto err; 614 615 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 616 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 617 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 618 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 619 CTL_EOL)) != 0) 620 goto err; 621 622 /* XXX save the sc for IO tag/handle */ 623 speedstep_cookie = sc; 624 aprint_verbose_dev(self, "SpeedStep enabled\n"); 625 } 626 627 return; 628 629 err: 630 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 631 } 632 633 /* 634 * get/set the SpeedStep state: 0 == low power, 1 == high power. 635 */ 636 static int 637 speedstep_sysctl_helper(SYSCTLFN_ARGS) 638 { 639 struct sysctlnode node; 640 struct lpcib_softc *sc = speedstep_cookie; 641 uint8_t state, state2; 642 int ostate, nstate, s, error = 0; 643 644 /* 645 * We do the dance with spl's to avoid being at high ipl during 646 * sysctl_lookup() which can both copyin and copyout. 647 */ 648 s = splserial(); 649 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 650 splx(s); 651 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 652 ostate = 1; 653 else 654 ostate = 0; 655 nstate = ostate; 656 657 node = *rnode; 658 node.sysctl_data = &nstate; 659 660 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 661 if (error || newp == NULL) 662 goto out; 663 664 /* Only two states are available */ 665 if (nstate != 0 && nstate != 1) { 666 error = EINVAL; 667 goto out; 668 } 669 670 s = splserial(); 671 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 672 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 673 ostate = 1; 674 else 675 ostate = 0; 676 677 if (ostate != nstate) { 678 uint8_t cntl; 679 680 if (nstate == 0) 681 state2 |= LPCIB_PM_SS_STATE_LOW; 682 else 683 state2 &= ~LPCIB_PM_SS_STATE_LOW; 684 685 /* 686 * Must disable bus master arbitration during the change. 687 */ 688 cntl = SS_READ(sc, LPCIB_PM_CTRL); 689 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 690 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 691 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 692 } 693 splx(s); 694 out: 695 return error; 696 } 697 698 #if NHPET > 0 699 struct lpcib_hpet_attach_arg { 700 bus_space_tag_t hpet_mem_t; 701 uint32_t hpet_reg; 702 }; 703 704 static int 705 lpcib_hpet_match(device_t parent, cfdata_t match, void *aux) 706 { 707 struct lpcib_hpet_attach_arg *arg = aux; 708 bus_space_tag_t tag; 709 bus_space_handle_t handle; 710 711 tag = arg->hpet_mem_t; 712 713 if (bus_space_map(tag, arg->hpet_reg, HPET_WINDOW_SIZE, 0, &handle)) { 714 aprint_verbose_dev(parent, "HPET window not mapped, skipping\n"); 715 return 0; 716 } 717 bus_space_unmap(tag, handle, HPET_WINDOW_SIZE); 718 719 return 1; 720 } 721 722 static void 723 lpcib_hpet_attach(device_t parent, device_t self, void *aux) 724 { 725 struct hpet_softc *sc = device_private(self); 726 struct lpcib_hpet_attach_arg *arg = aux; 727 728 aprint_naive("\n"); 729 aprint_normal("\n"); 730 731 sc->sc_memt = arg->hpet_mem_t; 732 733 if (bus_space_map(sc->sc_memt, arg->hpet_reg, HPET_WINDOW_SIZE, 0, 734 &sc->sc_memh)) { 735 aprint_error_dev(self, 736 "HPET memory window could not be mapped"); 737 return; 738 } 739 740 hpet_attach_subr(self); 741 } 742 743 CFATTACH_DECL_NEW(ichlpcib_hpet, sizeof(struct hpet_softc), lpcib_hpet_match, 744 lpcib_hpet_attach, NULL, NULL); 745 746 static void 747 lpcib_hpet_configure(device_t self) 748 { 749 struct lpcib_softc *sc = device_private(self); 750 struct lpcib_hpet_attach_arg arg; 751 uint32_t hpet_reg, val; 752 753 if (sc->sc_has_ich5_hpet) { 754 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 755 LPCIB_PCI_GEN_CNTL); 756 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 757 case LPCIB_ICH5_HPTC_0000: 758 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 759 break; 760 case LPCIB_ICH5_HPTC_1000: 761 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 762 break; 763 case LPCIB_ICH5_HPTC_2000: 764 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 765 break; 766 case LPCIB_ICH5_HPTC_3000: 767 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 768 break; 769 default: 770 return; 771 } 772 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 773 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 774 LPCIB_PCI_GEN_CNTL, val); 775 } else if (sc->sc_has_rcba) { 776 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 777 LPCIB_RCBA_HPTC); 778 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 779 case LPCIB_RCBA_HPTC_0000: 780 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 781 break; 782 case LPCIB_RCBA_HPTC_1000: 783 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 784 break; 785 case LPCIB_RCBA_HPTC_2000: 786 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 787 break; 788 case LPCIB_RCBA_HPTC_3000: 789 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 790 break; 791 default: 792 return; 793 } 794 val |= LPCIB_RCBA_HPTC_EN; 795 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 796 val); 797 } else { 798 /* No HPET here */ 799 return; 800 } 801 802 arg.hpet_mem_t = sc->sc_pa.pa_memt; 803 arg.hpet_reg = hpet_reg; 804 805 config_found_ia(self, "hpetichbus", &arg, NULL); 806 } 807 #endif 808
Indexes created Wed Oct 01 18:09:54 GMT 2025