ichlpcib.c revision 1.14.8.5
1 /* $NetBSD: ichlpcib.c,v 1.14.8.5 2011/08/27 15:37:30 jym Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.14.8.5 2011/08/27 15:37:30 jym Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 215 216 { 0, 0, 0, 0 }, 217 }; 218 219 /* 220 * Autoconf callbacks. 221 */ 222 static int 223 lpcibmatch(device_t parent, cfdata_t match, void *aux) 224 { 225 struct pci_attach_args *pa = aux; 226 struct lpcib_device *lpcib_dev; 227 228 /* We are ISA bridge, of course */ 229 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 230 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 231 return 0; 232 233 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 234 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 235 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 236 return 10; 237 } 238 239 return 0; 240 } 241 242 static void 243 lpcibattach(device_t parent, device_t self, void *aux) 244 { 245 struct pci_attach_args *pa = aux; 246 struct lpcib_softc *sc = device_private(self); 247 struct lpcib_device *lpcib_dev; 248 249 sc->sc_pa = *pa; 250 251 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 252 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 253 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 254 continue; 255 sc->sc_has_rcba = lpcib_dev->has_rcba; 256 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 257 break; 258 } 259 260 pcibattach(parent, self, aux); 261 262 /* 263 * Part of our I/O registers are used as ACPI PM regs. 264 * Since our ACPI subsystem accesses the I/O space directly so far, 265 * we do not have to bother bus_space I/O map confliction. 266 */ 267 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 268 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_iosize)) { 269 aprint_error_dev(self, "can't map power management i/o space"); 270 return; 271 } 272 273 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 274 LPCIB_PCI_GEN_PMCON_1); 275 276 /* For ICH6 and later, always enable RCBA */ 277 if (sc->sc_has_rcba) { 278 pcireg_t rcba; 279 280 sc->sc_rcbat = sc->sc_pa.pa_memt; 281 282 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 283 LPCIB_RCBA); 284 if ((rcba & LPCIB_RCBA_EN) == 0) { 285 aprint_error_dev(self, "RCBA is not enabled"); 286 return; 287 } 288 rcba &= ~LPCIB_RCBA_EN; 289 290 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 291 &sc->sc_rcbah)) { 292 aprint_error_dev(self, "RCBA could not be mapped"); 293 return; 294 } 295 } 296 297 /* Set up the power management timer. */ 298 pmtimer_configure(self); 299 300 /* Set up the TCO (watchdog). */ 301 tcotimer_configure(self); 302 303 /* Set up SpeedStep. */ 304 speedstep_configure(self); 305 306 /* Set up HPET. */ 307 lpcib_hpet_configure(self); 308 309 #if NGPIO > 0 310 /* Set up GPIO */ 311 lpcib_gpio_configure(self); 312 #endif 313 314 #if NFWHRNG > 0 315 lpcib_fwh_configure(self); 316 #endif 317 318 /* Install power handler */ 319 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 320 lpcib_shutdown)) 321 aprint_error_dev(self, "couldn't establish power handler\n"); 322 } 323 324 static void 325 lpcibchilddet(device_t self, device_t child) 326 { 327 struct lpcib_softc *sc = device_private(self); 328 uint32_t val; 329 330 #if NFWHRNG > 0 331 if (sc->sc_fwhbus == child) { 332 sc->sc_fwhbus = NULL; 333 return; 334 } 335 #endif 336 #if NGPIO > 0 337 if (sc->sc_gpiobus == child) { 338 sc->sc_gpiobus = NULL; 339 return; 340 } 341 #endif 342 if (sc->sc_hpetbus != child) { 343 pcibchilddet(self, child); 344 return; 345 } 346 sc->sc_hpetbus = NULL; 347 if (sc->sc_has_ich5_hpet) { 348 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 349 LPCIB_PCI_GEN_CNTL); 350 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 351 case LPCIB_ICH5_HPTC_0000: 352 case LPCIB_ICH5_HPTC_1000: 353 case LPCIB_ICH5_HPTC_2000: 354 case LPCIB_ICH5_HPTC_3000: 355 break; 356 default: 357 return; 358 } 359 val &= ~LPCIB_ICH5_HPTC_EN; 360 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 361 LPCIB_PCI_GEN_CNTL, val); 362 } else if (sc->sc_has_rcba) { 363 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 364 LPCIB_RCBA_HPTC); 365 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 366 case LPCIB_RCBA_HPTC_0000: 367 case LPCIB_RCBA_HPTC_1000: 368 case LPCIB_RCBA_HPTC_2000: 369 case LPCIB_RCBA_HPTC_3000: 370 break; 371 default: 372 return; 373 } 374 val &= ~LPCIB_RCBA_HPTC_EN; 375 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 376 val); 377 } 378 } 379 380 static int 381 lpcibrescan(device_t self, const char *ifattr, const int *locators) 382 { 383 struct lpcib_softc *sc = device_private(self); 384 385 #if NFWHRNG > 0 386 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 387 lpcib_fwh_configure(self); 388 #endif 389 390 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 391 lpcib_hpet_configure(self); 392 393 #if NGPIO > 0 394 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 395 lpcib_gpio_configure(self); 396 #endif 397 398 return pcibrescan(self, ifattr, locators); 399 } 400 401 static int 402 lpcibdetach(device_t self, int flags) 403 { 404 struct lpcib_softc *sc = device_private(self); 405 int rc; 406 407 pmf_device_deregister(self); 408 409 #if NFWHRNG > 0 410 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 411 return rc; 412 #endif 413 414 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 415 return rc; 416 417 #if NGPIO > 0 418 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 419 return rc; 420 #endif 421 422 /* Set up SpeedStep. */ 423 speedstep_unconfigure(self); 424 425 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 426 return rc; 427 428 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 429 return rc; 430 431 if (sc->sc_has_rcba) 432 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 433 434 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 435 436 return pcibdetach(self, flags); 437 } 438 439 static bool 440 lpcib_shutdown(device_t dv, int howto) 441 { 442 struct lpcib_softc *sc = device_private(dv); 443 444 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 445 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 446 447 return true; 448 } 449 450 static bool 451 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 452 { 453 struct lpcib_softc *sc = device_private(dv); 454 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 455 pcitag_t tag = sc->sc_pcib.sc_tag; 456 457 /* capture PIRQ routing control registers */ 458 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 459 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 460 461 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 462 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 463 464 if (sc->sc_has_rcba) { 465 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 466 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 467 LPCIB_RCBA_HPTC); 468 } else if (sc->sc_has_ich5_hpet) { 469 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 470 } 471 472 return true; 473 } 474 475 static bool 476 lpcib_resume(device_t dv, const pmf_qual_t *qual) 477 { 478 struct lpcib_softc *sc = device_private(dv); 479 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 480 pcitag_t tag = sc->sc_pcib.sc_tag; 481 482 /* restore PIRQ routing control registers */ 483 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 484 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 485 486 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 487 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 488 489 if (sc->sc_has_rcba) { 490 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 491 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 492 sc->sc_hpet_reg); 493 } else if (sc->sc_has_ich5_hpet) { 494 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 495 } 496 497 return true; 498 } 499 500 /* 501 * Initialize the power management timer. 502 */ 503 static void 504 pmtimer_configure(device_t self) 505 { 506 struct lpcib_softc *sc = device_private(self); 507 pcireg_t control; 508 509 /* 510 * Check if power management I/O space is enabled and enable the ACPI_EN 511 * bit if it's disabled. 512 */ 513 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 514 LPCIB_PCI_ACPI_CNTL); 515 sc->sc_acpi_cntl = control; 516 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 517 control |= LPCIB_PCI_ACPI_CNTL_EN; 518 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 519 LPCIB_PCI_ACPI_CNTL, control); 520 } 521 522 /* Attach our PM timer with the generic acpipmtimer function */ 523 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 524 LPCIB_PM1_TMR, 0); 525 } 526 527 static int 528 pmtimer_unconfigure(device_t self, int flags) 529 { 530 struct lpcib_softc *sc = device_private(self); 531 int rc; 532 533 if (sc->sc_pmtimer != NULL && 534 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 535 return rc; 536 537 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 538 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 539 540 return 0; 541 } 542 543 /* 544 * Initialize the watchdog timer. 545 */ 546 static void 547 tcotimer_configure(device_t self) 548 { 549 struct lpcib_softc *sc = device_private(self); 550 uint32_t ioreg; 551 unsigned int period; 552 553 /* Explicitly stop the TCO timer. */ 554 tcotimer_stop(sc); 555 556 /* 557 * Enable TCO timeout SMI only if the hardware reset does not 558 * work. We don't know what the SMBIOS does. 559 */ 560 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 561 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 562 563 /* 564 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 565 * in the SMI_EN register is the last chance. 566 */ 567 if (tcotimer_disable_noreboot(self)) { 568 ioreg |= LPCIB_SMI_EN_TCO_EN; 569 } 570 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 571 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 572 } 573 574 /* Reset the watchdog status registers. */ 575 tcotimer_status_reset(sc); 576 577 /* 578 * Register the driver with the sysmon watchdog framework. 579 */ 580 sc->sc_smw.smw_name = device_xname(self); 581 sc->sc_smw.smw_cookie = sc; 582 sc->sc_smw.smw_setmode = tcotimer_setmode; 583 sc->sc_smw.smw_tickle = tcotimer_tickle; 584 if (sc->sc_has_rcba) 585 period = LPCIB_TCOTIMER2_MAX_TICK; 586 else 587 period = LPCIB_TCOTIMER_MAX_TICK; 588 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 589 590 if (sysmon_wdog_register(&sc->sc_smw)) { 591 aprint_error_dev(self, "unable to register TCO timer" 592 "as a sysmon watchdog device.\n"); 593 return; 594 } 595 596 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 597 } 598 599 static int 600 tcotimer_unconfigure(device_t self, int flags) 601 { 602 struct lpcib_softc *sc = device_private(self); 603 int rc; 604 605 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 606 if (rc == ERESTART) 607 rc = EINTR; 608 return rc; 609 } 610 611 /* Explicitly stop the TCO timer. */ 612 tcotimer_stop(sc); 613 614 /* XXX Set No Reboot? */ 615 616 return 0; 617 } 618 619 620 /* 621 * Sysmon watchdog callbacks. 622 */ 623 static int 624 tcotimer_setmode(struct sysmon_wdog *smw) 625 { 626 struct lpcib_softc *sc = smw->smw_cookie; 627 unsigned int period; 628 uint16_t ich6period = 0; 629 uint8_t ich5period = 0; 630 631 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 632 /* Stop the TCO timer. */ 633 tcotimer_stop(sc); 634 } else { 635 /* 636 * ICH6 or newer are limited to 2s min and 613s max. 637 * ICH5 or older are limited to 4s min and 39s max. 638 */ 639 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 640 if (sc->sc_has_rcba) { 641 if (period < LPCIB_TCOTIMER2_MIN_TICK || 642 period > LPCIB_TCOTIMER2_MAX_TICK) 643 return EINVAL; 644 } else { 645 if (period < LPCIB_TCOTIMER_MIN_TICK || 646 period > LPCIB_TCOTIMER_MAX_TICK) 647 return EINVAL; 648 } 649 650 /* Stop the TCO timer, */ 651 tcotimer_stop(sc); 652 653 /* set the timeout, */ 654 if (sc->sc_has_rcba) { 655 /* ICH6 or newer */ 656 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 657 LPCIB_TCO_TMR2); 658 ich6period &= 0xfc00; 659 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 660 LPCIB_TCO_TMR2, ich6period | period); 661 } else { 662 /* ICH5 or older */ 663 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 664 LPCIB_TCO_TMR); 665 ich5period &= 0xc0; 666 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 667 LPCIB_TCO_TMR, ich5period | period); 668 } 669 670 /* and start/reload the timer. */ 671 tcotimer_start(sc); 672 tcotimer_tickle(smw); 673 } 674 675 return 0; 676 } 677 678 static int 679 tcotimer_tickle(struct sysmon_wdog *smw) 680 { 681 struct lpcib_softc *sc = smw->smw_cookie; 682 683 /* any value is allowed */ 684 if (sc->sc_has_rcba) 685 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 686 else 687 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 688 689 return 0; 690 } 691 692 static void 693 tcotimer_stop(struct lpcib_softc *sc) 694 { 695 uint16_t ioreg; 696 697 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 698 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 699 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 700 } 701 702 static void 703 tcotimer_start(struct lpcib_softc *sc) 704 { 705 uint16_t ioreg; 706 707 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 708 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 709 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 710 } 711 712 static void 713 tcotimer_status_reset(struct lpcib_softc *sc) 714 { 715 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 716 LPCIB_TCO1_STS_TIMEOUT); 717 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 718 LPCIB_TCO2_STS_BOOT_STS); 719 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 720 LPCIB_TCO2_STS_SECONDS_TO_STS); 721 } 722 723 /* 724 * Clear the No Reboot (NR) bit, this enables reboots when the timer 725 * reaches the timeout for the second time. 726 */ 727 static int 728 tcotimer_disable_noreboot(device_t self) 729 { 730 struct lpcib_softc *sc = device_private(self); 731 732 if (sc->sc_has_rcba) { 733 uint32_t status; 734 735 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 736 LPCIB_GCS_OFFSET); 737 status &= ~LPCIB_GCS_NO_REBOOT; 738 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 739 LPCIB_GCS_OFFSET, status); 740 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 741 LPCIB_GCS_OFFSET); 742 if (status & LPCIB_GCS_NO_REBOOT) 743 goto error; 744 } else { 745 pcireg_t pcireg; 746 747 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 748 LPCIB_PCI_GEN_STA); 749 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 750 /* TCO timeout reset is disabled; try to enable it */ 751 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 752 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 753 LPCIB_PCI_GEN_STA, pcireg); 754 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 755 goto error; 756 } 757 } 758 759 return 0; 760 error: 761 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 762 "hope SMBIOS properly handles it.\n"); 763 return EINVAL; 764 } 765 766 767 /* 768 * Intel ICH SpeedStep support. 769 */ 770 #define SS_READ(sc, reg) \ 771 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 772 #define SS_WRITE(sc, reg, val) \ 773 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 774 775 /* 776 * Linux driver says that SpeedStep on older chipsets cause 777 * lockups on Dell Inspiron 8000 and 8100. 778 * It should also not be enabled on systems with the 82855GM 779 * Hub, which typically have an EST-enabled CPU. 780 */ 781 static int 782 speedstep_bad_hb_check(const struct pci_attach_args *pa) 783 { 784 785 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 786 PCI_REVISION(pa->pa_class) < 5) 787 return 1; 788 789 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 790 return 1; 791 792 return 0; 793 } 794 795 static void 796 speedstep_configure(device_t self) 797 { 798 struct lpcib_softc *sc = device_private(self); 799 const struct sysctlnode *node, *ssnode; 800 int rv; 801 802 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 803 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 804 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 805 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 806 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 807 pcireg_t pmcon; 808 809 /* Enable SpeedStep if it isn't already enabled. */ 810 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 811 LPCIB_PCI_GEN_PMCON_1); 812 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 813 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 814 LPCIB_PCI_GEN_PMCON_1, 815 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 816 817 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 818 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 819 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 820 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 821 goto err; 822 823 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 824 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 825 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 826 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 827 CTL_EOL)) != 0) 828 goto err; 829 830 /* XXX save the sc for IO tag/handle */ 831 speedstep_cookie = sc; 832 aprint_verbose_dev(self, "SpeedStep enabled\n"); 833 } 834 835 return; 836 837 err: 838 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 839 } 840 841 static void 842 speedstep_unconfigure(device_t self) 843 { 844 struct lpcib_softc *sc = device_private(self); 845 846 sysctl_teardown(&sc->sc_log); 847 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 848 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 849 850 speedstep_cookie = NULL; 851 } 852 853 /* 854 * get/set the SpeedStep state: 0 == low power, 1 == high power. 855 */ 856 static int 857 speedstep_sysctl_helper(SYSCTLFN_ARGS) 858 { 859 struct sysctlnode node; 860 struct lpcib_softc *sc = speedstep_cookie; 861 uint8_t state, state2; 862 int ostate, nstate, s, error = 0; 863 864 /* 865 * We do the dance with spl's to avoid being at high ipl during 866 * sysctl_lookup() which can both copyin and copyout. 867 */ 868 s = splserial(); 869 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 870 splx(s); 871 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 872 ostate = 1; 873 else 874 ostate = 0; 875 nstate = ostate; 876 877 node = *rnode; 878 node.sysctl_data = &nstate; 879 880 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 881 if (error || newp == NULL) 882 goto out; 883 884 /* Only two states are available */ 885 if (nstate != 0 && nstate != 1) { 886 error = EINVAL; 887 goto out; 888 } 889 890 s = splserial(); 891 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 892 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 893 ostate = 1; 894 else 895 ostate = 0; 896 897 if (ostate != nstate) { 898 uint8_t cntl; 899 900 if (nstate == 0) 901 state2 |= LPCIB_PM_SS_STATE_LOW; 902 else 903 state2 &= ~LPCIB_PM_SS_STATE_LOW; 904 905 /* 906 * Must disable bus master arbitration during the change. 907 */ 908 cntl = SS_READ(sc, LPCIB_PM_CTRL); 909 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 910 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 911 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 912 } 913 splx(s); 914 out: 915 return error; 916 } 917 918 static void 919 lpcib_hpet_configure(device_t self) 920 { 921 struct lpcib_softc *sc = device_private(self); 922 struct lpcib_hpet_attach_args arg; 923 uint32_t hpet_reg, val; 924 925 if (sc->sc_has_ich5_hpet) { 926 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 927 LPCIB_PCI_GEN_CNTL); 928 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 929 case LPCIB_ICH5_HPTC_0000: 930 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 931 break; 932 case LPCIB_ICH5_HPTC_1000: 933 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 934 break; 935 case LPCIB_ICH5_HPTC_2000: 936 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 937 break; 938 case LPCIB_ICH5_HPTC_3000: 939 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 940 break; 941 default: 942 return; 943 } 944 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 945 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 946 LPCIB_PCI_GEN_CNTL, val); 947 } else if (sc->sc_has_rcba) { 948 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 949 LPCIB_RCBA_HPTC); 950 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 951 case LPCIB_RCBA_HPTC_0000: 952 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 953 break; 954 case LPCIB_RCBA_HPTC_1000: 955 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 956 break; 957 case LPCIB_RCBA_HPTC_2000: 958 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 959 break; 960 case LPCIB_RCBA_HPTC_3000: 961 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 962 break; 963 default: 964 return; 965 } 966 val |= LPCIB_RCBA_HPTC_EN; 967 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 968 val); 969 } else { 970 /* No HPET here */ 971 return; 972 } 973 974 arg.hpet_mem_t = sc->sc_pa.pa_memt; 975 arg.hpet_reg = hpet_reg; 976 977 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 978 } 979 980 static int 981 lpcib_hpet_unconfigure(device_t self, int flags) 982 { 983 struct lpcib_softc *sc = device_private(self); 984 int rc; 985 986 if (sc->sc_hpetbus != NULL && 987 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 988 return rc; 989 990 return 0; 991 } 992 993 #if NGPIO > 0 994 static void 995 lpcib_gpio_configure(device_t self) 996 { 997 struct lpcib_softc *sc = device_private(self); 998 struct gpiobus_attach_args gba; 999 pcireg_t gpio_cntl; 1000 uint32_t use, io, bit; 1001 int pin, shift, base_reg, cntl_reg, reg; 1002 1003 /* this implies ICH >= 6, and thus different mapreg */ 1004 if (sc->sc_has_rcba) { 1005 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1006 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1007 } else { 1008 base_reg = LPCIB_PCI_GPIO_BASE; 1009 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1010 } 1011 1012 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1013 cntl_reg); 1014 1015 /* Is GPIO enabled? */ 1016 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1017 return; 1018 1019 if (pci_mapreg_map(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0, 1020 &sc->sc_gpio_iot, &sc->sc_gpio_ioh, 1021 NULL, &sc->sc_gpio_ios)) { 1022 aprint_error_dev(self, "can't map general purpose i/o space\n"); 1023 return; 1024 } 1025 1026 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1027 1028 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1029 sc->sc_gpio_pins[pin].pin_num = pin; 1030 1031 /* Read initial state */ 1032 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1033 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1034 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1035 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1036 shift = pin % 32; 1037 bit = __BIT(shift); 1038 1039 if ((use & bit) != 0) { 1040 sc->sc_gpio_pins[pin].pin_caps = 1041 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1042 if (pin < 32) 1043 sc->sc_gpio_pins[pin].pin_caps |= 1044 GPIO_PIN_PULSATE; 1045 if ((io & bit) != 0) 1046 sc->sc_gpio_pins[pin].pin_flags = 1047 GPIO_PIN_INPUT; 1048 else 1049 sc->sc_gpio_pins[pin].pin_flags = 1050 GPIO_PIN_OUTPUT; 1051 } else 1052 sc->sc_gpio_pins[pin].pin_caps = 0; 1053 1054 if (lpcib_gpio_pin_read(sc, pin) == 0) 1055 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1056 else 1057 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1058 1059 } 1060 1061 /* Create controller tag */ 1062 sc->sc_gpio_gc.gp_cookie = sc; 1063 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1064 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1065 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1066 1067 memset(&gba, 0, sizeof(gba)); 1068 1069 gba.gba_gc = &sc->sc_gpio_gc; 1070 gba.gba_pins = sc->sc_gpio_pins; 1071 gba.gba_npins = LPCIB_GPIO_NPINS; 1072 1073 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1074 } 1075 1076 static int 1077 lpcib_gpio_unconfigure(device_t self, int flags) 1078 { 1079 struct lpcib_softc *sc = device_private(self); 1080 int rc; 1081 1082 if (sc->sc_gpiobus != NULL && 1083 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1084 return rc; 1085 1086 mutex_destroy(&sc->sc_gpio_mtx); 1087 1088 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1089 1090 return 0; 1091 } 1092 1093 static int 1094 lpcib_gpio_pin_read(void *arg, int pin) 1095 { 1096 struct lpcib_softc *sc = arg; 1097 uint32_t data; 1098 int reg, shift; 1099 1100 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1101 shift = pin % 32; 1102 1103 mutex_enter(&sc->sc_gpio_mtx); 1104 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1105 mutex_exit(&sc->sc_gpio_mtx); 1106 1107 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1108 } 1109 1110 static void 1111 lpcib_gpio_pin_write(void *arg, int pin, int value) 1112 { 1113 struct lpcib_softc *sc = arg; 1114 uint32_t data; 1115 int reg, shift; 1116 1117 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1118 shift = pin % 32; 1119 1120 mutex_enter(&sc->sc_gpio_mtx); 1121 1122 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1123 1124 if(value) 1125 data |= __BIT(shift); 1126 else 1127 data &= ~__BIT(shift); 1128 1129 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1130 1131 mutex_exit(&sc->sc_gpio_mtx); 1132 } 1133 1134 static void 1135 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1136 { 1137 struct lpcib_softc *sc = arg; 1138 uint32_t data; 1139 int reg, shift; 1140 1141 shift = pin % 32; 1142 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1143 1144 mutex_enter(&sc->sc_gpio_mtx); 1145 1146 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1147 1148 if (flags & GPIO_PIN_OUTPUT) 1149 data &= ~__BIT(shift); 1150 1151 if (flags & GPIO_PIN_INPUT) 1152 data |= __BIT(shift); 1153 1154 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1155 1156 1157 if (pin < 32) { 1158 reg = LPCIB_GPIO_GPO_BLINK; 1159 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1160 1161 if (flags & GPIO_PIN_PULSATE) 1162 data |= __BIT(shift); 1163 else 1164 data &= ~__BIT(shift); 1165 1166 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1167 } 1168 1169 mutex_exit(&sc->sc_gpio_mtx); 1170 } 1171 #endif 1172 1173 #if NFWHRNG > 0 1174 static void 1175 lpcib_fwh_configure(device_t self) 1176 { 1177 struct lpcib_softc *sc; 1178 pcireg_t pr; 1179 1180 sc = device_private(self); 1181 1182 if (sc->sc_has_rcba) { 1183 /* 1184 * Very unlikely to find a 82802 on a ICH6 or newer. 1185 * Also the write enable register moved at that point. 1186 */ 1187 return; 1188 } else { 1189 /* Enable FWH write to identify FWH. */ 1190 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1191 LPCIB_PCI_BIOS_CNTL); 1192 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1193 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1194 } 1195 1196 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1197 1198 /* restore previous write enable setting */ 1199 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1200 LPCIB_PCI_BIOS_CNTL, pr); 1201 } 1202 1203 static int 1204 lpcib_fwh_unconfigure(device_t self, int flags) 1205 { 1206 struct lpcib_softc *sc = device_private(self); 1207 int rc; 1208 1209 if (sc->sc_fwhbus != NULL && 1210 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1211 return rc; 1212 1213 return 0; 1214 } 1215 #endif 1216
Indexes created Wed Oct 01 18:09:54 GMT 2025