ichlpcib.c revision 1.16
1 /* $NetBSD: ichlpcib.c,v 1.16 2009/04/04 23:13:18 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.16 2009/04/04 23:13:18 joerg Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <machine/bus.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <dev/sysmon/sysmonvar.h> 57 58 #include <dev/ic/acpipmtimer.h> 59 #include <dev/ic/i82801lpcreg.h> 60 #include <dev/ic/hpetreg.h> 61 #include <dev/ic/hpetvar.h> 62 63 #include "hpet.h" 64 #include "pcibvar.h" 65 66 struct lpcib_softc { 67 /* we call pcibattach() which assumes this starts like this: */ 68 struct pcib_softc sc_pcib; 69 70 struct pci_attach_args sc_pa; 71 int sc_has_rcba; 72 int sc_has_ich5_hpet; 73 74 /* RCBA */ 75 bus_space_tag_t sc_rcbat; 76 bus_space_handle_t sc_rcbah; 77 pcireg_t sc_rcba_reg; 78 79 /* Watchdog variables. */ 80 struct sysmon_wdog sc_smw; 81 bus_space_tag_t sc_iot; 82 bus_space_handle_t sc_ioh; 83 84 #if NHPET > 0 85 /* HPET variables. */ 86 uint32_t sc_hpet_reg; 87 #endif 88 89 /* Speedstep */ 90 pcireg_t sc_pmcon_orig; 91 92 /* Power management */ 93 pcireg_t sc_pirq[2]; 94 pcireg_t sc_pmcon; 95 pcireg_t sc_fwhsel2; 96 }; 97 98 static int lpcibmatch(device_t, cfdata_t, void *); 99 static void lpcibattach(device_t, device_t, void *); 100 static bool lpcib_suspend(device_t PMF_FN_PROTO); 101 static bool lpcib_resume(device_t PMF_FN_PROTO); 102 static bool lpcib_shutdown(device_t, int); 103 104 static void pmtimer_configure(device_t); 105 106 static void tcotimer_configure(device_t); 107 static int tcotimer_setmode(struct sysmon_wdog *); 108 static int tcotimer_tickle(struct sysmon_wdog *); 109 static void tcotimer_stop(struct lpcib_softc *); 110 static void tcotimer_start(struct lpcib_softc *); 111 static void tcotimer_status_reset(struct lpcib_softc *); 112 static int tcotimer_disable_noreboot(device_t); 113 114 static void speedstep_configure(device_t); 115 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 116 117 #if NHPET > 0 118 static void lpcib_hpet_configure(device_t); 119 #endif 120 121 struct lpcib_softc *speedstep_cookie; /* XXX */ 122 123 CFATTACH_DECL_NEW(ichlpcib, sizeof(struct lpcib_softc), 124 lpcibmatch, lpcibattach, NULL, NULL); 125 126 static struct lpcib_device { 127 pcireg_t vendor, product; 128 int has_rcba; 129 int has_ich5_hpet; 130 } lpcib_devices[] = { 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 0, 0 }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 154 155 { 0, 0, 0, 0 }, 156 }; 157 158 /* 159 * Autoconf callbacks. 160 */ 161 static int 162 lpcibmatch(device_t parent, cfdata_t match, void *aux) 163 { 164 struct pci_attach_args *pa = aux; 165 struct lpcib_device *lpcib_dev; 166 167 /* We are ISA bridge, of course */ 168 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 169 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 170 return 0; 171 172 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 173 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 174 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 175 return 10; 176 } 177 178 return 0; 179 } 180 181 static void 182 lpcibattach(device_t parent, device_t self, void *aux) 183 { 184 struct pci_attach_args *pa = aux; 185 struct lpcib_softc *sc = device_private(self); 186 struct lpcib_device *lpcib_dev; 187 188 sc->sc_pa = *pa; 189 190 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 191 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 192 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 193 continue; 194 sc->sc_has_rcba = lpcib_dev->has_rcba; 195 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 196 break; 197 } 198 199 pcibattach(parent, self, aux); 200 201 /* 202 * Part of our I/O registers are used as ACPI PM regs. 203 * Since our ACPI subsystem accesses the I/O space directly so far, 204 * we do not have to bother bus_space I/O map confliction. 205 */ 206 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 207 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 208 aprint_error_dev(self, "can't map power management i/o space"); 209 return; 210 } 211 212 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 213 LPCIB_PCI_GEN_PMCON_1); 214 215 /* For ICH6 and later, always enable RCBA */ 216 if (sc->sc_has_rcba) { 217 pcireg_t rcba; 218 219 sc->sc_rcbat = sc->sc_pa.pa_memt; 220 221 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 222 LPCIB_RCBA); 223 if ((rcba & LPCIB_RCBA_EN) == 0) { 224 aprint_error_dev(self, "RCBA is not enabled"); 225 return; 226 } 227 rcba &= ~LPCIB_RCBA_EN; 228 229 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 230 &sc->sc_rcbah)) { 231 aprint_error_dev(self, "RCBA could not be mapped"); 232 return; 233 } 234 } 235 236 /* Set up the power management timer. */ 237 pmtimer_configure(self); 238 239 /* Set up the TCO (watchdog). */ 240 tcotimer_configure(self); 241 242 /* Set up SpeedStep. */ 243 speedstep_configure(self); 244 245 #if NHPET > 0 246 /* Set up HPET. */ 247 lpcib_hpet_configure(self); 248 #endif 249 250 /* Install power handler */ 251 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 252 lpcib_shutdown)) 253 aprint_error_dev(self, "couldn't establish power handler\n"); 254 } 255 256 static bool 257 lpcib_shutdown(device_t dv, int howto) 258 { 259 struct lpcib_softc *sc = device_private(dv); 260 261 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 262 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 263 264 return true; 265 } 266 267 static bool 268 lpcib_suspend(device_t dv PMF_FN_ARGS) 269 { 270 struct lpcib_softc *sc = device_private(dv); 271 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 272 pcitag_t tag = sc->sc_pcib.sc_tag; 273 274 /* capture PIRQ routing control registers */ 275 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 276 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 277 278 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 279 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 280 281 if (sc->sc_has_rcba) { 282 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 283 #if NHPET > 0 284 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 285 LPCIB_RCBA_HPTC); 286 #endif 287 } else if (sc->sc_has_ich5_hpet) { 288 #if NHPET > 0 289 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 290 #endif 291 } 292 293 return true; 294 } 295 296 static bool 297 lpcib_resume(device_t dv PMF_FN_ARGS) 298 { 299 struct lpcib_softc *sc = device_private(dv); 300 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 301 pcitag_t tag = sc->sc_pcib.sc_tag; 302 303 /* restore PIRQ routing control registers */ 304 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 305 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 306 307 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 308 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 309 310 if (sc->sc_has_rcba) { 311 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 312 #if NHPET > 0 313 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 314 sc->sc_hpet_reg); 315 #endif 316 } else if (sc->sc_has_ich5_hpet) { 317 #if NHPET > 0 318 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 319 #endif 320 } 321 322 return true; 323 } 324 325 /* 326 * Initialize the power management timer. 327 */ 328 static void 329 pmtimer_configure(device_t self) 330 { 331 struct lpcib_softc *sc = device_private(self); 332 pcireg_t control; 333 334 /* 335 * Check if power management I/O space is enabled and enable the ACPI_EN 336 * bit if it's disabled. 337 */ 338 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 339 LPCIB_PCI_ACPI_CNTL); 340 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 341 control |= LPCIB_PCI_ACPI_CNTL_EN; 342 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 343 LPCIB_PCI_ACPI_CNTL, control); 344 } 345 346 /* Attach our PM timer with the generic acpipmtimer function */ 347 acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 348 LPCIB_PM1_TMR, 0); 349 } 350 351 /* 352 * Initialize the watchdog timer. 353 */ 354 static void 355 tcotimer_configure(device_t self) 356 { 357 struct lpcib_softc *sc = device_private(self); 358 uint32_t ioreg; 359 unsigned int period; 360 361 /* Explicitly stop the TCO timer. */ 362 tcotimer_stop(sc); 363 364 /* 365 * Enable TCO timeout SMI only if the hardware reset does not 366 * work. We don't know what the SMBIOS does. 367 */ 368 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 369 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 370 371 /* 372 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 373 * in the SMI_EN register is the last chance. 374 */ 375 if (tcotimer_disable_noreboot(self)) { 376 ioreg |= LPCIB_SMI_EN_TCO_EN; 377 } 378 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 379 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 380 } 381 382 /* Reset the watchdog status registers. */ 383 tcotimer_status_reset(sc); 384 385 /* 386 * Register the driver with the sysmon watchdog framework. 387 */ 388 sc->sc_smw.smw_name = device_xname(self); 389 sc->sc_smw.smw_cookie = sc; 390 sc->sc_smw.smw_setmode = tcotimer_setmode; 391 sc->sc_smw.smw_tickle = tcotimer_tickle; 392 if (sc->sc_has_rcba) 393 period = LPCIB_TCOTIMER2_MAX_TICK; 394 else 395 period = LPCIB_TCOTIMER_MAX_TICK; 396 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 397 398 if (sysmon_wdog_register(&sc->sc_smw)) { 399 aprint_error_dev(self, "unable to register TCO timer" 400 "as a sysmon watchdog device.\n"); 401 return; 402 } 403 404 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 405 } 406 407 /* 408 * Sysmon watchdog callbacks. 409 */ 410 static int 411 tcotimer_setmode(struct sysmon_wdog *smw) 412 { 413 struct lpcib_softc *sc = smw->smw_cookie; 414 unsigned int period; 415 uint16_t ich6period = 0; 416 417 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 418 /* Stop the TCO timer. */ 419 tcotimer_stop(sc); 420 } else { 421 /* 422 * ICH6 or newer are limited to 2s min and 613s max. 423 * ICH5 or older are limited to 4s min and 39s max. 424 */ 425 if (sc->sc_has_rcba) { 426 if (smw->smw_period < LPCIB_TCOTIMER2_MIN_TICK || 427 smw->smw_period > LPCIB_TCOTIMER2_MAX_TICK) 428 return EINVAL; 429 } else { 430 if (smw->smw_period < LPCIB_TCOTIMER_MIN_TICK || 431 smw->smw_period > LPCIB_TCOTIMER_MAX_TICK) 432 return EINVAL; 433 } 434 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 435 436 /* Stop the TCO timer, */ 437 tcotimer_stop(sc); 438 439 /* set the timeout, */ 440 if (sc->sc_has_rcba) { 441 /* ICH6 or newer */ 442 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 443 LPCIB_TCO_TMR2); 444 ich6period &= 0xfc00; 445 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 446 LPCIB_TCO_TMR2, ich6period | period); 447 } else { 448 /* ICH5 or older */ 449 period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, 450 LPCIB_TCO_TMR); 451 period &= 0xc0; 452 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 453 LPCIB_TCO_TMR, period); 454 } 455 456 /* and start/reload the timer. */ 457 tcotimer_start(sc); 458 tcotimer_tickle(smw); 459 } 460 461 return 0; 462 } 463 464 static int 465 tcotimer_tickle(struct sysmon_wdog *smw) 466 { 467 struct lpcib_softc *sc = smw->smw_cookie; 468 469 /* any value is allowed */ 470 if (sc->sc_has_rcba) 471 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 472 else 473 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 474 475 return 0; 476 } 477 478 static void 479 tcotimer_stop(struct lpcib_softc *sc) 480 { 481 uint16_t ioreg; 482 483 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 484 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 485 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 486 } 487 488 static void 489 tcotimer_start(struct lpcib_softc *sc) 490 { 491 uint16_t ioreg; 492 493 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 494 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 495 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 496 } 497 498 static void 499 tcotimer_status_reset(struct lpcib_softc *sc) 500 { 501 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 502 LPCIB_TCO1_STS_TIMEOUT); 503 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 504 LPCIB_TCO2_STS_BOOT_STS); 505 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 506 LPCIB_TCO2_STS_SECONDS_TO_STS); 507 } 508 509 /* 510 * Clear the No Reboot (NR) bit, this enables reboots when the timer 511 * reaches the timeout for the second time. 512 */ 513 static int 514 tcotimer_disable_noreboot(device_t self) 515 { 516 struct lpcib_softc *sc = device_private(self); 517 518 if (sc->sc_has_rcba) { 519 uint32_t status; 520 521 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 522 LPCIB_GCS_OFFSET); 523 status &= ~LPCIB_GCS_NO_REBOOT; 524 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 525 LPCIB_GCS_OFFSET, status); 526 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 527 LPCIB_GCS_OFFSET); 528 if (status & LPCIB_GCS_NO_REBOOT) 529 goto error; 530 } else { 531 pcireg_t pcireg; 532 533 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 534 LPCIB_PCI_GEN_STA); 535 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 536 /* TCO timeout reset is disabled; try to enable it */ 537 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 538 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 539 LPCIB_PCI_GEN_STA, pcireg); 540 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 541 goto error; 542 } 543 } 544 545 return 0; 546 error: 547 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 548 "hope SMBIOS properly handles it.\n"); 549 return EINVAL; 550 } 551 552 553 /* 554 * Intel ICH SpeedStep support. 555 */ 556 #define SS_READ(sc, reg) \ 557 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 558 #define SS_WRITE(sc, reg, val) \ 559 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 560 561 /* 562 * Linux driver says that SpeedStep on older chipsets cause 563 * lockups on Dell Inspiron 8000 and 8100. 564 * It should also not be enabled on systems with the 82855GM 565 * Hub, which typically have an EST-enabled CPU. 566 */ 567 static int 568 speedstep_bad_hb_check(struct pci_attach_args *pa) 569 { 570 571 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 572 PCI_REVISION(pa->pa_class) < 5) 573 return 1; 574 575 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 576 return 1; 577 578 return 0; 579 } 580 581 static void 582 speedstep_configure(device_t self) 583 { 584 struct lpcib_softc *sc = device_private(self); 585 const struct sysctlnode *node, *ssnode; 586 int rv; 587 588 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 589 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 590 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 591 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 592 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 593 uint8_t pmcon; 594 595 /* Enable SpeedStep if it isn't already enabled. */ 596 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 597 LPCIB_PCI_GEN_PMCON_1); 598 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 599 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 600 LPCIB_PCI_GEN_PMCON_1, 601 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 602 603 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 604 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 605 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 606 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 607 goto err; 608 609 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 610 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 611 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 612 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 613 CTL_EOL)) != 0) 614 goto err; 615 616 /* XXX save the sc for IO tag/handle */ 617 speedstep_cookie = sc; 618 aprint_verbose_dev(self, "SpeedStep enabled\n"); 619 } 620 621 return; 622 623 err: 624 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 625 } 626 627 /* 628 * get/set the SpeedStep state: 0 == low power, 1 == high power. 629 */ 630 static int 631 speedstep_sysctl_helper(SYSCTLFN_ARGS) 632 { 633 struct sysctlnode node; 634 struct lpcib_softc *sc = speedstep_cookie; 635 uint8_t state, state2; 636 int ostate, nstate, s, error = 0; 637 638 /* 639 * We do the dance with spl's to avoid being at high ipl during 640 * sysctl_lookup() which can both copyin and copyout. 641 */ 642 s = splserial(); 643 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 644 splx(s); 645 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 646 ostate = 1; 647 else 648 ostate = 0; 649 nstate = ostate; 650 651 node = *rnode; 652 node.sysctl_data = &nstate; 653 654 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 655 if (error || newp == NULL) 656 goto out; 657 658 /* Only two states are available */ 659 if (nstate != 0 && nstate != 1) { 660 error = EINVAL; 661 goto out; 662 } 663 664 s = splserial(); 665 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 666 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 667 ostate = 1; 668 else 669 ostate = 0; 670 671 if (ostate != nstate) { 672 uint8_t cntl; 673 674 if (nstate == 0) 675 state2 |= LPCIB_PM_SS_STATE_LOW; 676 else 677 state2 &= ~LPCIB_PM_SS_STATE_LOW; 678 679 /* 680 * Must disable bus master arbitration during the change. 681 */ 682 cntl = SS_READ(sc, LPCIB_PM_CTRL); 683 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 684 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 685 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 686 } 687 splx(s); 688 out: 689 return error; 690 } 691 692 #if NHPET > 0 693 struct lpcib_hpet_attach_arg { 694 bus_space_tag_t hpet_mem_t; 695 uint32_t hpet_reg; 696 }; 697 698 static int 699 lpcib_hpet_match(device_t parent, cfdata_t match, void *aux) 700 { 701 struct lpcib_hpet_attach_arg *arg = aux; 702 bus_space_tag_t tag; 703 bus_space_handle_t handle; 704 705 tag = arg->hpet_mem_t; 706 707 if (bus_space_map(tag, arg->hpet_reg, HPET_WINDOW_SIZE, 0, &handle)) { 708 aprint_verbose_dev(parent, "HPET window not mapped, skipping\n"); 709 return 0; 710 } 711 bus_space_unmap(tag, handle, HPET_WINDOW_SIZE); 712 713 return 1; 714 } 715 716 static void 717 lpcib_hpet_attach(device_t parent, device_t self, void *aux) 718 { 719 struct hpet_softc *sc = device_private(self); 720 struct lpcib_hpet_attach_arg *arg = aux; 721 722 aprint_naive("\n"); 723 aprint_normal("\n"); 724 725 sc->sc_memt = arg->hpet_mem_t; 726 727 if (bus_space_map(sc->sc_memt, arg->hpet_reg, HPET_WINDOW_SIZE, 0, 728 &sc->sc_memh)) { 729 aprint_error_dev(self, 730 "HPET memory window could not be mapped"); 731 return; 732 } 733 734 hpet_attach_subr(self); 735 } 736 737 CFATTACH_DECL_NEW(ichlpcib_hpet, sizeof(struct hpet_softc), lpcib_hpet_match, 738 lpcib_hpet_attach, NULL, NULL); 739 740 static void 741 lpcib_hpet_configure(device_t self) 742 { 743 struct lpcib_softc *sc = device_private(self); 744 struct lpcib_hpet_attach_arg arg; 745 uint32_t hpet_reg, val; 746 747 if (sc->sc_has_ich5_hpet) { 748 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 749 LPCIB_PCI_GEN_CNTL); 750 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 751 case LPCIB_ICH5_HPTC_0000: 752 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 753 break; 754 case LPCIB_ICH5_HPTC_1000: 755 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 756 break; 757 case LPCIB_ICH5_HPTC_2000: 758 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 759 break; 760 case LPCIB_ICH5_HPTC_3000: 761 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 762 break; 763 default: 764 return; 765 } 766 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 767 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 768 LPCIB_PCI_GEN_CNTL, val); 769 } else if (sc->sc_has_rcba) { 770 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 771 LPCIB_RCBA_HPTC); 772 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 773 case LPCIB_RCBA_HPTC_0000: 774 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 775 break; 776 case LPCIB_RCBA_HPTC_1000: 777 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 778 break; 779 case LPCIB_RCBA_HPTC_2000: 780 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 781 break; 782 case LPCIB_RCBA_HPTC_3000: 783 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 784 break; 785 default: 786 return; 787 } 788 val |= LPCIB_RCBA_HPTC_EN; 789 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 790 val); 791 } else { 792 /* No HPET here */ 793 return; 794 } 795 796 arg.hpet_mem_t = sc->sc_pa.pa_memt; 797 arg.hpet_reg = hpet_reg; 798 799 config_found_ia(self, "hpetichbus", &arg, NULL); 800 } 801 #endif 802
Indexes created Tue Sep 30 10:09:55 GMT 2025