ichlpcib.c revision 1.17
1 /* $NetBSD: ichlpcib.c,v 1.17 2009/04/29 14:55:36 njoly Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.17 2009/04/29 14:55:36 njoly Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <machine/bus.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <dev/sysmon/sysmonvar.h> 57 58 #include <dev/ic/acpipmtimer.h> 59 #include <dev/ic/i82801lpcreg.h> 60 #include <dev/ic/hpetreg.h> 61 #include <dev/ic/hpetvar.h> 62 63 #include "hpet.h" 64 #include "pcibvar.h" 65 66 struct lpcib_softc { 67 /* we call pcibattach() which assumes this starts like this: */ 68 struct pcib_softc sc_pcib; 69 70 struct pci_attach_args sc_pa; 71 int sc_has_rcba; 72 int sc_has_ich5_hpet; 73 74 /* RCBA */ 75 bus_space_tag_t sc_rcbat; 76 bus_space_handle_t sc_rcbah; 77 pcireg_t sc_rcba_reg; 78 79 /* Watchdog variables. */ 80 struct sysmon_wdog sc_smw; 81 bus_space_tag_t sc_iot; 82 bus_space_handle_t sc_ioh; 83 84 #if NHPET > 0 85 /* HPET variables. */ 86 uint32_t sc_hpet_reg; 87 #endif 88 89 /* Speedstep */ 90 pcireg_t sc_pmcon_orig; 91 92 /* Power management */ 93 pcireg_t sc_pirq[2]; 94 pcireg_t sc_pmcon; 95 pcireg_t sc_fwhsel2; 96 }; 97 98 static int lpcibmatch(device_t, cfdata_t, void *); 99 static void lpcibattach(device_t, device_t, void *); 100 static bool lpcib_suspend(device_t PMF_FN_PROTO); 101 static bool lpcib_resume(device_t PMF_FN_PROTO); 102 static bool lpcib_shutdown(device_t, int); 103 104 static void pmtimer_configure(device_t); 105 106 static void tcotimer_configure(device_t); 107 static int tcotimer_setmode(struct sysmon_wdog *); 108 static int tcotimer_tickle(struct sysmon_wdog *); 109 static void tcotimer_stop(struct lpcib_softc *); 110 static void tcotimer_start(struct lpcib_softc *); 111 static void tcotimer_status_reset(struct lpcib_softc *); 112 static int tcotimer_disable_noreboot(device_t); 113 114 static void speedstep_configure(device_t); 115 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 116 117 #if NHPET > 0 118 static void lpcib_hpet_configure(device_t); 119 #endif 120 121 struct lpcib_softc *speedstep_cookie; /* XXX */ 122 123 CFATTACH_DECL_NEW(ichlpcib, sizeof(struct lpcib_softc), 124 lpcibmatch, lpcibattach, NULL, NULL); 125 126 static struct lpcib_device { 127 pcireg_t vendor, product; 128 int has_rcba; 129 int has_ich5_hpet; 130 } lpcib_devices[] = { 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 0, 0 }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 155 156 { 0, 0, 0, 0 }, 157 }; 158 159 /* 160 * Autoconf callbacks. 161 */ 162 static int 163 lpcibmatch(device_t parent, cfdata_t match, void *aux) 164 { 165 struct pci_attach_args *pa = aux; 166 struct lpcib_device *lpcib_dev; 167 168 /* We are ISA bridge, of course */ 169 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 170 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 171 return 0; 172 173 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 174 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 175 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 176 return 10; 177 } 178 179 return 0; 180 } 181 182 static void 183 lpcibattach(device_t parent, device_t self, void *aux) 184 { 185 struct pci_attach_args *pa = aux; 186 struct lpcib_softc *sc = device_private(self); 187 struct lpcib_device *lpcib_dev; 188 189 sc->sc_pa = *pa; 190 191 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 192 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 193 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 194 continue; 195 sc->sc_has_rcba = lpcib_dev->has_rcba; 196 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 197 break; 198 } 199 200 pcibattach(parent, self, aux); 201 202 /* 203 * Part of our I/O registers are used as ACPI PM regs. 204 * Since our ACPI subsystem accesses the I/O space directly so far, 205 * we do not have to bother bus_space I/O map confliction. 206 */ 207 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 208 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 209 aprint_error_dev(self, "can't map power management i/o space"); 210 return; 211 } 212 213 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 214 LPCIB_PCI_GEN_PMCON_1); 215 216 /* For ICH6 and later, always enable RCBA */ 217 if (sc->sc_has_rcba) { 218 pcireg_t rcba; 219 220 sc->sc_rcbat = sc->sc_pa.pa_memt; 221 222 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 223 LPCIB_RCBA); 224 if ((rcba & LPCIB_RCBA_EN) == 0) { 225 aprint_error_dev(self, "RCBA is not enabled"); 226 return; 227 } 228 rcba &= ~LPCIB_RCBA_EN; 229 230 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 231 &sc->sc_rcbah)) { 232 aprint_error_dev(self, "RCBA could not be mapped"); 233 return; 234 } 235 } 236 237 /* Set up the power management timer. */ 238 pmtimer_configure(self); 239 240 /* Set up the TCO (watchdog). */ 241 tcotimer_configure(self); 242 243 /* Set up SpeedStep. */ 244 speedstep_configure(self); 245 246 #if NHPET > 0 247 /* Set up HPET. */ 248 lpcib_hpet_configure(self); 249 #endif 250 251 /* Install power handler */ 252 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 253 lpcib_shutdown)) 254 aprint_error_dev(self, "couldn't establish power handler\n"); 255 } 256 257 static bool 258 lpcib_shutdown(device_t dv, int howto) 259 { 260 struct lpcib_softc *sc = device_private(dv); 261 262 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 263 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 264 265 return true; 266 } 267 268 static bool 269 lpcib_suspend(device_t dv PMF_FN_ARGS) 270 { 271 struct lpcib_softc *sc = device_private(dv); 272 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 273 pcitag_t tag = sc->sc_pcib.sc_tag; 274 275 /* capture PIRQ routing control registers */ 276 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 277 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 278 279 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 280 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 281 282 if (sc->sc_has_rcba) { 283 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 284 #if NHPET > 0 285 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 286 LPCIB_RCBA_HPTC); 287 #endif 288 } else if (sc->sc_has_ich5_hpet) { 289 #if NHPET > 0 290 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 291 #endif 292 } 293 294 return true; 295 } 296 297 static bool 298 lpcib_resume(device_t dv PMF_FN_ARGS) 299 { 300 struct lpcib_softc *sc = device_private(dv); 301 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 302 pcitag_t tag = sc->sc_pcib.sc_tag; 303 304 /* restore PIRQ routing control registers */ 305 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 306 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 307 308 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 309 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 310 311 if (sc->sc_has_rcba) { 312 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 313 #if NHPET > 0 314 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 315 sc->sc_hpet_reg); 316 #endif 317 } else if (sc->sc_has_ich5_hpet) { 318 #if NHPET > 0 319 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 320 #endif 321 } 322 323 return true; 324 } 325 326 /* 327 * Initialize the power management timer. 328 */ 329 static void 330 pmtimer_configure(device_t self) 331 { 332 struct lpcib_softc *sc = device_private(self); 333 pcireg_t control; 334 335 /* 336 * Check if power management I/O space is enabled and enable the ACPI_EN 337 * bit if it's disabled. 338 */ 339 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 340 LPCIB_PCI_ACPI_CNTL); 341 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 342 control |= LPCIB_PCI_ACPI_CNTL_EN; 343 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 344 LPCIB_PCI_ACPI_CNTL, control); 345 } 346 347 /* Attach our PM timer with the generic acpipmtimer function */ 348 acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 349 LPCIB_PM1_TMR, 0); 350 } 351 352 /* 353 * Initialize the watchdog timer. 354 */ 355 static void 356 tcotimer_configure(device_t self) 357 { 358 struct lpcib_softc *sc = device_private(self); 359 uint32_t ioreg; 360 unsigned int period; 361 362 /* Explicitly stop the TCO timer. */ 363 tcotimer_stop(sc); 364 365 /* 366 * Enable TCO timeout SMI only if the hardware reset does not 367 * work. We don't know what the SMBIOS does. 368 */ 369 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 370 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 371 372 /* 373 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 374 * in the SMI_EN register is the last chance. 375 */ 376 if (tcotimer_disable_noreboot(self)) { 377 ioreg |= LPCIB_SMI_EN_TCO_EN; 378 } 379 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 380 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 381 } 382 383 /* Reset the watchdog status registers. */ 384 tcotimer_status_reset(sc); 385 386 /* 387 * Register the driver with the sysmon watchdog framework. 388 */ 389 sc->sc_smw.smw_name = device_xname(self); 390 sc->sc_smw.smw_cookie = sc; 391 sc->sc_smw.smw_setmode = tcotimer_setmode; 392 sc->sc_smw.smw_tickle = tcotimer_tickle; 393 if (sc->sc_has_rcba) 394 period = LPCIB_TCOTIMER2_MAX_TICK; 395 else 396 period = LPCIB_TCOTIMER_MAX_TICK; 397 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 398 399 if (sysmon_wdog_register(&sc->sc_smw)) { 400 aprint_error_dev(self, "unable to register TCO timer" 401 "as a sysmon watchdog device.\n"); 402 return; 403 } 404 405 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 406 } 407 408 /* 409 * Sysmon watchdog callbacks. 410 */ 411 static int 412 tcotimer_setmode(struct sysmon_wdog *smw) 413 { 414 struct lpcib_softc *sc = smw->smw_cookie; 415 unsigned int period; 416 uint16_t ich6period = 0; 417 418 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 419 /* Stop the TCO timer. */ 420 tcotimer_stop(sc); 421 } else { 422 /* 423 * ICH6 or newer are limited to 2s min and 613s max. 424 * ICH5 or older are limited to 4s min and 39s max. 425 */ 426 if (sc->sc_has_rcba) { 427 if (smw->smw_period < LPCIB_TCOTIMER2_MIN_TICK || 428 smw->smw_period > LPCIB_TCOTIMER2_MAX_TICK) 429 return EINVAL; 430 } else { 431 if (smw->smw_period < LPCIB_TCOTIMER_MIN_TICK || 432 smw->smw_period > LPCIB_TCOTIMER_MAX_TICK) 433 return EINVAL; 434 } 435 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 436 437 /* Stop the TCO timer, */ 438 tcotimer_stop(sc); 439 440 /* set the timeout, */ 441 if (sc->sc_has_rcba) { 442 /* ICH6 or newer */ 443 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 444 LPCIB_TCO_TMR2); 445 ich6period &= 0xfc00; 446 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 447 LPCIB_TCO_TMR2, ich6period | period); 448 } else { 449 /* ICH5 or older */ 450 period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, 451 LPCIB_TCO_TMR); 452 period &= 0xc0; 453 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 454 LPCIB_TCO_TMR, period); 455 } 456 457 /* and start/reload the timer. */ 458 tcotimer_start(sc); 459 tcotimer_tickle(smw); 460 } 461 462 return 0; 463 } 464 465 static int 466 tcotimer_tickle(struct sysmon_wdog *smw) 467 { 468 struct lpcib_softc *sc = smw->smw_cookie; 469 470 /* any value is allowed */ 471 if (sc->sc_has_rcba) 472 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 473 else 474 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 475 476 return 0; 477 } 478 479 static void 480 tcotimer_stop(struct lpcib_softc *sc) 481 { 482 uint16_t ioreg; 483 484 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 485 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 486 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 487 } 488 489 static void 490 tcotimer_start(struct lpcib_softc *sc) 491 { 492 uint16_t ioreg; 493 494 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 495 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 496 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 497 } 498 499 static void 500 tcotimer_status_reset(struct lpcib_softc *sc) 501 { 502 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 503 LPCIB_TCO1_STS_TIMEOUT); 504 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 505 LPCIB_TCO2_STS_BOOT_STS); 506 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 507 LPCIB_TCO2_STS_SECONDS_TO_STS); 508 } 509 510 /* 511 * Clear the No Reboot (NR) bit, this enables reboots when the timer 512 * reaches the timeout for the second time. 513 */ 514 static int 515 tcotimer_disable_noreboot(device_t self) 516 { 517 struct lpcib_softc *sc = device_private(self); 518 519 if (sc->sc_has_rcba) { 520 uint32_t status; 521 522 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 523 LPCIB_GCS_OFFSET); 524 status &= ~LPCIB_GCS_NO_REBOOT; 525 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 526 LPCIB_GCS_OFFSET, status); 527 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 528 LPCIB_GCS_OFFSET); 529 if (status & LPCIB_GCS_NO_REBOOT) 530 goto error; 531 } else { 532 pcireg_t pcireg; 533 534 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 535 LPCIB_PCI_GEN_STA); 536 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 537 /* TCO timeout reset is disabled; try to enable it */ 538 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 539 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 540 LPCIB_PCI_GEN_STA, pcireg); 541 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 542 goto error; 543 } 544 } 545 546 return 0; 547 error: 548 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 549 "hope SMBIOS properly handles it.\n"); 550 return EINVAL; 551 } 552 553 554 /* 555 * Intel ICH SpeedStep support. 556 */ 557 #define SS_READ(sc, reg) \ 558 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 559 #define SS_WRITE(sc, reg, val) \ 560 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 561 562 /* 563 * Linux driver says that SpeedStep on older chipsets cause 564 * lockups on Dell Inspiron 8000 and 8100. 565 * It should also not be enabled on systems with the 82855GM 566 * Hub, which typically have an EST-enabled CPU. 567 */ 568 static int 569 speedstep_bad_hb_check(struct pci_attach_args *pa) 570 { 571 572 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 573 PCI_REVISION(pa->pa_class) < 5) 574 return 1; 575 576 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 577 return 1; 578 579 return 0; 580 } 581 582 static void 583 speedstep_configure(device_t self) 584 { 585 struct lpcib_softc *sc = device_private(self); 586 const struct sysctlnode *node, *ssnode; 587 int rv; 588 589 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 590 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 591 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 592 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 593 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 594 uint8_t pmcon; 595 596 /* Enable SpeedStep if it isn't already enabled. */ 597 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 598 LPCIB_PCI_GEN_PMCON_1); 599 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 600 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 601 LPCIB_PCI_GEN_PMCON_1, 602 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 603 604 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 605 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 606 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 607 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 608 goto err; 609 610 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 611 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 612 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 613 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 614 CTL_EOL)) != 0) 615 goto err; 616 617 /* XXX save the sc for IO tag/handle */ 618 speedstep_cookie = sc; 619 aprint_verbose_dev(self, "SpeedStep enabled\n"); 620 } 621 622 return; 623 624 err: 625 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 626 } 627 628 /* 629 * get/set the SpeedStep state: 0 == low power, 1 == high power. 630 */ 631 static int 632 speedstep_sysctl_helper(SYSCTLFN_ARGS) 633 { 634 struct sysctlnode node; 635 struct lpcib_softc *sc = speedstep_cookie; 636 uint8_t state, state2; 637 int ostate, nstate, s, error = 0; 638 639 /* 640 * We do the dance with spl's to avoid being at high ipl during 641 * sysctl_lookup() which can both copyin and copyout. 642 */ 643 s = splserial(); 644 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 645 splx(s); 646 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 647 ostate = 1; 648 else 649 ostate = 0; 650 nstate = ostate; 651 652 node = *rnode; 653 node.sysctl_data = &nstate; 654 655 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 656 if (error || newp == NULL) 657 goto out; 658 659 /* Only two states are available */ 660 if (nstate != 0 && nstate != 1) { 661 error = EINVAL; 662 goto out; 663 } 664 665 s = splserial(); 666 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 667 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 668 ostate = 1; 669 else 670 ostate = 0; 671 672 if (ostate != nstate) { 673 uint8_t cntl; 674 675 if (nstate == 0) 676 state2 |= LPCIB_PM_SS_STATE_LOW; 677 else 678 state2 &= ~LPCIB_PM_SS_STATE_LOW; 679 680 /* 681 * Must disable bus master arbitration during the change. 682 */ 683 cntl = SS_READ(sc, LPCIB_PM_CTRL); 684 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 685 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 686 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 687 } 688 splx(s); 689 out: 690 return error; 691 } 692 693 #if NHPET > 0 694 struct lpcib_hpet_attach_arg { 695 bus_space_tag_t hpet_mem_t; 696 uint32_t hpet_reg; 697 }; 698 699 static int 700 lpcib_hpet_match(device_t parent, cfdata_t match, void *aux) 701 { 702 struct lpcib_hpet_attach_arg *arg = aux; 703 bus_space_tag_t tag; 704 bus_space_handle_t handle; 705 706 tag = arg->hpet_mem_t; 707 708 if (bus_space_map(tag, arg->hpet_reg, HPET_WINDOW_SIZE, 0, &handle)) { 709 aprint_verbose_dev(parent, "HPET window not mapped, skipping\n"); 710 return 0; 711 } 712 bus_space_unmap(tag, handle, HPET_WINDOW_SIZE); 713 714 return 1; 715 } 716 717 static void 718 lpcib_hpet_attach(device_t parent, device_t self, void *aux) 719 { 720 struct hpet_softc *sc = device_private(self); 721 struct lpcib_hpet_attach_arg *arg = aux; 722 723 aprint_naive("\n"); 724 aprint_normal("\n"); 725 726 sc->sc_memt = arg->hpet_mem_t; 727 728 if (bus_space_map(sc->sc_memt, arg->hpet_reg, HPET_WINDOW_SIZE, 0, 729 &sc->sc_memh)) { 730 aprint_error_dev(self, 731 "HPET memory window could not be mapped"); 732 return; 733 } 734 735 hpet_attach_subr(self); 736 } 737 738 CFATTACH_DECL_NEW(ichlpcib_hpet, sizeof(struct hpet_softc), lpcib_hpet_match, 739 lpcib_hpet_attach, NULL, NULL); 740 741 static void 742 lpcib_hpet_configure(device_t self) 743 { 744 struct lpcib_softc *sc = device_private(self); 745 struct lpcib_hpet_attach_arg arg; 746 uint32_t hpet_reg, val; 747 748 if (sc->sc_has_ich5_hpet) { 749 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 750 LPCIB_PCI_GEN_CNTL); 751 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 752 case LPCIB_ICH5_HPTC_0000: 753 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 754 break; 755 case LPCIB_ICH5_HPTC_1000: 756 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 757 break; 758 case LPCIB_ICH5_HPTC_2000: 759 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 760 break; 761 case LPCIB_ICH5_HPTC_3000: 762 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 763 break; 764 default: 765 return; 766 } 767 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 768 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 769 LPCIB_PCI_GEN_CNTL, val); 770 } else if (sc->sc_has_rcba) { 771 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 772 LPCIB_RCBA_HPTC); 773 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 774 case LPCIB_RCBA_HPTC_0000: 775 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 776 break; 777 case LPCIB_RCBA_HPTC_1000: 778 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 779 break; 780 case LPCIB_RCBA_HPTC_2000: 781 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 782 break; 783 case LPCIB_RCBA_HPTC_3000: 784 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 785 break; 786 default: 787 return; 788 } 789 val |= LPCIB_RCBA_HPTC_EN; 790 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 791 val); 792 } else { 793 /* No HPET here */ 794 return; 795 } 796 797 arg.hpet_mem_t = sc->sc_pa.pa_memt; 798 arg.hpet_reg = hpet_reg; 799 800 config_found_ia(self, "hpetichbus", &arg, NULL); 801 } 802 #endif 803
Indexes created Tue Sep 30 10:09:55 GMT 2025