ichlpcib.c revision 1.2
1 /* $NetBSD: ichlpcib.c,v 1.2 2007/08/29 12:54:05 xtraeme Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 41 * 42 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 43 * some power management and monitoring functions. 44 * Currently we support the watchdog timer, SpeedStep (on some systems) 45 * and the power management timer. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.2 2007/08/29 12:54:05 xtraeme Exp $"); 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/sysctl.h> 56 #include <machine/bus.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/sysmon/sysmonvar.h> 63 64 #include <dev/ic/i82801lpcreg.h> 65 #include <dev/ic/acpipmtimer.h> 66 67 struct lpcib_softc { 68 /* Device object. */ 69 struct device sc_dev; 70 71 pci_chipset_tag_t sc_pc; 72 pcitag_t sc_pcitag; 73 74 /* Watchdog variables. */ 75 struct sysmon_wdog sc_smw; 76 bus_space_tag_t sc_iot; 77 bus_space_handle_t sc_ioh; 78 79 /* Power management */ 80 void *sc_powerhook; 81 struct pci_conf_state sc_pciconf; 82 pcireg_t sc_pirq[8]; 83 }; 84 85 static int lpcibmatch(struct device *, struct cfdata *, void *); 86 static void lpcibattach(struct device *, struct device *, void *); 87 static void lpcib_powerhook(int, void *); 88 89 static void pmtimer_configure(struct lpcib_softc *, struct pci_attach_args *); 90 91 static void tcotimer_configure(struct lpcib_softc *, struct pci_attach_args *); 92 static int tcotimer_setmode(struct sysmon_wdog *); 93 static int tcotimer_tickle(struct sysmon_wdog *); 94 static void tcotimer_stop(struct lpcib_softc *); 95 static void tcotimer_start(struct lpcib_softc *); 96 static void tcotimer_status_reset(struct lpcib_softc *); 97 static int tcotimer_disable_noreboot(struct lpcib_softc *, bus_space_tag_t, 98 bus_space_handle_t); 99 100 static void speedstep_configure(struct lpcib_softc *, struct pci_attach_args *); 101 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 102 103 struct lpcib_softc *speedstep_cookie; /* XXX */ 104 static int lpcib_ich6 = 0; 105 106 /* Defined in arch/.../pci/pcib.c. */ 107 extern void pcibattach(struct device *, struct device *, void *); 108 109 CFATTACH_DECL(ichlpcib, sizeof(struct lpcib_softc), 110 lpcibmatch, lpcibattach, NULL, NULL); 111 112 /* 113 * Autoconf callbacks. 114 */ 115 static int 116 lpcibmatch(struct device *parent, struct cfdata *match, void *aux) 117 { 118 struct pci_attach_args *pa = aux; 119 120 /* We are ISA bridge, of course */ 121 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 122 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 123 return 0; 124 125 /* Matches only Intel ICH */ 126 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 127 switch (PCI_PRODUCT(pa->pa_id)) { 128 case PCI_PRODUCT_INTEL_82801AA_LPC: /* ICH */ 129 case PCI_PRODUCT_INTEL_82801AB_LPC: /* ICH0 */ 130 case PCI_PRODUCT_INTEL_82801BA_LPC: /* ICH2 */ 131 case PCI_PRODUCT_INTEL_82801BAM_LPC: /* ICH2-M */ 132 case PCI_PRODUCT_INTEL_82801CA_LPC: /* ICH3-S */ 133 case PCI_PRODUCT_INTEL_82801CAM_LPC: /* ICH3-M */ 134 case PCI_PRODUCT_INTEL_82801DB_LPC: /* ICH4 */ 135 case PCI_PRODUCT_INTEL_82801DB_ISA: /* ICH4-M */ 136 case PCI_PRODUCT_INTEL_82801EB_LPC: /* ICH5 */ 137 return 10; 138 case PCI_PRODUCT_INTEL_82801FB_LPC: /* ICH6 */ 139 case PCI_PRODUCT_INTEL_82801FBM_LPC: /* ICH6-M */ 140 case PCI_PRODUCT_INTEL_82801G_LPC: /* ICH7 */ 141 case PCI_PRODUCT_INTEL_82801GBM_LPC: /* ICH7-M */ 142 case PCI_PRODUCT_INTEL_82801GHM_LPC: /* ICH7-M DH */ 143 case PCI_PRODUCT_INTEL_82801H_LPC: /* ICH8 */ 144 case PCI_PRODUCT_INTEL_82801HH_LPC: /* ICH8 DH */ 145 case PCI_PRODUCT_INTEL_82801HO_LPC: /* ICH8 DO */ 146 case PCI_PRODUCT_INTEL_82801IH_LPC: /* ICH9 */ 147 case PCI_PRODUCT_INTEL_82801IR_LPC: /* ICH9-R */ 148 case PCI_PRODUCT_INTEL_82801IB_LPC: /* ICH9 ? */ 149 lpcib_ich6 = 1; 150 return 10; /* prior to pcib */ 151 } 152 } 153 154 return 0; 155 } 156 157 static void 158 lpcibattach(struct device *parent, struct device *self, void *aux) 159 { 160 struct pci_attach_args *pa = aux; 161 struct lpcib_softc *sc = (void*) self; 162 163 sc->sc_pc = pa->pa_pc; 164 sc->sc_pcitag = pa->pa_tag; 165 166 pcibattach(parent, self, aux); 167 168 /* 169 * Part of our I/O registers are used as ACPI PM regs. 170 * Since our ACPI subsystem accesses the I/O space directly so far, 171 * we do not have to bother bus_space I/O map confliction. 172 */ 173 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 174 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 175 aprint_error("%s: can't map power management i/o space", 176 sc->sc_dev.dv_xname); 177 return; 178 } 179 180 /* Set up the power management timer. */ 181 pmtimer_configure(sc, pa); 182 183 /* Set up the TCO (watchdog). */ 184 tcotimer_configure(sc, pa); 185 186 /* Set up SpeedStep. */ 187 speedstep_configure(sc, pa); 188 189 /* Install powerhook */ 190 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 191 lpcib_powerhook, sc); 192 if (sc->sc_powerhook == NULL) 193 aprint_error("%s: can't establish powerhook\n", 194 sc->sc_dev.dv_xname); 195 } 196 197 static void 198 lpcib_powerhook(int why, void *opaque) 199 { 200 struct lpcib_softc *sc; 201 pci_chipset_tag_t pc; 202 pcitag_t tag; 203 204 sc = (struct lpcib_softc *)opaque; 205 pc = sc->sc_pc; 206 tag = sc->sc_pcitag; 207 208 switch (why) { 209 case PWR_SUSPEND: 210 pci_conf_capture(pc, tag, &sc->sc_pciconf); 211 212 /* capture PIRQ routing control registers */ 213 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 214 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQB_ROUT); 215 sc->sc_pirq[2] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQC_ROUT); 216 sc->sc_pirq[3] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQD_ROUT); 217 sc->sc_pirq[4] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 218 sc->sc_pirq[5] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQF_ROUT); 219 sc->sc_pirq[6] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQG_ROUT); 220 sc->sc_pirq[7] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQH_ROUT); 221 222 break; 223 224 case PWR_RESUME: 225 pci_conf_restore(pc, tag, &sc->sc_pciconf); 226 227 /* restore PIRQ routing control registers */ 228 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 229 pci_conf_write(pc, tag, LPCIB_PCI_PIRQB_ROUT, sc->sc_pirq[1]); 230 pci_conf_write(pc, tag, LPCIB_PCI_PIRQC_ROUT, sc->sc_pirq[2]); 231 pci_conf_write(pc, tag, LPCIB_PCI_PIRQD_ROUT, sc->sc_pirq[3]); 232 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[4]); 233 pci_conf_write(pc, tag, LPCIB_PCI_PIRQF_ROUT, sc->sc_pirq[5]); 234 pci_conf_write(pc, tag, LPCIB_PCI_PIRQG_ROUT, sc->sc_pirq[6]); 235 pci_conf_write(pc, tag, LPCIB_PCI_PIRQH_ROUT, sc->sc_pirq[7]); 236 237 break; 238 } 239 } 240 241 /* 242 * Initialize the power management timer. 243 */ 244 static void 245 pmtimer_configure(struct lpcib_softc *sc, struct pci_attach_args *pa) 246 { 247 pcireg_t control; 248 249 /* 250 * Check if power management I/O space is enabled and enable the ACPI_EN 251 * bit if it's disabled. 252 */ 253 control = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_PCI_ACPI_CNTL); 254 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 255 control |= LPCIB_PCI_ACPI_CNTL_EN; 256 pci_conf_write(pa->pa_pc, pa->pa_tag, LPCIB_PCI_ACPI_CNTL, 257 control); 258 } 259 260 /* Attach our PM timer with the generic acpipmtimer function */ 261 acpipmtimer_attach(&sc->sc_dev, sc->sc_iot, sc->sc_ioh, 262 LPCIB_PM1_TMR, 0); 263 } 264 265 /* 266 * Initialize the watchdog timer. 267 */ 268 static void 269 tcotimer_configure(struct lpcib_softc *sc, struct pci_attach_args *pa) 270 { 271 bus_space_handle_t gcs_memh; 272 pcireg_t pcireg; 273 uint32_t ioreg; 274 unsigned int period; 275 276 /* 277 * Map the memory space necessary for the GCS register. 278 * This is only used for ICH6 or newer, to clear the NO_REBOOT 279 * bit. 280 */ 281 if (lpcib_ich6) { 282 pcireg = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_RCBA); 283 pcireg &= 0xffffc000; 284 if (bus_space_map(pa->pa_memt, pcireg + LPCIB_GCS_OFFSET, 285 LPCIB_GCS_SIZE, 0, &gcs_memh)) { 286 aprint_error("%s: can't map GCS memory space; " 287 "TCO timer disabled\n", sc->sc_dev.dv_xname); 288 return; 289 } 290 } 291 292 /* 293 * Clear the NO_REBOOT bit. If this fails, enabling the TCO_EN bit 294 * in the SMI_EN register is the last chance. 295 */ 296 if (tcotimer_disable_noreboot(sc, pa->pa_memt, gcs_memh)) { 297 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 298 ioreg |= LPCIB_SMI_EN_TCO_EN; 299 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 300 } 301 302 /* Reset the watchdog status registers. */ 303 tcotimer_status_reset(sc); 304 305 /* Explicitly stop the TCO timer. */ 306 tcotimer_stop(sc); 307 308 /* 309 * Register the driver with the sysmon watchdog framework. 310 */ 311 sc->sc_smw.smw_name = sc->sc_dev.dv_xname; 312 sc->sc_smw.smw_cookie = sc; 313 sc->sc_smw.smw_setmode = tcotimer_setmode; 314 sc->sc_smw.smw_tickle = tcotimer_tickle; 315 if (lpcib_ich6) 316 period = LPCIB_TCOTIMER2_MAX_TICK; 317 else 318 period = LPCIB_TCOTIMER_MAX_TICK; 319 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 320 321 if (sysmon_wdog_register(&sc->sc_smw)) { 322 aprint_error("%s: unable to register TCO timer" 323 "as a sysmon watchdog device.\n", 324 sc->sc_dev.dv_xname); 325 return; 326 } 327 328 aprint_verbose("%s: TCO (watchdog) timer configured.\n", 329 sc->sc_dev.dv_xname); 330 } 331 332 /* 333 * Sysmon watchdog callbacks. 334 */ 335 static int 336 tcotimer_setmode(struct sysmon_wdog *smw) 337 { 338 struct lpcib_softc *sc = smw->smw_cookie; 339 unsigned int period; 340 uint16_t ich6period = 0; 341 342 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 343 /* Stop the TCO timer. */ 344 tcotimer_stop(sc); 345 } else { 346 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 347 /* 348 * ICH5 or older are limited to 4s min and 39s max. 349 * ICH6 or newer are limited to 2s min and 613s max. 350 */ 351 if (!lpcib_ich6) { 352 if (period < LPCIB_TCOTIMER_MIN_TICK || 353 period > LPCIB_TCOTIMER_MAX_TICK) 354 return EINVAL; 355 } else { 356 if (period < LPCIB_TCOTIMER2_MIN_TICK || 357 period > LPCIB_TCOTIMER2_MAX_TICK) 358 return EINVAL; 359 } 360 361 /* Stop the TCO timer, */ 362 tcotimer_stop(sc); 363 364 /* set the timeout, */ 365 if (lpcib_ich6) { 366 /* ICH6 or newer */ 367 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 368 LPCIB_TCO_TMR2); 369 ich6period &= 0xfc00; 370 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 371 LPCIB_TCO_TMR2, ich6period | period); 372 } else { 373 /* ICH5 or older */ 374 period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, 375 LPCIB_TCO_TMR); 376 period &= 0xc0; 377 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 378 LPCIB_TCO_TMR, period); 379 } 380 381 /* and start/reload the timer. */ 382 tcotimer_start(sc); 383 tcotimer_tickle(smw); 384 } 385 386 return 0; 387 } 388 389 static int 390 tcotimer_tickle(struct sysmon_wdog *smw) 391 { 392 struct lpcib_softc *sc = smw->smw_cookie; 393 394 /* any value is allowed */ 395 if (!lpcib_ich6) 396 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 397 else 398 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 399 400 return 0; 401 } 402 403 static void 404 tcotimer_stop(struct lpcib_softc *sc) 405 { 406 uint16_t ioreg; 407 408 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 409 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 410 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 411 } 412 413 static void 414 tcotimer_start(struct lpcib_softc *sc) 415 { 416 uint16_t ioreg; 417 418 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 419 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 420 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 421 } 422 423 static void 424 tcotimer_status_reset(struct lpcib_softc *sc) 425 { 426 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 427 LPCIB_TCO1_STS_TIMEOUT); 428 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 429 LPCIB_TCO2_STS_BOOT_STS); 430 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 431 LPCIB_TCO2_STS_SECONDS_TO_STS); 432 } 433 434 /* 435 * Clear the NO_REBOOT bit, this enables reboots. 436 */ 437 static int 438 tcotimer_disable_noreboot(struct lpcib_softc *sc, bus_space_tag_t gcs_memt, 439 bus_space_handle_t gcs_memh) 440 { 441 pcireg_t pcireg; 442 uint16_t status = 0; 443 444 if (!lpcib_ich6) { 445 pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 446 LPCIB_PCI_GEN_STA); 447 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 448 /* TCO timeout reset is disabled; try to enable it */ 449 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 450 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 451 LPCIB_PCI_GEN_STA, pcireg); 452 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 453 goto error; 454 } 455 } else { 456 status = bus_space_read_4(gcs_memt, gcs_memh, 0); 457 status &= ~LPCIB_GCS_NO_REBOOT; 458 bus_space_write_4(gcs_memt, gcs_memh, 0, status); 459 status = bus_space_read_4(gcs_memt, gcs_memh, 0); 460 bus_space_unmap(gcs_memt, gcs_memh, LPCIB_GCS_SIZE); 461 if (status & LPCIB_GCS_NO_REBOOT) 462 goto error; 463 } 464 465 return 0; 466 error: 467 aprint_error("%s: TCO timer reboot disabled by hardware; " 468 "hope SMBIOS properly handles it.\n", sc->sc_dev.dv_xname); 469 return EINVAL; 470 } 471 472 473 /* 474 * Intel ICH SpeedStep support. 475 */ 476 #define SS_READ(sc, reg) \ 477 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 478 #define SS_WRITE(sc, reg, val) \ 479 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 480 481 /* 482 * Linux driver says that SpeedStep on older chipsets cause 483 * lockups on Dell Inspiron 8000 and 8100. 484 */ 485 static int 486 speedstep_bad_hb_check(struct pci_attach_args *pa) 487 { 488 489 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 490 PCI_REVISION(pa->pa_class) < 5) 491 return 1; 492 493 return 0; 494 } 495 496 static void 497 speedstep_configure(struct lpcib_softc *sc, struct pci_attach_args *pa) 498 { 499 const struct sysctlnode *node, *ssnode; 500 int rv; 501 502 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 503 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 504 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 505 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 506 pci_find_device(pa, speedstep_bad_hb_check) == 0)) { 507 uint8_t pmcon; 508 509 /* Enable SpeedStep if it isn't already enabled. */ 510 pmcon = pci_conf_read(pa->pa_pc, pa->pa_tag, 511 LPCIB_PCI_GEN_PMCON_1); 512 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 513 pci_conf_write(pa->pa_pc, pa->pa_tag, 514 LPCIB_PCI_GEN_PMCON_1, 515 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 516 517 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 518 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 519 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 520 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 521 goto err; 522 523 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 524 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 525 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 526 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 527 CTL_EOL)) != 0) 528 goto err; 529 530 /* XXX save the sc for IO tag/handle */ 531 speedstep_cookie = sc; 532 aprint_verbose("%s: SpeedStep enabled\n", sc->sc_dev.dv_xname); 533 } 534 535 return; 536 537 err: 538 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 539 } 540 541 /* 542 * get/set the SpeedStep state: 0 == low power, 1 == high power. 543 */ 544 static int 545 speedstep_sysctl_helper(SYSCTLFN_ARGS) 546 { 547 struct sysctlnode node; 548 struct lpcib_softc *sc = speedstep_cookie; 549 uint8_t state, state2; 550 int ostate, nstate, s, error = 0; 551 552 /* 553 * We do the dance with spl's to avoid being at high ipl during 554 * sysctl_lookup() which can both copyin and copyout. 555 */ 556 s = splserial(); 557 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 558 splx(s); 559 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 560 ostate = 1; 561 else 562 ostate = 0; 563 nstate = ostate; 564 565 node = *rnode; 566 node.sysctl_data = &nstate; 567 568 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 569 if (error || newp == NULL) 570 goto out; 571 572 /* Only two states are available */ 573 if (nstate != 0 && nstate != 1) { 574 error = EINVAL; 575 goto out; 576 } 577 578 s = splserial(); 579 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 580 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 581 ostate = 1; 582 else 583 ostate = 0; 584 585 if (ostate != nstate) { 586 uint8_t cntl; 587 588 if (nstate == 0) 589 state2 |= LPCIB_PM_SS_STATE_LOW; 590 else 591 state2 &= ~LPCIB_PM_SS_STATE_LOW; 592 593 /* 594 * Must disable bus master arbitration during the change. 595 */ 596 cntl = SS_READ(sc, LPCIB_PM_CTRL); 597 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 598 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 599 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 600 } 601 splx(s); 602 out: 603 return error; 604 } 605
Indexes created Tue Sep 30 20:09:53 GMT 2025