ichlpcib.c revision 1.20
1 /* $NetBSD: ichlpcib.c,v 1.20 2009/09/27 17:55:31 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.20 2009/09/27 17:55:31 jakllsch Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <machine/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/hpetreg.h> 63 #include <dev/ic/hpetvar.h> 64 65 #include "hpet.h" 66 #include "pcibvar.h" 67 #include "gpio.h" 68 69 #define LPCIB_GPIO_NPINS 64 70 71 struct lpcib_softc { 72 /* we call pcibattach() which assumes this starts like this: */ 73 struct pcib_softc sc_pcib; 74 75 struct pci_attach_args sc_pa; 76 int sc_has_rcba; 77 int sc_has_ich5_hpet; 78 79 /* RCBA */ 80 bus_space_tag_t sc_rcbat; 81 bus_space_handle_t sc_rcbah; 82 pcireg_t sc_rcba_reg; 83 84 /* Watchdog variables. */ 85 struct sysmon_wdog sc_smw; 86 bus_space_tag_t sc_iot; 87 bus_space_handle_t sc_ioh; 88 bus_size_t sc_iosize; 89 90 #if NHPET > 0 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 #endif 94 95 #if NGPIO > 0 96 device_t sc_gpiobus; 97 kmutex_t sc_gpio_mtx; 98 bus_space_tag_t sc_gpio_iot; 99 bus_space_handle_t sc_gpio_ioh; 100 bus_size_t sc_gpio_ios; 101 struct gpio_chipset_tag sc_gpio_gc; 102 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 103 #endif 104 105 /* Speedstep */ 106 pcireg_t sc_pmcon_orig; 107 108 /* Power management */ 109 pcireg_t sc_pirq[2]; 110 pcireg_t sc_pmcon; 111 pcireg_t sc_fwhsel2; 112 113 /* Child devices */ 114 device_t sc_hpetbus; 115 acpipmtimer_t sc_pmtimer; 116 pcireg_t sc_acpi_cntl; 117 118 struct sysctllog *sc_log; 119 }; 120 121 static int lpcibmatch(device_t, cfdata_t, void *); 122 static void lpcibattach(device_t, device_t, void *); 123 static int lpcibdetach(device_t, int); 124 static void lpcibchilddet(device_t, device_t); 125 static int lpcibrescan(device_t, const char *, const int *); 126 static bool lpcib_suspend(device_t PMF_FN_PROTO); 127 static bool lpcib_resume(device_t PMF_FN_PROTO); 128 static bool lpcib_shutdown(device_t, int); 129 130 static void pmtimer_configure(device_t); 131 static int pmtimer_unconfigure(device_t, int); 132 133 static void tcotimer_configure(device_t); 134 static int tcotimer_unconfigure(device_t, int); 135 static int tcotimer_setmode(struct sysmon_wdog *); 136 static int tcotimer_tickle(struct sysmon_wdog *); 137 static void tcotimer_stop(struct lpcib_softc *); 138 static void tcotimer_start(struct lpcib_softc *); 139 static void tcotimer_status_reset(struct lpcib_softc *); 140 static int tcotimer_disable_noreboot(device_t); 141 142 static void speedstep_configure(device_t); 143 static void speedstep_unconfigure(device_t); 144 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 145 146 #if NHPET > 0 147 static void lpcib_hpet_configure(device_t); 148 static int lpcib_hpet_unconfigure(device_t, int); 149 #endif 150 151 #if NGPIO > 0 152 static void lpcib_gpio_configure(device_t); 153 static int lpcib_gpio_unconfigure(device_t, int); 154 static int lpcib_gpio_pin_read(void *, int); 155 static void lpcib_gpio_pin_write(void *, int, int); 156 static void lpcib_gpio_pin_ctl(void *, int, int); 157 #endif 158 159 struct lpcib_softc *speedstep_cookie; /* XXX */ 160 161 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 162 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 163 164 static struct lpcib_device { 165 pcireg_t vendor, product; 166 int has_rcba; 167 int has_ich5_hpet; 168 } lpcib_devices[] = { 169 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 170 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 171 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 172 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 173 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 174 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 0, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 193 194 { 0, 0, 0, 0 }, 195 }; 196 197 /* 198 * Autoconf callbacks. 199 */ 200 static int 201 lpcibmatch(device_t parent, cfdata_t match, void *aux) 202 { 203 struct pci_attach_args *pa = aux; 204 struct lpcib_device *lpcib_dev; 205 206 /* We are ISA bridge, of course */ 207 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 208 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 209 return 0; 210 211 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 212 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 213 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 214 return 10; 215 } 216 217 return 0; 218 } 219 220 static void 221 lpcibattach(device_t parent, device_t self, void *aux) 222 { 223 struct pci_attach_args *pa = aux; 224 struct lpcib_softc *sc = device_private(self); 225 struct lpcib_device *lpcib_dev; 226 227 sc->sc_pa = *pa; 228 229 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 230 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 231 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 232 continue; 233 sc->sc_has_rcba = lpcib_dev->has_rcba; 234 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 235 break; 236 } 237 238 pcibattach(parent, self, aux); 239 240 /* 241 * Part of our I/O registers are used as ACPI PM regs. 242 * Since our ACPI subsystem accesses the I/O space directly so far, 243 * we do not have to bother bus_space I/O map confliction. 244 */ 245 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 246 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_iosize)) { 247 aprint_error_dev(self, "can't map power management i/o space"); 248 return; 249 } 250 251 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 252 LPCIB_PCI_GEN_PMCON_1); 253 254 /* For ICH6 and later, always enable RCBA */ 255 if (sc->sc_has_rcba) { 256 pcireg_t rcba; 257 258 sc->sc_rcbat = sc->sc_pa.pa_memt; 259 260 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 261 LPCIB_RCBA); 262 if ((rcba & LPCIB_RCBA_EN) == 0) { 263 aprint_error_dev(self, "RCBA is not enabled"); 264 return; 265 } 266 rcba &= ~LPCIB_RCBA_EN; 267 268 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 269 &sc->sc_rcbah)) { 270 aprint_error_dev(self, "RCBA could not be mapped"); 271 return; 272 } 273 } 274 275 /* Set up the power management timer. */ 276 pmtimer_configure(self); 277 278 /* Set up the TCO (watchdog). */ 279 tcotimer_configure(self); 280 281 /* Set up SpeedStep. */ 282 speedstep_configure(self); 283 284 #if NHPET > 0 285 /* Set up HPET. */ 286 lpcib_hpet_configure(self); 287 #endif 288 289 #if NGPIO > 0 290 /* Set up GPIO */ 291 lpcib_gpio_configure(self); 292 #endif 293 294 /* Install power handler */ 295 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 296 lpcib_shutdown)) 297 aprint_error_dev(self, "couldn't establish power handler\n"); 298 } 299 300 static void 301 lpcibchilddet(device_t self, device_t child) 302 { 303 struct lpcib_softc *sc = device_private(self); 304 uint32_t val; 305 306 if (sc->sc_gpiobus == child) { 307 sc->sc_gpiobus = NULL; 308 return; 309 } 310 if (sc->sc_hpetbus != child) { 311 pcibchilddet(self, child); 312 return; 313 } 314 sc->sc_hpetbus = NULL; 315 if (sc->sc_has_ich5_hpet) { 316 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 317 LPCIB_PCI_GEN_CNTL); 318 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 319 case LPCIB_ICH5_HPTC_0000: 320 case LPCIB_ICH5_HPTC_1000: 321 case LPCIB_ICH5_HPTC_2000: 322 case LPCIB_ICH5_HPTC_3000: 323 break; 324 default: 325 return; 326 } 327 val &= ~LPCIB_ICH5_HPTC_EN; 328 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 329 LPCIB_PCI_GEN_CNTL, val); 330 } else if (sc->sc_has_rcba) { 331 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 332 LPCIB_RCBA_HPTC); 333 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 334 case LPCIB_RCBA_HPTC_0000: 335 case LPCIB_RCBA_HPTC_1000: 336 case LPCIB_RCBA_HPTC_2000: 337 case LPCIB_RCBA_HPTC_3000: 338 break; 339 default: 340 return; 341 } 342 val &= ~LPCIB_RCBA_HPTC_EN; 343 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 344 val); 345 } 346 } 347 348 #if NHPET > 0 || NGPIO > 0 349 /* XXX share this with sys/arch/i386/pci/elan520.c */ 350 static bool 351 ifattr_match(const char *snull, const char *t) 352 { 353 return (snull == NULL) || strcmp(snull, t) == 0; 354 } 355 #endif 356 357 static int 358 lpcibrescan(device_t self, const char *ifattr, const int *locators) 359 { 360 #if NHPET > 0 || NGPIO > 0 361 struct lpcib_softc *sc = device_private(self); 362 #endif 363 364 #if NHPET > 0 365 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 366 lpcib_hpet_configure(self); 367 #endif 368 369 #if NGPIO > 0 370 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 371 lpcib_gpio_configure(self); 372 #endif 373 374 return pcibrescan(self, ifattr, locators); 375 } 376 377 static int 378 lpcibdetach(device_t self, int flags) 379 { 380 struct lpcib_softc *sc = device_private(self); 381 int rc; 382 383 pmf_device_deregister(self); 384 385 #if NHPET > 0 386 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 387 return rc; 388 #endif 389 390 #if NGPIO > 0 391 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 392 return rc; 393 #endif 394 395 /* Set up SpeedStep. */ 396 speedstep_unconfigure(self); 397 398 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 399 return rc; 400 401 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 402 return rc; 403 404 if (sc->sc_has_rcba) 405 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 406 407 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 408 409 return pcibdetach(self, flags); 410 } 411 412 static bool 413 lpcib_shutdown(device_t dv, int howto) 414 { 415 struct lpcib_softc *sc = device_private(dv); 416 417 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 418 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 419 420 return true; 421 } 422 423 static bool 424 lpcib_suspend(device_t dv PMF_FN_ARGS) 425 { 426 struct lpcib_softc *sc = device_private(dv); 427 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 428 pcitag_t tag = sc->sc_pcib.sc_tag; 429 430 /* capture PIRQ routing control registers */ 431 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 432 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 433 434 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 435 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 436 437 if (sc->sc_has_rcba) { 438 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 439 #if NHPET > 0 440 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 441 LPCIB_RCBA_HPTC); 442 #endif 443 } else if (sc->sc_has_ich5_hpet) { 444 #if NHPET > 0 445 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 446 #endif 447 } 448 449 return true; 450 } 451 452 static bool 453 lpcib_resume(device_t dv PMF_FN_ARGS) 454 { 455 struct lpcib_softc *sc = device_private(dv); 456 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 457 pcitag_t tag = sc->sc_pcib.sc_tag; 458 459 /* restore PIRQ routing control registers */ 460 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 461 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 462 463 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 464 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 465 466 if (sc->sc_has_rcba) { 467 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 468 #if NHPET > 0 469 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 470 sc->sc_hpet_reg); 471 #endif 472 } else if (sc->sc_has_ich5_hpet) { 473 #if NHPET > 0 474 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 475 #endif 476 } 477 478 return true; 479 } 480 481 /* 482 * Initialize the power management timer. 483 */ 484 static void 485 pmtimer_configure(device_t self) 486 { 487 struct lpcib_softc *sc = device_private(self); 488 pcireg_t control; 489 490 /* 491 * Check if power management I/O space is enabled and enable the ACPI_EN 492 * bit if it's disabled. 493 */ 494 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 495 LPCIB_PCI_ACPI_CNTL); 496 sc->sc_acpi_cntl = control; 497 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 498 control |= LPCIB_PCI_ACPI_CNTL_EN; 499 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 500 LPCIB_PCI_ACPI_CNTL, control); 501 } 502 503 /* Attach our PM timer with the generic acpipmtimer function */ 504 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 505 LPCIB_PM1_TMR, 0); 506 } 507 508 static int 509 pmtimer_unconfigure(device_t self, int flags) 510 { 511 struct lpcib_softc *sc = device_private(self); 512 int rc; 513 514 if (sc->sc_pmtimer != NULL && 515 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 516 return rc; 517 518 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 519 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 520 521 return 0; 522 } 523 524 /* 525 * Initialize the watchdog timer. 526 */ 527 static void 528 tcotimer_configure(device_t self) 529 { 530 struct lpcib_softc *sc = device_private(self); 531 uint32_t ioreg; 532 unsigned int period; 533 534 /* Explicitly stop the TCO timer. */ 535 tcotimer_stop(sc); 536 537 /* 538 * Enable TCO timeout SMI only if the hardware reset does not 539 * work. We don't know what the SMBIOS does. 540 */ 541 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 542 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 543 544 /* 545 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 546 * in the SMI_EN register is the last chance. 547 */ 548 if (tcotimer_disable_noreboot(self)) { 549 ioreg |= LPCIB_SMI_EN_TCO_EN; 550 } 551 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 552 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 553 } 554 555 /* Reset the watchdog status registers. */ 556 tcotimer_status_reset(sc); 557 558 /* 559 * Register the driver with the sysmon watchdog framework. 560 */ 561 sc->sc_smw.smw_name = device_xname(self); 562 sc->sc_smw.smw_cookie = sc; 563 sc->sc_smw.smw_setmode = tcotimer_setmode; 564 sc->sc_smw.smw_tickle = tcotimer_tickle; 565 if (sc->sc_has_rcba) 566 period = LPCIB_TCOTIMER2_MAX_TICK; 567 else 568 period = LPCIB_TCOTIMER_MAX_TICK; 569 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 570 571 if (sysmon_wdog_register(&sc->sc_smw)) { 572 aprint_error_dev(self, "unable to register TCO timer" 573 "as a sysmon watchdog device.\n"); 574 return; 575 } 576 577 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 578 } 579 580 static int 581 tcotimer_unconfigure(device_t self, int flags) 582 { 583 struct lpcib_softc *sc = device_private(self); 584 int rc; 585 586 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 587 if (rc == ERESTART) 588 rc = EINTR; 589 return rc; 590 } 591 592 /* Explicitly stop the TCO timer. */ 593 tcotimer_stop(sc); 594 595 /* XXX Set No Reboot? */ 596 597 return 0; 598 } 599 600 601 /* 602 * Sysmon watchdog callbacks. 603 */ 604 static int 605 tcotimer_setmode(struct sysmon_wdog *smw) 606 { 607 struct lpcib_softc *sc = smw->smw_cookie; 608 unsigned int period; 609 uint16_t ich6period = 0; 610 uint8_t ich5period = 0; 611 612 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 613 /* Stop the TCO timer. */ 614 tcotimer_stop(sc); 615 } else { 616 /* 617 * ICH6 or newer are limited to 2s min and 613s max. 618 * ICH5 or older are limited to 4s min and 39s max. 619 */ 620 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 621 if (sc->sc_has_rcba) { 622 if (period < LPCIB_TCOTIMER2_MIN_TICK || 623 period > LPCIB_TCOTIMER2_MAX_TICK) 624 return EINVAL; 625 } else { 626 if (period < LPCIB_TCOTIMER_MIN_TICK || 627 period > LPCIB_TCOTIMER_MAX_TICK) 628 return EINVAL; 629 } 630 631 /* Stop the TCO timer, */ 632 tcotimer_stop(sc); 633 634 /* set the timeout, */ 635 if (sc->sc_has_rcba) { 636 /* ICH6 or newer */ 637 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 638 LPCIB_TCO_TMR2); 639 ich6period &= 0xfc00; 640 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 641 LPCIB_TCO_TMR2, ich6period | period); 642 } else { 643 /* ICH5 or older */ 644 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 645 LPCIB_TCO_TMR); 646 ich5period &= 0xc0; 647 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 648 LPCIB_TCO_TMR, ich5period | period); 649 } 650 651 /* and start/reload the timer. */ 652 tcotimer_start(sc); 653 tcotimer_tickle(smw); 654 } 655 656 return 0; 657 } 658 659 static int 660 tcotimer_tickle(struct sysmon_wdog *smw) 661 { 662 struct lpcib_softc *sc = smw->smw_cookie; 663 664 /* any value is allowed */ 665 if (sc->sc_has_rcba) 666 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 667 else 668 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 669 670 return 0; 671 } 672 673 static void 674 tcotimer_stop(struct lpcib_softc *sc) 675 { 676 uint16_t ioreg; 677 678 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 679 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 680 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 681 } 682 683 static void 684 tcotimer_start(struct lpcib_softc *sc) 685 { 686 uint16_t ioreg; 687 688 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 689 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 690 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 691 } 692 693 static void 694 tcotimer_status_reset(struct lpcib_softc *sc) 695 { 696 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 697 LPCIB_TCO1_STS_TIMEOUT); 698 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 699 LPCIB_TCO2_STS_BOOT_STS); 700 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 701 LPCIB_TCO2_STS_SECONDS_TO_STS); 702 } 703 704 /* 705 * Clear the No Reboot (NR) bit, this enables reboots when the timer 706 * reaches the timeout for the second time. 707 */ 708 static int 709 tcotimer_disable_noreboot(device_t self) 710 { 711 struct lpcib_softc *sc = device_private(self); 712 713 if (sc->sc_has_rcba) { 714 uint32_t status; 715 716 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 717 LPCIB_GCS_OFFSET); 718 status &= ~LPCIB_GCS_NO_REBOOT; 719 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 720 LPCIB_GCS_OFFSET, status); 721 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 722 LPCIB_GCS_OFFSET); 723 if (status & LPCIB_GCS_NO_REBOOT) 724 goto error; 725 } else { 726 pcireg_t pcireg; 727 728 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 729 LPCIB_PCI_GEN_STA); 730 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 731 /* TCO timeout reset is disabled; try to enable it */ 732 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 733 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 734 LPCIB_PCI_GEN_STA, pcireg); 735 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 736 goto error; 737 } 738 } 739 740 return 0; 741 error: 742 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 743 "hope SMBIOS properly handles it.\n"); 744 return EINVAL; 745 } 746 747 748 /* 749 * Intel ICH SpeedStep support. 750 */ 751 #define SS_READ(sc, reg) \ 752 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 753 #define SS_WRITE(sc, reg, val) \ 754 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 755 756 /* 757 * Linux driver says that SpeedStep on older chipsets cause 758 * lockups on Dell Inspiron 8000 and 8100. 759 * It should also not be enabled on systems with the 82855GM 760 * Hub, which typically have an EST-enabled CPU. 761 */ 762 static int 763 speedstep_bad_hb_check(struct pci_attach_args *pa) 764 { 765 766 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 767 PCI_REVISION(pa->pa_class) < 5) 768 return 1; 769 770 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 771 return 1; 772 773 return 0; 774 } 775 776 static void 777 speedstep_configure(device_t self) 778 { 779 struct lpcib_softc *sc = device_private(self); 780 const struct sysctlnode *node, *ssnode; 781 int rv; 782 783 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 784 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 785 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 786 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 787 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 788 pcireg_t pmcon; 789 790 /* Enable SpeedStep if it isn't already enabled. */ 791 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 792 LPCIB_PCI_GEN_PMCON_1); 793 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 794 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 795 LPCIB_PCI_GEN_PMCON_1, 796 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 797 798 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 799 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 800 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 801 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 802 goto err; 803 804 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 805 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 806 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 807 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 808 CTL_EOL)) != 0) 809 goto err; 810 811 /* XXX save the sc for IO tag/handle */ 812 speedstep_cookie = sc; 813 aprint_verbose_dev(self, "SpeedStep enabled\n"); 814 } 815 816 return; 817 818 err: 819 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 820 } 821 822 static void 823 speedstep_unconfigure(device_t self) 824 { 825 struct lpcib_softc *sc = device_private(self); 826 827 sysctl_teardown(&sc->sc_log); 828 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 829 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 830 831 speedstep_cookie = NULL; 832 } 833 834 /* 835 * get/set the SpeedStep state: 0 == low power, 1 == high power. 836 */ 837 static int 838 speedstep_sysctl_helper(SYSCTLFN_ARGS) 839 { 840 struct sysctlnode node; 841 struct lpcib_softc *sc = speedstep_cookie; 842 uint8_t state, state2; 843 int ostate, nstate, s, error = 0; 844 845 /* 846 * We do the dance with spl's to avoid being at high ipl during 847 * sysctl_lookup() which can both copyin and copyout. 848 */ 849 s = splserial(); 850 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 851 splx(s); 852 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 853 ostate = 1; 854 else 855 ostate = 0; 856 nstate = ostate; 857 858 node = *rnode; 859 node.sysctl_data = &nstate; 860 861 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 862 if (error || newp == NULL) 863 goto out; 864 865 /* Only two states are available */ 866 if (nstate != 0 && nstate != 1) { 867 error = EINVAL; 868 goto out; 869 } 870 871 s = splserial(); 872 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 873 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 874 ostate = 1; 875 else 876 ostate = 0; 877 878 if (ostate != nstate) { 879 uint8_t cntl; 880 881 if (nstate == 0) 882 state2 |= LPCIB_PM_SS_STATE_LOW; 883 else 884 state2 &= ~LPCIB_PM_SS_STATE_LOW; 885 886 /* 887 * Must disable bus master arbitration during the change. 888 */ 889 cntl = SS_READ(sc, LPCIB_PM_CTRL); 890 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 891 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 892 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 893 } 894 splx(s); 895 out: 896 return error; 897 } 898 899 #if NHPET > 0 900 struct lpcib_hpet_attach_arg { 901 bus_space_tag_t hpet_mem_t; 902 uint32_t hpet_reg; 903 }; 904 905 static int 906 lpcib_hpet_match(device_t parent, cfdata_t match, void *aux) 907 { 908 struct lpcib_hpet_attach_arg *arg = aux; 909 bus_space_tag_t tag; 910 bus_space_handle_t handle; 911 912 tag = arg->hpet_mem_t; 913 914 if (bus_space_map(tag, arg->hpet_reg, HPET_WINDOW_SIZE, 0, &handle)) { 915 aprint_verbose_dev(parent, "HPET window not mapped, skipping\n"); 916 return 0; 917 } 918 bus_space_unmap(tag, handle, HPET_WINDOW_SIZE); 919 920 return 1; 921 } 922 923 static int 924 lpcib_hpet_detach(device_t self, int flags) 925 { 926 struct hpet_softc *sc = device_private(self); 927 int rc; 928 929 if ((rc = hpet_detach(self, flags)) != 0) 930 return rc; 931 932 bus_space_unmap(sc->sc_memt, sc->sc_memh, HPET_WINDOW_SIZE); 933 934 return 0; 935 } 936 937 static void 938 lpcib_hpet_attach(device_t parent, device_t self, void *aux) 939 { 940 struct hpet_softc *sc = device_private(self); 941 struct lpcib_hpet_attach_arg *arg = aux; 942 943 aprint_naive("\n"); 944 aprint_normal("\n"); 945 946 sc->sc_memt = arg->hpet_mem_t; 947 948 if (bus_space_map(sc->sc_memt, arg->hpet_reg, HPET_WINDOW_SIZE, 0, 949 &sc->sc_memh)) { 950 aprint_error_dev(self, 951 "HPET memory window could not be mapped"); 952 return; 953 } 954 955 hpet_attach_subr(self); 956 } 957 958 CFATTACH_DECL_NEW(ichlpcib_hpet, sizeof(struct hpet_softc), lpcib_hpet_match, 959 lpcib_hpet_attach, lpcib_hpet_detach, NULL); 960 961 static void 962 lpcib_hpet_configure(device_t self) 963 { 964 struct lpcib_softc *sc = device_private(self); 965 struct lpcib_hpet_attach_arg arg; 966 uint32_t hpet_reg, val; 967 968 if (sc->sc_has_ich5_hpet) { 969 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 970 LPCIB_PCI_GEN_CNTL); 971 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 972 case LPCIB_ICH5_HPTC_0000: 973 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 974 break; 975 case LPCIB_ICH5_HPTC_1000: 976 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 977 break; 978 case LPCIB_ICH5_HPTC_2000: 979 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 980 break; 981 case LPCIB_ICH5_HPTC_3000: 982 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 983 break; 984 default: 985 return; 986 } 987 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 988 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 989 LPCIB_PCI_GEN_CNTL, val); 990 } else if (sc->sc_has_rcba) { 991 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 992 LPCIB_RCBA_HPTC); 993 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 994 case LPCIB_RCBA_HPTC_0000: 995 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 996 break; 997 case LPCIB_RCBA_HPTC_1000: 998 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 999 break; 1000 case LPCIB_RCBA_HPTC_2000: 1001 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 1002 break; 1003 case LPCIB_RCBA_HPTC_3000: 1004 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 1005 break; 1006 default: 1007 return; 1008 } 1009 val |= LPCIB_RCBA_HPTC_EN; 1010 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 1011 val); 1012 } else { 1013 /* No HPET here */ 1014 return; 1015 } 1016 1017 arg.hpet_mem_t = sc->sc_pa.pa_memt; 1018 arg.hpet_reg = hpet_reg; 1019 1020 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 1021 } 1022 1023 static int 1024 lpcib_hpet_unconfigure(device_t self, int flags) 1025 { 1026 struct lpcib_softc *sc = device_private(self); 1027 int rc; 1028 1029 if (sc->sc_hpetbus != NULL && 1030 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1031 return rc; 1032 1033 return 0; 1034 } 1035 #endif 1036 1037 #if NGPIO > 0 1038 static void 1039 lpcib_gpio_configure(device_t self) 1040 { 1041 struct lpcib_softc *sc = device_private(self); 1042 struct gpiobus_attach_args gba; 1043 pcireg_t gpio_cntl; 1044 uint32_t use, io, bit; 1045 int pin, shift, base_reg, cntl_reg, reg; 1046 1047 /* this implies ICH >= 6, and thus different mapreg */ 1048 if (sc->sc_has_rcba) { 1049 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1050 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1051 } else { 1052 base_reg = LPCIB_PCI_GPIO_BASE; 1053 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1054 } 1055 1056 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1057 cntl_reg); 1058 1059 /* Is GPIO enabled? */ 1060 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1061 return; 1062 1063 if (pci_mapreg_map(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0, 1064 &sc->sc_gpio_iot, &sc->sc_gpio_ioh, 1065 NULL, &sc->sc_gpio_ios)) { 1066 aprint_error_dev(self, "can't map general purpose i/o space\n"); 1067 return; 1068 } 1069 1070 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1071 1072 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1073 sc->sc_gpio_pins[pin].pin_num = pin; 1074 1075 /* Read initial state */ 1076 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1077 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1078 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1079 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1080 shift = pin % 32; 1081 bit = __BIT(shift); 1082 1083 if ((use & bit) != 0) { 1084 sc->sc_gpio_pins[pin].pin_caps = 1085 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1086 if (pin < 32) 1087 sc->sc_gpio_pins[pin].pin_caps |= 1088 GPIO_PIN_PULSATE; 1089 if ((io & bit) != 0) 1090 sc->sc_gpio_pins[pin].pin_flags = 1091 GPIO_PIN_INPUT; 1092 else 1093 sc->sc_gpio_pins[pin].pin_flags = 1094 GPIO_PIN_OUTPUT; 1095 } else 1096 sc->sc_gpio_pins[pin].pin_caps = 0; 1097 1098 if (lpcib_gpio_pin_read(sc, pin) == 0) 1099 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1100 else 1101 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1102 1103 } 1104 1105 /* Create controller tag */ 1106 sc->sc_gpio_gc.gp_cookie = sc; 1107 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1108 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1109 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1110 1111 memset(&gba, 0, sizeof(gba)); 1112 1113 gba.gba_gc = &sc->sc_gpio_gc; 1114 gba.gba_pins = sc->sc_gpio_pins; 1115 gba.gba_npins = LPCIB_GPIO_NPINS; 1116 1117 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1118 } 1119 1120 static int 1121 lpcib_gpio_unconfigure(device_t self, int flags) 1122 { 1123 struct lpcib_softc *sc = device_private(self); 1124 int rc; 1125 1126 if (sc->sc_gpiobus != NULL && 1127 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1128 return rc; 1129 1130 mutex_destroy(&sc->sc_gpio_mtx); 1131 1132 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1133 1134 return 0; 1135 } 1136 1137 static int 1138 lpcib_gpio_pin_read(void *arg, int pin) 1139 { 1140 struct lpcib_softc *sc = arg; 1141 uint32_t data; 1142 int reg, shift; 1143 1144 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1145 shift = pin % 32; 1146 1147 mutex_enter(&sc->sc_gpio_mtx); 1148 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1149 mutex_exit(&sc->sc_gpio_mtx); 1150 1151 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1152 } 1153 1154 static void 1155 lpcib_gpio_pin_write(void *arg, int pin, int value) 1156 { 1157 struct lpcib_softc *sc = arg; 1158 uint32_t data; 1159 int reg, shift; 1160 1161 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1162 shift = pin % 32; 1163 1164 mutex_enter(&sc->sc_gpio_mtx); 1165 1166 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1167 1168 if(value) 1169 data |= __BIT(shift); 1170 else 1171 data &= ~__BIT(shift); 1172 1173 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1174 1175 mutex_exit(&sc->sc_gpio_mtx); 1176 } 1177 1178 static void 1179 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1180 { 1181 struct lpcib_softc *sc = arg; 1182 uint32_t data; 1183 int reg, shift; 1184 1185 shift = pin % 32; 1186 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1187 1188 mutex_enter(&sc->sc_gpio_mtx); 1189 1190 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1191 1192 if (flags & GPIO_PIN_OUTPUT) 1193 data &= ~__BIT(shift); 1194 1195 if (flags & GPIO_PIN_INPUT) 1196 data |= __BIT(shift); 1197 1198 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1199 1200 1201 if (pin < 32) { 1202 reg = LPCIB_GPIO_GPO_BLINK; 1203 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1204 1205 if (flags & GPIO_PIN_PULSATE) 1206 data |= __BIT(shift); 1207 else 1208 data &= ~__BIT(shift); 1209 1210 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1211 } 1212 1213 mutex_exit(&sc->sc_gpio_mtx); 1214 } 1215 #endif 1216
Indexes created Tue Sep 30 11:09:46 GMT 2025