ichlpcib.c revision 1.26
1 /* $NetBSD: ichlpcib.c,v 1.26 2010/07/23 02:23:58 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.26 2010/07/23 02:23:58 jakllsch Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <machine/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/hpetreg.h> 63 #include <dev/ic/hpetvar.h> 64 65 #include "hpet.h" 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 #if NHPET > 0 92 /* HPET variables. */ 93 uint32_t sc_hpet_reg; 94 #endif 95 96 #if NGPIO > 0 97 device_t sc_gpiobus; 98 kmutex_t sc_gpio_mtx; 99 bus_space_tag_t sc_gpio_iot; 100 bus_space_handle_t sc_gpio_ioh; 101 bus_size_t sc_gpio_ios; 102 struct gpio_chipset_tag sc_gpio_gc; 103 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 104 #endif 105 106 #if NFWHRNG > 0 107 device_t sc_fwhbus; 108 #endif 109 110 /* Speedstep */ 111 pcireg_t sc_pmcon_orig; 112 113 /* Power management */ 114 pcireg_t sc_pirq[2]; 115 pcireg_t sc_pmcon; 116 pcireg_t sc_fwhsel2; 117 118 /* Child devices */ 119 device_t sc_hpetbus; 120 acpipmtimer_t sc_pmtimer; 121 pcireg_t sc_acpi_cntl; 122 123 struct sysctllog *sc_log; 124 }; 125 126 static int lpcibmatch(device_t, cfdata_t, void *); 127 static void lpcibattach(device_t, device_t, void *); 128 static int lpcibdetach(device_t, int); 129 static void lpcibchilddet(device_t, device_t); 130 static int lpcibrescan(device_t, const char *, const int *); 131 static bool lpcib_suspend(device_t, const pmf_qual_t *); 132 static bool lpcib_resume(device_t, const pmf_qual_t *); 133 static bool lpcib_shutdown(device_t, int); 134 135 static void pmtimer_configure(device_t); 136 static int pmtimer_unconfigure(device_t, int); 137 138 static void tcotimer_configure(device_t); 139 static int tcotimer_unconfigure(device_t, int); 140 static int tcotimer_setmode(struct sysmon_wdog *); 141 static int tcotimer_tickle(struct sysmon_wdog *); 142 static void tcotimer_stop(struct lpcib_softc *); 143 static void tcotimer_start(struct lpcib_softc *); 144 static void tcotimer_status_reset(struct lpcib_softc *); 145 static int tcotimer_disable_noreboot(device_t); 146 147 static void speedstep_configure(device_t); 148 static void speedstep_unconfigure(device_t); 149 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 150 151 #if NHPET > 0 152 static void lpcib_hpet_configure(device_t); 153 static int lpcib_hpet_unconfigure(device_t, int); 154 #endif 155 156 #if NGPIO > 0 157 static void lpcib_gpio_configure(device_t); 158 static int lpcib_gpio_unconfigure(device_t, int); 159 static int lpcib_gpio_pin_read(void *, int); 160 static void lpcib_gpio_pin_write(void *, int, int); 161 static void lpcib_gpio_pin_ctl(void *, int, int); 162 #endif 163 164 #if NFWHRNG > 0 165 static void lpcib_fwh_configure(device_t); 166 static int lpcib_fwh_unconfigure(device_t, int); 167 #endif 168 169 struct lpcib_softc *speedstep_cookie; /* XXX */ 170 171 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 172 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 173 174 static struct lpcib_device { 175 pcireg_t vendor, product; 176 int has_rcba; 177 int has_ich5_hpet; 178 } lpcib_devices[] = { 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 0, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 203 204 { 0, 0, 0, 0 }, 205 }; 206 207 /* 208 * Autoconf callbacks. 209 */ 210 static int 211 lpcibmatch(device_t parent, cfdata_t match, void *aux) 212 { 213 struct pci_attach_args *pa = aux; 214 struct lpcib_device *lpcib_dev; 215 216 /* We are ISA bridge, of course */ 217 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 218 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 219 return 0; 220 221 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 222 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 223 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 224 return 10; 225 } 226 227 return 0; 228 } 229 230 static void 231 lpcibattach(device_t parent, device_t self, void *aux) 232 { 233 struct pci_attach_args *pa = aux; 234 struct lpcib_softc *sc = device_private(self); 235 struct lpcib_device *lpcib_dev; 236 237 sc->sc_pa = *pa; 238 239 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 240 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 241 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 242 continue; 243 sc->sc_has_rcba = lpcib_dev->has_rcba; 244 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 245 break; 246 } 247 248 pcibattach(parent, self, aux); 249 250 /* 251 * Part of our I/O registers are used as ACPI PM regs. 252 * Since our ACPI subsystem accesses the I/O space directly so far, 253 * we do not have to bother bus_space I/O map confliction. 254 */ 255 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 256 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_iosize)) { 257 aprint_error_dev(self, "can't map power management i/o space"); 258 return; 259 } 260 261 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 262 LPCIB_PCI_GEN_PMCON_1); 263 264 /* For ICH6 and later, always enable RCBA */ 265 if (sc->sc_has_rcba) { 266 pcireg_t rcba; 267 268 sc->sc_rcbat = sc->sc_pa.pa_memt; 269 270 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 271 LPCIB_RCBA); 272 if ((rcba & LPCIB_RCBA_EN) == 0) { 273 aprint_error_dev(self, "RCBA is not enabled"); 274 return; 275 } 276 rcba &= ~LPCIB_RCBA_EN; 277 278 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 279 &sc->sc_rcbah)) { 280 aprint_error_dev(self, "RCBA could not be mapped"); 281 return; 282 } 283 } 284 285 /* Set up the power management timer. */ 286 pmtimer_configure(self); 287 288 /* Set up the TCO (watchdog). */ 289 tcotimer_configure(self); 290 291 /* Set up SpeedStep. */ 292 speedstep_configure(self); 293 294 #if NHPET > 0 295 /* Set up HPET. */ 296 lpcib_hpet_configure(self); 297 #endif 298 299 #if NGPIO > 0 300 /* Set up GPIO */ 301 lpcib_gpio_configure(self); 302 #endif 303 304 #if NFWHRNG > 0 305 lpcib_fwh_configure(self); 306 #endif 307 308 /* Install power handler */ 309 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 310 lpcib_shutdown)) 311 aprint_error_dev(self, "couldn't establish power handler\n"); 312 } 313 314 static void 315 lpcibchilddet(device_t self, device_t child) 316 { 317 struct lpcib_softc *sc = device_private(self); 318 uint32_t val; 319 320 #if NFWHRNG > 0 321 if (sc->sc_fwhbus == child) { 322 sc->sc_fwhbus = NULL; 323 return; 324 } 325 #endif 326 #if NGPIO > 0 327 if (sc->sc_gpiobus == child) { 328 sc->sc_gpiobus = NULL; 329 return; 330 } 331 #endif 332 if (sc->sc_hpetbus != child) { 333 pcibchilddet(self, child); 334 return; 335 } 336 sc->sc_hpetbus = NULL; 337 if (sc->sc_has_ich5_hpet) { 338 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 339 LPCIB_PCI_GEN_CNTL); 340 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 341 case LPCIB_ICH5_HPTC_0000: 342 case LPCIB_ICH5_HPTC_1000: 343 case LPCIB_ICH5_HPTC_2000: 344 case LPCIB_ICH5_HPTC_3000: 345 break; 346 default: 347 return; 348 } 349 val &= ~LPCIB_ICH5_HPTC_EN; 350 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 351 LPCIB_PCI_GEN_CNTL, val); 352 } else if (sc->sc_has_rcba) { 353 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 354 LPCIB_RCBA_HPTC); 355 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 356 case LPCIB_RCBA_HPTC_0000: 357 case LPCIB_RCBA_HPTC_1000: 358 case LPCIB_RCBA_HPTC_2000: 359 case LPCIB_RCBA_HPTC_3000: 360 break; 361 default: 362 return; 363 } 364 val &= ~LPCIB_RCBA_HPTC_EN; 365 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 366 val); 367 } 368 } 369 370 static int 371 lpcibrescan(device_t self, const char *ifattr, const int *locators) 372 { 373 #if NHPET > 0 || NGPIO > 0 374 struct lpcib_softc *sc = device_private(self); 375 #endif 376 377 #if NFWHRNG > 0 378 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 379 lpcib_fwh_configure(self); 380 #endif 381 382 #if NHPET > 0 383 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 384 lpcib_hpet_configure(self); 385 #endif 386 387 #if NGPIO > 0 388 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 389 lpcib_gpio_configure(self); 390 #endif 391 392 return pcibrescan(self, ifattr, locators); 393 } 394 395 static int 396 lpcibdetach(device_t self, int flags) 397 { 398 struct lpcib_softc *sc = device_private(self); 399 int rc; 400 401 pmf_device_deregister(self); 402 403 #if NFWHRNG > 0 404 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 405 return rc; 406 #endif 407 408 #if NHPET > 0 409 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 410 return rc; 411 #endif 412 413 #if NGPIO > 0 414 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 415 return rc; 416 #endif 417 418 /* Set up SpeedStep. */ 419 speedstep_unconfigure(self); 420 421 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 422 return rc; 423 424 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 425 return rc; 426 427 if (sc->sc_has_rcba) 428 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 429 430 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 431 432 return pcibdetach(self, flags); 433 } 434 435 static bool 436 lpcib_shutdown(device_t dv, int howto) 437 { 438 struct lpcib_softc *sc = device_private(dv); 439 440 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 441 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 442 443 return true; 444 } 445 446 static bool 447 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 448 { 449 struct lpcib_softc *sc = device_private(dv); 450 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 451 pcitag_t tag = sc->sc_pcib.sc_tag; 452 453 /* capture PIRQ routing control registers */ 454 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 455 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 456 457 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 458 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 459 460 if (sc->sc_has_rcba) { 461 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 462 #if NHPET > 0 463 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 464 LPCIB_RCBA_HPTC); 465 #endif 466 } else if (sc->sc_has_ich5_hpet) { 467 #if NHPET > 0 468 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 469 #endif 470 } 471 472 return true; 473 } 474 475 static bool 476 lpcib_resume(device_t dv, const pmf_qual_t *qual) 477 { 478 struct lpcib_softc *sc = device_private(dv); 479 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 480 pcitag_t tag = sc->sc_pcib.sc_tag; 481 482 /* restore PIRQ routing control registers */ 483 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 484 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 485 486 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 487 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 488 489 if (sc->sc_has_rcba) { 490 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 491 #if NHPET > 0 492 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 493 sc->sc_hpet_reg); 494 #endif 495 } else if (sc->sc_has_ich5_hpet) { 496 #if NHPET > 0 497 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 498 #endif 499 } 500 501 return true; 502 } 503 504 /* 505 * Initialize the power management timer. 506 */ 507 static void 508 pmtimer_configure(device_t self) 509 { 510 struct lpcib_softc *sc = device_private(self); 511 pcireg_t control; 512 513 /* 514 * Check if power management I/O space is enabled and enable the ACPI_EN 515 * bit if it's disabled. 516 */ 517 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 518 LPCIB_PCI_ACPI_CNTL); 519 sc->sc_acpi_cntl = control; 520 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 521 control |= LPCIB_PCI_ACPI_CNTL_EN; 522 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 523 LPCIB_PCI_ACPI_CNTL, control); 524 } 525 526 /* Attach our PM timer with the generic acpipmtimer function */ 527 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 528 LPCIB_PM1_TMR, 0); 529 } 530 531 static int 532 pmtimer_unconfigure(device_t self, int flags) 533 { 534 struct lpcib_softc *sc = device_private(self); 535 int rc; 536 537 if (sc->sc_pmtimer != NULL && 538 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 539 return rc; 540 541 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 542 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 543 544 return 0; 545 } 546 547 /* 548 * Initialize the watchdog timer. 549 */ 550 static void 551 tcotimer_configure(device_t self) 552 { 553 struct lpcib_softc *sc = device_private(self); 554 uint32_t ioreg; 555 unsigned int period; 556 557 /* Explicitly stop the TCO timer. */ 558 tcotimer_stop(sc); 559 560 /* 561 * Enable TCO timeout SMI only if the hardware reset does not 562 * work. We don't know what the SMBIOS does. 563 */ 564 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 565 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 566 567 /* 568 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 569 * in the SMI_EN register is the last chance. 570 */ 571 if (tcotimer_disable_noreboot(self)) { 572 ioreg |= LPCIB_SMI_EN_TCO_EN; 573 } 574 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 575 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 576 } 577 578 /* Reset the watchdog status registers. */ 579 tcotimer_status_reset(sc); 580 581 /* 582 * Register the driver with the sysmon watchdog framework. 583 */ 584 sc->sc_smw.smw_name = device_xname(self); 585 sc->sc_smw.smw_cookie = sc; 586 sc->sc_smw.smw_setmode = tcotimer_setmode; 587 sc->sc_smw.smw_tickle = tcotimer_tickle; 588 if (sc->sc_has_rcba) 589 period = LPCIB_TCOTIMER2_MAX_TICK; 590 else 591 period = LPCIB_TCOTIMER_MAX_TICK; 592 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 593 594 if (sysmon_wdog_register(&sc->sc_smw)) { 595 aprint_error_dev(self, "unable to register TCO timer" 596 "as a sysmon watchdog device.\n"); 597 return; 598 } 599 600 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 601 } 602 603 static int 604 tcotimer_unconfigure(device_t self, int flags) 605 { 606 struct lpcib_softc *sc = device_private(self); 607 int rc; 608 609 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 610 if (rc == ERESTART) 611 rc = EINTR; 612 return rc; 613 } 614 615 /* Explicitly stop the TCO timer. */ 616 tcotimer_stop(sc); 617 618 /* XXX Set No Reboot? */ 619 620 return 0; 621 } 622 623 624 /* 625 * Sysmon watchdog callbacks. 626 */ 627 static int 628 tcotimer_setmode(struct sysmon_wdog *smw) 629 { 630 struct lpcib_softc *sc = smw->smw_cookie; 631 unsigned int period; 632 uint16_t ich6period = 0; 633 uint8_t ich5period = 0; 634 635 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 636 /* Stop the TCO timer. */ 637 tcotimer_stop(sc); 638 } else { 639 /* 640 * ICH6 or newer are limited to 2s min and 613s max. 641 * ICH5 or older are limited to 4s min and 39s max. 642 */ 643 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 644 if (sc->sc_has_rcba) { 645 if (period < LPCIB_TCOTIMER2_MIN_TICK || 646 period > LPCIB_TCOTIMER2_MAX_TICK) 647 return EINVAL; 648 } else { 649 if (period < LPCIB_TCOTIMER_MIN_TICK || 650 period > LPCIB_TCOTIMER_MAX_TICK) 651 return EINVAL; 652 } 653 654 /* Stop the TCO timer, */ 655 tcotimer_stop(sc); 656 657 /* set the timeout, */ 658 if (sc->sc_has_rcba) { 659 /* ICH6 or newer */ 660 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 661 LPCIB_TCO_TMR2); 662 ich6period &= 0xfc00; 663 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 664 LPCIB_TCO_TMR2, ich6period | period); 665 } else { 666 /* ICH5 or older */ 667 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 668 LPCIB_TCO_TMR); 669 ich5period &= 0xc0; 670 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 671 LPCIB_TCO_TMR, ich5period | period); 672 } 673 674 /* and start/reload the timer. */ 675 tcotimer_start(sc); 676 tcotimer_tickle(smw); 677 } 678 679 return 0; 680 } 681 682 static int 683 tcotimer_tickle(struct sysmon_wdog *smw) 684 { 685 struct lpcib_softc *sc = smw->smw_cookie; 686 687 /* any value is allowed */ 688 if (sc->sc_has_rcba) 689 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 690 else 691 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 692 693 return 0; 694 } 695 696 static void 697 tcotimer_stop(struct lpcib_softc *sc) 698 { 699 uint16_t ioreg; 700 701 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 702 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 703 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 704 } 705 706 static void 707 tcotimer_start(struct lpcib_softc *sc) 708 { 709 uint16_t ioreg; 710 711 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 712 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 713 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 714 } 715 716 static void 717 tcotimer_status_reset(struct lpcib_softc *sc) 718 { 719 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 720 LPCIB_TCO1_STS_TIMEOUT); 721 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 722 LPCIB_TCO2_STS_BOOT_STS); 723 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 724 LPCIB_TCO2_STS_SECONDS_TO_STS); 725 } 726 727 /* 728 * Clear the No Reboot (NR) bit, this enables reboots when the timer 729 * reaches the timeout for the second time. 730 */ 731 static int 732 tcotimer_disable_noreboot(device_t self) 733 { 734 struct lpcib_softc *sc = device_private(self); 735 736 if (sc->sc_has_rcba) { 737 uint32_t status; 738 739 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 740 LPCIB_GCS_OFFSET); 741 status &= ~LPCIB_GCS_NO_REBOOT; 742 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 743 LPCIB_GCS_OFFSET, status); 744 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 745 LPCIB_GCS_OFFSET); 746 if (status & LPCIB_GCS_NO_REBOOT) 747 goto error; 748 } else { 749 pcireg_t pcireg; 750 751 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 752 LPCIB_PCI_GEN_STA); 753 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 754 /* TCO timeout reset is disabled; try to enable it */ 755 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 756 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 757 LPCIB_PCI_GEN_STA, pcireg); 758 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 759 goto error; 760 } 761 } 762 763 return 0; 764 error: 765 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 766 "hope SMBIOS properly handles it.\n"); 767 return EINVAL; 768 } 769 770 771 /* 772 * Intel ICH SpeedStep support. 773 */ 774 #define SS_READ(sc, reg) \ 775 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 776 #define SS_WRITE(sc, reg, val) \ 777 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 778 779 /* 780 * Linux driver says that SpeedStep on older chipsets cause 781 * lockups on Dell Inspiron 8000 and 8100. 782 * It should also not be enabled on systems with the 82855GM 783 * Hub, which typically have an EST-enabled CPU. 784 */ 785 static int 786 speedstep_bad_hb_check(struct pci_attach_args *pa) 787 { 788 789 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 790 PCI_REVISION(pa->pa_class) < 5) 791 return 1; 792 793 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 794 return 1; 795 796 return 0; 797 } 798 799 static void 800 speedstep_configure(device_t self) 801 { 802 struct lpcib_softc *sc = device_private(self); 803 const struct sysctlnode *node, *ssnode; 804 int rv; 805 806 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 807 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 808 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 809 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 810 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 811 pcireg_t pmcon; 812 813 /* Enable SpeedStep if it isn't already enabled. */ 814 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 815 LPCIB_PCI_GEN_PMCON_1); 816 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 817 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 818 LPCIB_PCI_GEN_PMCON_1, 819 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 820 821 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 822 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 823 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 824 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 825 goto err; 826 827 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 828 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 829 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 830 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 831 CTL_EOL)) != 0) 832 goto err; 833 834 /* XXX save the sc for IO tag/handle */ 835 speedstep_cookie = sc; 836 aprint_verbose_dev(self, "SpeedStep enabled\n"); 837 } 838 839 return; 840 841 err: 842 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 843 } 844 845 static void 846 speedstep_unconfigure(device_t self) 847 { 848 struct lpcib_softc *sc = device_private(self); 849 850 sysctl_teardown(&sc->sc_log); 851 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 852 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 853 854 speedstep_cookie = NULL; 855 } 856 857 /* 858 * get/set the SpeedStep state: 0 == low power, 1 == high power. 859 */ 860 static int 861 speedstep_sysctl_helper(SYSCTLFN_ARGS) 862 { 863 struct sysctlnode node; 864 struct lpcib_softc *sc = speedstep_cookie; 865 uint8_t state, state2; 866 int ostate, nstate, s, error = 0; 867 868 /* 869 * We do the dance with spl's to avoid being at high ipl during 870 * sysctl_lookup() which can both copyin and copyout. 871 */ 872 s = splserial(); 873 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 874 splx(s); 875 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 876 ostate = 1; 877 else 878 ostate = 0; 879 nstate = ostate; 880 881 node = *rnode; 882 node.sysctl_data = &nstate; 883 884 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 885 if (error || newp == NULL) 886 goto out; 887 888 /* Only two states are available */ 889 if (nstate != 0 && nstate != 1) { 890 error = EINVAL; 891 goto out; 892 } 893 894 s = splserial(); 895 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 896 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 897 ostate = 1; 898 else 899 ostate = 0; 900 901 if (ostate != nstate) { 902 uint8_t cntl; 903 904 if (nstate == 0) 905 state2 |= LPCIB_PM_SS_STATE_LOW; 906 else 907 state2 &= ~LPCIB_PM_SS_STATE_LOW; 908 909 /* 910 * Must disable bus master arbitration during the change. 911 */ 912 cntl = SS_READ(sc, LPCIB_PM_CTRL); 913 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 914 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 915 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 916 } 917 splx(s); 918 out: 919 return error; 920 } 921 922 #if NHPET > 0 923 struct lpcib_hpet_attach_arg { 924 bus_space_tag_t hpet_mem_t; 925 uint32_t hpet_reg; 926 }; 927 928 static int 929 lpcib_hpet_match(device_t parent, cfdata_t match, void *aux) 930 { 931 struct lpcib_hpet_attach_arg *arg = aux; 932 bus_space_tag_t tag; 933 bus_space_handle_t handle; 934 935 tag = arg->hpet_mem_t; 936 937 if (bus_space_map(tag, arg->hpet_reg, HPET_WINDOW_SIZE, 0, &handle)) { 938 aprint_verbose_dev(parent, "HPET window not mapped, skipping\n"); 939 return 0; 940 } 941 bus_space_unmap(tag, handle, HPET_WINDOW_SIZE); 942 943 return 1; 944 } 945 946 static int 947 lpcib_hpet_detach(device_t self, int flags) 948 { 949 struct hpet_softc *sc = device_private(self); 950 int rc; 951 952 if ((rc = hpet_detach(self, flags)) != 0) 953 return rc; 954 955 bus_space_unmap(sc->sc_memt, sc->sc_memh, HPET_WINDOW_SIZE); 956 957 return 0; 958 } 959 960 static void 961 lpcib_hpet_attach(device_t parent, device_t self, void *aux) 962 { 963 struct hpet_softc *sc = device_private(self); 964 struct lpcib_hpet_attach_arg *arg = aux; 965 966 aprint_naive("\n"); 967 aprint_normal("\n"); 968 969 sc->sc_memt = arg->hpet_mem_t; 970 971 if (bus_space_map(sc->sc_memt, arg->hpet_reg, HPET_WINDOW_SIZE, 0, 972 &sc->sc_memh)) { 973 aprint_error_dev(self, 974 "HPET memory window could not be mapped"); 975 return; 976 } 977 978 hpet_attach_subr(self); 979 } 980 981 CFATTACH_DECL_NEW(ichlpcib_hpet, sizeof(struct hpet_softc), lpcib_hpet_match, 982 lpcib_hpet_attach, lpcib_hpet_detach, NULL); 983 984 static void 985 lpcib_hpet_configure(device_t self) 986 { 987 struct lpcib_softc *sc = device_private(self); 988 struct lpcib_hpet_attach_arg arg; 989 uint32_t hpet_reg, val; 990 991 if (sc->sc_has_ich5_hpet) { 992 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 993 LPCIB_PCI_GEN_CNTL); 994 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 995 case LPCIB_ICH5_HPTC_0000: 996 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 997 break; 998 case LPCIB_ICH5_HPTC_1000: 999 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 1000 break; 1001 case LPCIB_ICH5_HPTC_2000: 1002 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 1003 break; 1004 case LPCIB_ICH5_HPTC_3000: 1005 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 1006 break; 1007 default: 1008 return; 1009 } 1010 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 1011 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1012 LPCIB_PCI_GEN_CNTL, val); 1013 } else if (sc->sc_has_rcba) { 1014 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 1015 LPCIB_RCBA_HPTC); 1016 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 1017 case LPCIB_RCBA_HPTC_0000: 1018 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 1019 break; 1020 case LPCIB_RCBA_HPTC_1000: 1021 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 1022 break; 1023 case LPCIB_RCBA_HPTC_2000: 1024 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 1025 break; 1026 case LPCIB_RCBA_HPTC_3000: 1027 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 1028 break; 1029 default: 1030 return; 1031 } 1032 val |= LPCIB_RCBA_HPTC_EN; 1033 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 1034 val); 1035 } else { 1036 /* No HPET here */ 1037 return; 1038 } 1039 1040 arg.hpet_mem_t = sc->sc_pa.pa_memt; 1041 arg.hpet_reg = hpet_reg; 1042 1043 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 1044 } 1045 1046 static int 1047 lpcib_hpet_unconfigure(device_t self, int flags) 1048 { 1049 struct lpcib_softc *sc = device_private(self); 1050 int rc; 1051 1052 if (sc->sc_hpetbus != NULL && 1053 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1054 return rc; 1055 1056 return 0; 1057 } 1058 #endif 1059 1060 #if NGPIO > 0 1061 static void 1062 lpcib_gpio_configure(device_t self) 1063 { 1064 struct lpcib_softc *sc = device_private(self); 1065 struct gpiobus_attach_args gba; 1066 pcireg_t gpio_cntl; 1067 uint32_t use, io, bit; 1068 int pin, shift, base_reg, cntl_reg, reg; 1069 1070 /* this implies ICH >= 6, and thus different mapreg */ 1071 if (sc->sc_has_rcba) { 1072 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1073 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1074 } else { 1075 base_reg = LPCIB_PCI_GPIO_BASE; 1076 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1077 } 1078 1079 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1080 cntl_reg); 1081 1082 /* Is GPIO enabled? */ 1083 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1084 return; 1085 1086 if (pci_mapreg_map(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0, 1087 &sc->sc_gpio_iot, &sc->sc_gpio_ioh, 1088 NULL, &sc->sc_gpio_ios)) { 1089 aprint_error_dev(self, "can't map general purpose i/o space\n"); 1090 return; 1091 } 1092 1093 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1094 1095 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1096 sc->sc_gpio_pins[pin].pin_num = pin; 1097 1098 /* Read initial state */ 1099 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1100 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1101 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1102 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1103 shift = pin % 32; 1104 bit = __BIT(shift); 1105 1106 if ((use & bit) != 0) { 1107 sc->sc_gpio_pins[pin].pin_caps = 1108 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1109 if (pin < 32) 1110 sc->sc_gpio_pins[pin].pin_caps |= 1111 GPIO_PIN_PULSATE; 1112 if ((io & bit) != 0) 1113 sc->sc_gpio_pins[pin].pin_flags = 1114 GPIO_PIN_INPUT; 1115 else 1116 sc->sc_gpio_pins[pin].pin_flags = 1117 GPIO_PIN_OUTPUT; 1118 } else 1119 sc->sc_gpio_pins[pin].pin_caps = 0; 1120 1121 if (lpcib_gpio_pin_read(sc, pin) == 0) 1122 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1123 else 1124 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1125 1126 } 1127 1128 /* Create controller tag */ 1129 sc->sc_gpio_gc.gp_cookie = sc; 1130 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1131 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1132 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1133 1134 memset(&gba, 0, sizeof(gba)); 1135 1136 gba.gba_gc = &sc->sc_gpio_gc; 1137 gba.gba_pins = sc->sc_gpio_pins; 1138 gba.gba_npins = LPCIB_GPIO_NPINS; 1139 1140 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1141 } 1142 1143 static int 1144 lpcib_gpio_unconfigure(device_t self, int flags) 1145 { 1146 struct lpcib_softc *sc = device_private(self); 1147 int rc; 1148 1149 if (sc->sc_gpiobus != NULL && 1150 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1151 return rc; 1152 1153 mutex_destroy(&sc->sc_gpio_mtx); 1154 1155 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1156 1157 return 0; 1158 } 1159 1160 static int 1161 lpcib_gpio_pin_read(void *arg, int pin) 1162 { 1163 struct lpcib_softc *sc = arg; 1164 uint32_t data; 1165 int reg, shift; 1166 1167 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1168 shift = pin % 32; 1169 1170 mutex_enter(&sc->sc_gpio_mtx); 1171 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1172 mutex_exit(&sc->sc_gpio_mtx); 1173 1174 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1175 } 1176 1177 static void 1178 lpcib_gpio_pin_write(void *arg, int pin, int value) 1179 { 1180 struct lpcib_softc *sc = arg; 1181 uint32_t data; 1182 int reg, shift; 1183 1184 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1185 shift = pin % 32; 1186 1187 mutex_enter(&sc->sc_gpio_mtx); 1188 1189 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1190 1191 if(value) 1192 data |= __BIT(shift); 1193 else 1194 data &= ~__BIT(shift); 1195 1196 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1197 1198 mutex_exit(&sc->sc_gpio_mtx); 1199 } 1200 1201 static void 1202 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1203 { 1204 struct lpcib_softc *sc = arg; 1205 uint32_t data; 1206 int reg, shift; 1207 1208 shift = pin % 32; 1209 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1210 1211 mutex_enter(&sc->sc_gpio_mtx); 1212 1213 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1214 1215 if (flags & GPIO_PIN_OUTPUT) 1216 data &= ~__BIT(shift); 1217 1218 if (flags & GPIO_PIN_INPUT) 1219 data |= __BIT(shift); 1220 1221 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1222 1223 1224 if (pin < 32) { 1225 reg = LPCIB_GPIO_GPO_BLINK; 1226 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1227 1228 if (flags & GPIO_PIN_PULSATE) 1229 data |= __BIT(shift); 1230 else 1231 data &= ~__BIT(shift); 1232 1233 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1234 } 1235 1236 mutex_exit(&sc->sc_gpio_mtx); 1237 } 1238 #endif 1239 1240 #if NFWHRNG > 0 1241 static void 1242 lpcib_fwh_configure(device_t self) 1243 { 1244 struct lpcib_softc *sc; 1245 pcireg_t pr; 1246 1247 sc = device_private(self); 1248 1249 if (sc->sc_has_rcba) { 1250 /* 1251 * Very unlikely to find a 82802 on a ICH6 or newer. 1252 * Also the write enable register moved at that point. 1253 */ 1254 return; 1255 } else { 1256 /* Enable FWH write to identify FWH. */ 1257 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1258 LPCIB_PCI_BIOS_CNTL); 1259 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1260 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1261 } 1262 1263 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1264 1265 /* restore previous write enable setting */ 1266 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1267 LPCIB_PCI_BIOS_CNTL, pr); 1268 } 1269 1270 static int 1271 lpcib_fwh_unconfigure(device_t self, int flags) 1272 { 1273 struct lpcib_softc *sc = device_private(self); 1274 int rc; 1275 1276 if (sc->sc_fwhbus != NULL && 1277 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1278 return rc; 1279 1280 return 0; 1281 } 1282 #endif 1283
Indexes created Tue Sep 30 11:09:46 GMT 2025