ichlpcib.c revision 1.3
1 /* $NetBSD: ichlpcib.c,v 1.3 2007/09/01 21:52:06 ober Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 41 * 42 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 43 * some power management and monitoring functions. 44 * Currently we support the watchdog timer, SpeedStep (on some systems) 45 * and the power management timer. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.3 2007/09/01 21:52:06 ober Exp $"); 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/sysctl.h> 56 #include <machine/bus.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/sysmon/sysmonvar.h> 63 64 #include <dev/ic/i82801lpcreg.h> 65 #include <dev/ic/acpipmtimer.h> 66 67 struct lpcib_softc { 68 /* Device object. */ 69 struct device sc_dev; 70 71 pci_chipset_tag_t sc_pc; 72 pcitag_t sc_pcitag; 73 74 /* Watchdog variables. */ 75 struct sysmon_wdog sc_smw; 76 bus_space_tag_t sc_iot; 77 bus_space_handle_t sc_ioh; 78 79 /* Power management */ 80 void *sc_powerhook; 81 struct pci_conf_state sc_pciconf; 82 pcireg_t sc_pirq[8]; 83 }; 84 85 static int lpcibmatch(struct device *, struct cfdata *, void *); 86 static void lpcibattach(struct device *, struct device *, void *); 87 static void lpcib_powerhook(int, void *); 88 89 static void pmtimer_configure(struct lpcib_softc *, struct pci_attach_args *); 90 91 static void tcotimer_configure(struct lpcib_softc *, struct pci_attach_args *); 92 static int tcotimer_setmode(struct sysmon_wdog *); 93 static int tcotimer_tickle(struct sysmon_wdog *); 94 static void tcotimer_stop(struct lpcib_softc *); 95 static void tcotimer_start(struct lpcib_softc *); 96 static void tcotimer_status_reset(struct lpcib_softc *); 97 static int tcotimer_disable_noreboot(struct lpcib_softc *, bus_space_tag_t, 98 bus_space_handle_t); 99 100 static void speedstep_configure(struct lpcib_softc *, struct pci_attach_args *); 101 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 102 103 struct lpcib_softc *speedstep_cookie; /* XXX */ 104 static int lpcib_ich6 = 0; 105 106 /* Defined in arch/.../pci/pcib.c. */ 107 extern void pcibattach(struct device *, struct device *, void *); 108 109 CFATTACH_DECL(ichlpcib, sizeof(struct lpcib_softc), 110 lpcibmatch, lpcibattach, NULL, NULL); 111 112 /* 113 * Autoconf callbacks. 114 */ 115 static int 116 lpcibmatch(struct device *parent, struct cfdata *match, void *aux) 117 { 118 struct pci_attach_args *pa = aux; 119 120 /* We are ISA bridge, of course */ 121 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 122 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 123 return 0; 124 125 /* Matches only Intel ICH */ 126 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 127 switch (PCI_PRODUCT(pa->pa_id)) { 128 case PCI_PRODUCT_INTEL_82801AA_LPC: /* ICH */ 129 case PCI_PRODUCT_INTEL_82801AB_LPC: /* ICH0 */ 130 case PCI_PRODUCT_INTEL_82801BA_LPC: /* ICH2 */ 131 case PCI_PRODUCT_INTEL_82801BAM_LPC: /* ICH2-M */ 132 case PCI_PRODUCT_INTEL_82801CA_LPC: /* ICH3-S */ 133 case PCI_PRODUCT_INTEL_82801CAM_LPC: /* ICH3-M */ 134 case PCI_PRODUCT_INTEL_82801DB_LPC: /* ICH4 */ 135 case PCI_PRODUCT_INTEL_82801DB_ISA: /* ICH4-M */ 136 case PCI_PRODUCT_INTEL_82801EB_LPC: /* ICH5 */ 137 return 10; 138 case PCI_PRODUCT_INTEL_82801FB_LPC: /* ICH6 */ 139 case PCI_PRODUCT_INTEL_82801FBM_LPC: /* ICH6-M */ 140 case PCI_PRODUCT_INTEL_82801G_LPC: /* ICH7 */ 141 case PCI_PRODUCT_INTEL_82801GBM_LPC: /* ICH7-M */ 142 case PCI_PRODUCT_INTEL_82801GHM_LPC: /* ICH7-M DH */ 143 case PCI_PRODUCT_INTEL_82801H_LPC: /* ICH8 */ 144 case PCI_PRODUCT_INTEL_82801HH_LPC: /* ICH8 DH */ 145 case PCI_PRODUCT_INTEL_82801HO_LPC: /* ICH8 DO */ 146 case PCI_PRODUCT_INTEL_82801HBM_LPC: /* iCH8-M */ 147 case PCI_PRODUCT_INTEL_82801IH_LPC: /* ICH9 */ 148 case PCI_PRODUCT_INTEL_82801IR_LPC: /* ICH9-R */ 149 case PCI_PRODUCT_INTEL_82801IB_LPC: /* ICH9 ? */ 150 lpcib_ich6 = 1; 151 return 10; /* prior to pcib */ 152 } 153 } 154 155 return 0; 156 } 157 158 static void 159 lpcibattach(struct device *parent, struct device *self, void *aux) 160 { 161 struct pci_attach_args *pa = aux; 162 struct lpcib_softc *sc = (void*) self; 163 164 sc->sc_pc = pa->pa_pc; 165 sc->sc_pcitag = pa->pa_tag; 166 167 pcibattach(parent, self, aux); 168 169 /* 170 * Part of our I/O registers are used as ACPI PM regs. 171 * Since our ACPI subsystem accesses the I/O space directly so far, 172 * we do not have to bother bus_space I/O map confliction. 173 */ 174 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 175 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 176 aprint_error("%s: can't map power management i/o space", 177 sc->sc_dev.dv_xname); 178 return; 179 } 180 181 /* Set up the power management timer. */ 182 pmtimer_configure(sc, pa); 183 184 /* Set up the TCO (watchdog). */ 185 tcotimer_configure(sc, pa); 186 187 /* Set up SpeedStep. */ 188 speedstep_configure(sc, pa); 189 190 /* Install powerhook */ 191 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 192 lpcib_powerhook, sc); 193 if (sc->sc_powerhook == NULL) 194 aprint_error("%s: can't establish powerhook\n", 195 sc->sc_dev.dv_xname); 196 } 197 198 static void 199 lpcib_powerhook(int why, void *opaque) 200 { 201 struct lpcib_softc *sc; 202 pci_chipset_tag_t pc; 203 pcitag_t tag; 204 205 sc = (struct lpcib_softc *)opaque; 206 pc = sc->sc_pc; 207 tag = sc->sc_pcitag; 208 209 switch (why) { 210 case PWR_SUSPEND: 211 pci_conf_capture(pc, tag, &sc->sc_pciconf); 212 213 /* capture PIRQ routing control registers */ 214 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 215 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQB_ROUT); 216 sc->sc_pirq[2] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQC_ROUT); 217 sc->sc_pirq[3] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQD_ROUT); 218 sc->sc_pirq[4] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 219 sc->sc_pirq[5] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQF_ROUT); 220 sc->sc_pirq[6] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQG_ROUT); 221 sc->sc_pirq[7] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQH_ROUT); 222 223 break; 224 225 case PWR_RESUME: 226 pci_conf_restore(pc, tag, &sc->sc_pciconf); 227 228 /* restore PIRQ routing control registers */ 229 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 230 pci_conf_write(pc, tag, LPCIB_PCI_PIRQB_ROUT, sc->sc_pirq[1]); 231 pci_conf_write(pc, tag, LPCIB_PCI_PIRQC_ROUT, sc->sc_pirq[2]); 232 pci_conf_write(pc, tag, LPCIB_PCI_PIRQD_ROUT, sc->sc_pirq[3]); 233 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[4]); 234 pci_conf_write(pc, tag, LPCIB_PCI_PIRQF_ROUT, sc->sc_pirq[5]); 235 pci_conf_write(pc, tag, LPCIB_PCI_PIRQG_ROUT, sc->sc_pirq[6]); 236 pci_conf_write(pc, tag, LPCIB_PCI_PIRQH_ROUT, sc->sc_pirq[7]); 237 238 break; 239 } 240 } 241 242 /* 243 * Initialize the power management timer. 244 */ 245 static void 246 pmtimer_configure(struct lpcib_softc *sc, struct pci_attach_args *pa) 247 { 248 pcireg_t control; 249 250 /* 251 * Check if power management I/O space is enabled and enable the ACPI_EN 252 * bit if it's disabled. 253 */ 254 control = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_PCI_ACPI_CNTL); 255 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 256 control |= LPCIB_PCI_ACPI_CNTL_EN; 257 pci_conf_write(pa->pa_pc, pa->pa_tag, LPCIB_PCI_ACPI_CNTL, 258 control); 259 } 260 261 /* Attach our PM timer with the generic acpipmtimer function */ 262 acpipmtimer_attach(&sc->sc_dev, sc->sc_iot, sc->sc_ioh, 263 LPCIB_PM1_TMR, 0); 264 } 265 266 /* 267 * Initialize the watchdog timer. 268 */ 269 static void 270 tcotimer_configure(struct lpcib_softc *sc, struct pci_attach_args *pa) 271 { 272 bus_space_handle_t gcs_memh; 273 pcireg_t pcireg; 274 uint32_t ioreg; 275 unsigned int period; 276 277 /* 278 * Map the memory space necessary for the GCS register. 279 * This is only used for ICH6 or newer, to clear the NO_REBOOT 280 * bit. 281 */ 282 if (lpcib_ich6) { 283 pcireg = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_RCBA); 284 pcireg &= 0xffffc000; 285 if (bus_space_map(pa->pa_memt, pcireg + LPCIB_GCS_OFFSET, 286 LPCIB_GCS_SIZE, 0, &gcs_memh)) { 287 aprint_error("%s: can't map GCS memory space; " 288 "TCO timer disabled\n", sc->sc_dev.dv_xname); 289 return; 290 } 291 } 292 293 /* 294 * Clear the NO_REBOOT bit. If this fails, enabling the TCO_EN bit 295 * in the SMI_EN register is the last chance. 296 */ 297 if (tcotimer_disable_noreboot(sc, pa->pa_memt, gcs_memh)) { 298 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 299 ioreg |= LPCIB_SMI_EN_TCO_EN; 300 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 301 } 302 303 /* Reset the watchdog status registers. */ 304 tcotimer_status_reset(sc); 305 306 /* Explicitly stop the TCO timer. */ 307 tcotimer_stop(sc); 308 309 /* 310 * Register the driver with the sysmon watchdog framework. 311 */ 312 sc->sc_smw.smw_name = sc->sc_dev.dv_xname; 313 sc->sc_smw.smw_cookie = sc; 314 sc->sc_smw.smw_setmode = tcotimer_setmode; 315 sc->sc_smw.smw_tickle = tcotimer_tickle; 316 if (lpcib_ich6) 317 period = LPCIB_TCOTIMER2_MAX_TICK; 318 else 319 period = LPCIB_TCOTIMER_MAX_TICK; 320 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 321 322 if (sysmon_wdog_register(&sc->sc_smw)) { 323 aprint_error("%s: unable to register TCO timer" 324 "as a sysmon watchdog device.\n", 325 sc->sc_dev.dv_xname); 326 return; 327 } 328 329 aprint_verbose("%s: TCO (watchdog) timer configured.\n", 330 sc->sc_dev.dv_xname); 331 } 332 333 /* 334 * Sysmon watchdog callbacks. 335 */ 336 static int 337 tcotimer_setmode(struct sysmon_wdog *smw) 338 { 339 struct lpcib_softc *sc = smw->smw_cookie; 340 unsigned int period; 341 uint16_t ich6period = 0; 342 343 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 344 /* Stop the TCO timer. */ 345 tcotimer_stop(sc); 346 } else { 347 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 348 /* 349 * ICH5 or older are limited to 4s min and 39s max. 350 * ICH6 or newer are limited to 2s min and 613s max. 351 */ 352 if (!lpcib_ich6) { 353 if (period < LPCIB_TCOTIMER_MIN_TICK || 354 period > LPCIB_TCOTIMER_MAX_TICK) 355 return EINVAL; 356 } else { 357 if (period < LPCIB_TCOTIMER2_MIN_TICK || 358 period > LPCIB_TCOTIMER2_MAX_TICK) 359 return EINVAL; 360 } 361 362 /* Stop the TCO timer, */ 363 tcotimer_stop(sc); 364 365 /* set the timeout, */ 366 if (lpcib_ich6) { 367 /* ICH6 or newer */ 368 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 369 LPCIB_TCO_TMR2); 370 ich6period &= 0xfc00; 371 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 372 LPCIB_TCO_TMR2, ich6period | period); 373 } else { 374 /* ICH5 or older */ 375 period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, 376 LPCIB_TCO_TMR); 377 period &= 0xc0; 378 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 379 LPCIB_TCO_TMR, period); 380 } 381 382 /* and start/reload the timer. */ 383 tcotimer_start(sc); 384 tcotimer_tickle(smw); 385 } 386 387 return 0; 388 } 389 390 static int 391 tcotimer_tickle(struct sysmon_wdog *smw) 392 { 393 struct lpcib_softc *sc = smw->smw_cookie; 394 395 /* any value is allowed */ 396 if (!lpcib_ich6) 397 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 398 else 399 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 400 401 return 0; 402 } 403 404 static void 405 tcotimer_stop(struct lpcib_softc *sc) 406 { 407 uint16_t ioreg; 408 409 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 410 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 411 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 412 } 413 414 static void 415 tcotimer_start(struct lpcib_softc *sc) 416 { 417 uint16_t ioreg; 418 419 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 420 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 421 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 422 } 423 424 static void 425 tcotimer_status_reset(struct lpcib_softc *sc) 426 { 427 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 428 LPCIB_TCO1_STS_TIMEOUT); 429 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 430 LPCIB_TCO2_STS_BOOT_STS); 431 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 432 LPCIB_TCO2_STS_SECONDS_TO_STS); 433 } 434 435 /* 436 * Clear the NO_REBOOT bit, this enables reboots. 437 */ 438 static int 439 tcotimer_disable_noreboot(struct lpcib_softc *sc, bus_space_tag_t gcs_memt, 440 bus_space_handle_t gcs_memh) 441 { 442 pcireg_t pcireg; 443 uint16_t status = 0; 444 445 if (!lpcib_ich6) { 446 pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 447 LPCIB_PCI_GEN_STA); 448 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 449 /* TCO timeout reset is disabled; try to enable it */ 450 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 451 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 452 LPCIB_PCI_GEN_STA, pcireg); 453 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 454 goto error; 455 } 456 } else { 457 status = bus_space_read_4(gcs_memt, gcs_memh, 0); 458 status &= ~LPCIB_GCS_NO_REBOOT; 459 bus_space_write_4(gcs_memt, gcs_memh, 0, status); 460 status = bus_space_read_4(gcs_memt, gcs_memh, 0); 461 bus_space_unmap(gcs_memt, gcs_memh, LPCIB_GCS_SIZE); 462 if (status & LPCIB_GCS_NO_REBOOT) 463 goto error; 464 } 465 466 return 0; 467 error: 468 aprint_error("%s: TCO timer reboot disabled by hardware; " 469 "hope SMBIOS properly handles it.\n", sc->sc_dev.dv_xname); 470 return EINVAL; 471 } 472 473 474 /* 475 * Intel ICH SpeedStep support. 476 */ 477 #define SS_READ(sc, reg) \ 478 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 479 #define SS_WRITE(sc, reg, val) \ 480 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 481 482 /* 483 * Linux driver says that SpeedStep on older chipsets cause 484 * lockups on Dell Inspiron 8000 and 8100. 485 */ 486 static int 487 speedstep_bad_hb_check(struct pci_attach_args *pa) 488 { 489 490 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 491 PCI_REVISION(pa->pa_class) < 5) 492 return 1; 493 494 return 0; 495 } 496 497 static void 498 speedstep_configure(struct lpcib_softc *sc, struct pci_attach_args *pa) 499 { 500 const struct sysctlnode *node, *ssnode; 501 int rv; 502 503 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 504 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 505 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 506 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 507 pci_find_device(pa, speedstep_bad_hb_check) == 0)) { 508 uint8_t pmcon; 509 510 /* Enable SpeedStep if it isn't already enabled. */ 511 pmcon = pci_conf_read(pa->pa_pc, pa->pa_tag, 512 LPCIB_PCI_GEN_PMCON_1); 513 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 514 pci_conf_write(pa->pa_pc, pa->pa_tag, 515 LPCIB_PCI_GEN_PMCON_1, 516 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 517 518 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 519 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 520 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 521 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 522 goto err; 523 524 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 525 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 526 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 527 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 528 CTL_EOL)) != 0) 529 goto err; 530 531 /* XXX save the sc for IO tag/handle */ 532 speedstep_cookie = sc; 533 aprint_verbose("%s: SpeedStep enabled\n", sc->sc_dev.dv_xname); 534 } 535 536 return; 537 538 err: 539 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 540 } 541 542 /* 543 * get/set the SpeedStep state: 0 == low power, 1 == high power. 544 */ 545 static int 546 speedstep_sysctl_helper(SYSCTLFN_ARGS) 547 { 548 struct sysctlnode node; 549 struct lpcib_softc *sc = speedstep_cookie; 550 uint8_t state, state2; 551 int ostate, nstate, s, error = 0; 552 553 /* 554 * We do the dance with spl's to avoid being at high ipl during 555 * sysctl_lookup() which can both copyin and copyout. 556 */ 557 s = splserial(); 558 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 559 splx(s); 560 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 561 ostate = 1; 562 else 563 ostate = 0; 564 nstate = ostate; 565 566 node = *rnode; 567 node.sysctl_data = &nstate; 568 569 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 570 if (error || newp == NULL) 571 goto out; 572 573 /* Only two states are available */ 574 if (nstate != 0 && nstate != 1) { 575 error = EINVAL; 576 goto out; 577 } 578 579 s = splserial(); 580 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 581 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 582 ostate = 1; 583 else 584 ostate = 0; 585 586 if (ostate != nstate) { 587 uint8_t cntl; 588 589 if (nstate == 0) 590 state2 |= LPCIB_PM_SS_STATE_LOW; 591 else 592 state2 &= ~LPCIB_PM_SS_STATE_LOW; 593 594 /* 595 * Must disable bus master arbitration during the change. 596 */ 597 cntl = SS_READ(sc, LPCIB_PM_CTRL); 598 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 599 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 600 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 601 } 602 splx(s); 603 out: 604 return error; 605 } 606
Indexes created Tue Sep 30 20:09:53 GMT 2025