ichlpcib.c revision 1.33.2.1
1 /* $NetBSD: ichlpcib.c,v 1.33.2.1 2012/04/17 00:07:05 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.33.2.1 2012/04/17 00:07:05 yamt Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 230 231 { 0, 0, 0, 0 }, 232 }; 233 234 /* 235 * Autoconf callbacks. 236 */ 237 static int 238 lpcibmatch(device_t parent, cfdata_t match, void *aux) 239 { 240 struct pci_attach_args *pa = aux; 241 struct lpcib_device *lpcib_dev; 242 243 /* We are ISA bridge, of course */ 244 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 245 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 246 return 0; 247 248 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 249 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 250 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 251 return 10; 252 } 253 254 return 0; 255 } 256 257 static void 258 lpcibattach(device_t parent, device_t self, void *aux) 259 { 260 struct pci_attach_args *pa = aux; 261 struct lpcib_softc *sc = device_private(self); 262 struct lpcib_device *lpcib_dev; 263 264 sc->sc_pa = *pa; 265 266 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 267 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 268 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 269 continue; 270 sc->sc_has_rcba = lpcib_dev->has_rcba; 271 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 272 break; 273 } 274 275 pcibattach(parent, self, aux); 276 277 /* 278 * Part of our I/O registers are used as ACPI PM regs. 279 * Since our ACPI subsystem accesses the I/O space directly so far, 280 * we do not have to bother bus_space I/O map confliction. 281 */ 282 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 283 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_iosize)) { 284 aprint_error_dev(self, "can't map power management i/o space"); 285 return; 286 } 287 288 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 289 LPCIB_PCI_GEN_PMCON_1); 290 291 /* For ICH6 and later, always enable RCBA */ 292 if (sc->sc_has_rcba) { 293 pcireg_t rcba; 294 295 sc->sc_rcbat = sc->sc_pa.pa_memt; 296 297 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 298 LPCIB_RCBA); 299 if ((rcba & LPCIB_RCBA_EN) == 0) { 300 aprint_error_dev(self, "RCBA is not enabled"); 301 return; 302 } 303 rcba &= ~LPCIB_RCBA_EN; 304 305 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 306 &sc->sc_rcbah)) { 307 aprint_error_dev(self, "RCBA could not be mapped"); 308 return; 309 } 310 } 311 312 /* Set up the power management timer. */ 313 pmtimer_configure(self); 314 315 /* Set up the TCO (watchdog). */ 316 tcotimer_configure(self); 317 318 /* Set up SpeedStep. */ 319 speedstep_configure(self); 320 321 /* Set up HPET. */ 322 lpcib_hpet_configure(self); 323 324 #if NGPIO > 0 325 /* Set up GPIO */ 326 lpcib_gpio_configure(self); 327 #endif 328 329 #if NFWHRNG > 0 330 lpcib_fwh_configure(self); 331 #endif 332 333 /* Install power handler */ 334 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 335 lpcib_shutdown)) 336 aprint_error_dev(self, "couldn't establish power handler\n"); 337 } 338 339 static void 340 lpcibchilddet(device_t self, device_t child) 341 { 342 struct lpcib_softc *sc = device_private(self); 343 uint32_t val; 344 345 #if NFWHRNG > 0 346 if (sc->sc_fwhbus == child) { 347 sc->sc_fwhbus = NULL; 348 return; 349 } 350 #endif 351 #if NGPIO > 0 352 if (sc->sc_gpiobus == child) { 353 sc->sc_gpiobus = NULL; 354 return; 355 } 356 #endif 357 if (sc->sc_hpetbus != child) { 358 pcibchilddet(self, child); 359 return; 360 } 361 sc->sc_hpetbus = NULL; 362 if (sc->sc_has_ich5_hpet) { 363 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 364 LPCIB_PCI_GEN_CNTL); 365 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 366 case LPCIB_ICH5_HPTC_0000: 367 case LPCIB_ICH5_HPTC_1000: 368 case LPCIB_ICH5_HPTC_2000: 369 case LPCIB_ICH5_HPTC_3000: 370 break; 371 default: 372 return; 373 } 374 val &= ~LPCIB_ICH5_HPTC_EN; 375 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 376 LPCIB_PCI_GEN_CNTL, val); 377 } else if (sc->sc_has_rcba) { 378 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 379 LPCIB_RCBA_HPTC); 380 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 381 case LPCIB_RCBA_HPTC_0000: 382 case LPCIB_RCBA_HPTC_1000: 383 case LPCIB_RCBA_HPTC_2000: 384 case LPCIB_RCBA_HPTC_3000: 385 break; 386 default: 387 return; 388 } 389 val &= ~LPCIB_RCBA_HPTC_EN; 390 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 391 val); 392 } 393 } 394 395 static int 396 lpcibrescan(device_t self, const char *ifattr, const int *locators) 397 { 398 struct lpcib_softc *sc = device_private(self); 399 400 #if NFWHRNG > 0 401 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 402 lpcib_fwh_configure(self); 403 #endif 404 405 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 406 lpcib_hpet_configure(self); 407 408 #if NGPIO > 0 409 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 410 lpcib_gpio_configure(self); 411 #endif 412 413 return pcibrescan(self, ifattr, locators); 414 } 415 416 static int 417 lpcibdetach(device_t self, int flags) 418 { 419 struct lpcib_softc *sc = device_private(self); 420 int rc; 421 422 pmf_device_deregister(self); 423 424 #if NFWHRNG > 0 425 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 426 return rc; 427 #endif 428 429 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 430 return rc; 431 432 #if NGPIO > 0 433 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 434 return rc; 435 #endif 436 437 /* Set up SpeedStep. */ 438 speedstep_unconfigure(self); 439 440 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 441 return rc; 442 443 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 444 return rc; 445 446 if (sc->sc_has_rcba) 447 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 448 449 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 450 451 return pcibdetach(self, flags); 452 } 453 454 static bool 455 lpcib_shutdown(device_t dv, int howto) 456 { 457 struct lpcib_softc *sc = device_private(dv); 458 459 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 460 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 461 462 return true; 463 } 464 465 static bool 466 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 467 { 468 struct lpcib_softc *sc = device_private(dv); 469 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 470 pcitag_t tag = sc->sc_pcib.sc_tag; 471 472 /* capture PIRQ routing control registers */ 473 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 474 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 475 476 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 477 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 478 479 if (sc->sc_has_rcba) { 480 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 481 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 482 LPCIB_RCBA_HPTC); 483 } else if (sc->sc_has_ich5_hpet) { 484 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 485 } 486 487 return true; 488 } 489 490 static bool 491 lpcib_resume(device_t dv, const pmf_qual_t *qual) 492 { 493 struct lpcib_softc *sc = device_private(dv); 494 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 495 pcitag_t tag = sc->sc_pcib.sc_tag; 496 497 /* restore PIRQ routing control registers */ 498 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 499 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 500 501 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 502 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 503 504 if (sc->sc_has_rcba) { 505 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 506 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 507 sc->sc_hpet_reg); 508 } else if (sc->sc_has_ich5_hpet) { 509 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 510 } 511 512 return true; 513 } 514 515 /* 516 * Initialize the power management timer. 517 */ 518 static void 519 pmtimer_configure(device_t self) 520 { 521 struct lpcib_softc *sc = device_private(self); 522 pcireg_t control; 523 524 /* 525 * Check if power management I/O space is enabled and enable the ACPI_EN 526 * bit if it's disabled. 527 */ 528 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 529 LPCIB_PCI_ACPI_CNTL); 530 sc->sc_acpi_cntl = control; 531 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 532 control |= LPCIB_PCI_ACPI_CNTL_EN; 533 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 534 LPCIB_PCI_ACPI_CNTL, control); 535 } 536 537 /* Attach our PM timer with the generic acpipmtimer function */ 538 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 539 LPCIB_PM1_TMR, 0); 540 } 541 542 static int 543 pmtimer_unconfigure(device_t self, int flags) 544 { 545 struct lpcib_softc *sc = device_private(self); 546 int rc; 547 548 if (sc->sc_pmtimer != NULL && 549 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 550 return rc; 551 552 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 553 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 554 555 return 0; 556 } 557 558 /* 559 * Initialize the watchdog timer. 560 */ 561 static void 562 tcotimer_configure(device_t self) 563 { 564 struct lpcib_softc *sc = device_private(self); 565 uint32_t ioreg; 566 unsigned int period; 567 568 /* Explicitly stop the TCO timer. */ 569 tcotimer_stop(sc); 570 571 /* 572 * Enable TCO timeout SMI only if the hardware reset does not 573 * work. We don't know what the SMBIOS does. 574 */ 575 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 576 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 577 578 /* 579 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 580 * in the SMI_EN register is the last chance. 581 */ 582 if (tcotimer_disable_noreboot(self)) { 583 ioreg |= LPCIB_SMI_EN_TCO_EN; 584 } 585 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 586 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 587 } 588 589 /* Reset the watchdog status registers. */ 590 tcotimer_status_reset(sc); 591 592 /* 593 * Register the driver with the sysmon watchdog framework. 594 */ 595 sc->sc_smw.smw_name = device_xname(self); 596 sc->sc_smw.smw_cookie = sc; 597 sc->sc_smw.smw_setmode = tcotimer_setmode; 598 sc->sc_smw.smw_tickle = tcotimer_tickle; 599 if (sc->sc_has_rcba) 600 period = LPCIB_TCOTIMER2_MAX_TICK; 601 else 602 period = LPCIB_TCOTIMER_MAX_TICK; 603 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 604 605 if (sysmon_wdog_register(&sc->sc_smw)) { 606 aprint_error_dev(self, "unable to register TCO timer" 607 "as a sysmon watchdog device.\n"); 608 return; 609 } 610 611 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 612 } 613 614 static int 615 tcotimer_unconfigure(device_t self, int flags) 616 { 617 struct lpcib_softc *sc = device_private(self); 618 int rc; 619 620 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 621 if (rc == ERESTART) 622 rc = EINTR; 623 return rc; 624 } 625 626 /* Explicitly stop the TCO timer. */ 627 tcotimer_stop(sc); 628 629 /* XXX Set No Reboot? */ 630 631 return 0; 632 } 633 634 635 /* 636 * Sysmon watchdog callbacks. 637 */ 638 static int 639 tcotimer_setmode(struct sysmon_wdog *smw) 640 { 641 struct lpcib_softc *sc = smw->smw_cookie; 642 unsigned int period; 643 uint16_t ich6period = 0; 644 uint8_t ich5period = 0; 645 646 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 647 /* Stop the TCO timer. */ 648 tcotimer_stop(sc); 649 } else { 650 /* 651 * ICH6 or newer are limited to 2s min and 613s max. 652 * ICH5 or older are limited to 4s min and 39s max. 653 */ 654 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 655 if (sc->sc_has_rcba) { 656 if (period < LPCIB_TCOTIMER2_MIN_TICK || 657 period > LPCIB_TCOTIMER2_MAX_TICK) 658 return EINVAL; 659 } else { 660 if (period < LPCIB_TCOTIMER_MIN_TICK || 661 period > LPCIB_TCOTIMER_MAX_TICK) 662 return EINVAL; 663 } 664 665 /* Stop the TCO timer, */ 666 tcotimer_stop(sc); 667 668 /* set the timeout, */ 669 if (sc->sc_has_rcba) { 670 /* ICH6 or newer */ 671 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 672 LPCIB_TCO_TMR2); 673 ich6period &= 0xfc00; 674 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 675 LPCIB_TCO_TMR2, ich6period | period); 676 } else { 677 /* ICH5 or older */ 678 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 679 LPCIB_TCO_TMR); 680 ich5period &= 0xc0; 681 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 682 LPCIB_TCO_TMR, ich5period | period); 683 } 684 685 /* and start/reload the timer. */ 686 tcotimer_start(sc); 687 tcotimer_tickle(smw); 688 } 689 690 return 0; 691 } 692 693 static int 694 tcotimer_tickle(struct sysmon_wdog *smw) 695 { 696 struct lpcib_softc *sc = smw->smw_cookie; 697 698 /* any value is allowed */ 699 if (sc->sc_has_rcba) 700 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 701 else 702 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 703 704 return 0; 705 } 706 707 static void 708 tcotimer_stop(struct lpcib_softc *sc) 709 { 710 uint16_t ioreg; 711 712 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 713 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 714 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 715 } 716 717 static void 718 tcotimer_start(struct lpcib_softc *sc) 719 { 720 uint16_t ioreg; 721 722 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 723 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 724 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 725 } 726 727 static void 728 tcotimer_status_reset(struct lpcib_softc *sc) 729 { 730 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 731 LPCIB_TCO1_STS_TIMEOUT); 732 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 733 LPCIB_TCO2_STS_BOOT_STS); 734 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 735 LPCIB_TCO2_STS_SECONDS_TO_STS); 736 } 737 738 /* 739 * Clear the No Reboot (NR) bit, this enables reboots when the timer 740 * reaches the timeout for the second time. 741 */ 742 static int 743 tcotimer_disable_noreboot(device_t self) 744 { 745 struct lpcib_softc *sc = device_private(self); 746 747 if (sc->sc_has_rcba) { 748 uint32_t status; 749 750 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 751 LPCIB_GCS_OFFSET); 752 status &= ~LPCIB_GCS_NO_REBOOT; 753 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 754 LPCIB_GCS_OFFSET, status); 755 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 756 LPCIB_GCS_OFFSET); 757 if (status & LPCIB_GCS_NO_REBOOT) 758 goto error; 759 } else { 760 pcireg_t pcireg; 761 762 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 763 LPCIB_PCI_GEN_STA); 764 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 765 /* TCO timeout reset is disabled; try to enable it */ 766 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 767 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 768 LPCIB_PCI_GEN_STA, pcireg); 769 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 770 goto error; 771 } 772 } 773 774 return 0; 775 error: 776 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 777 "hope SMBIOS properly handles it.\n"); 778 return EINVAL; 779 } 780 781 782 /* 783 * Intel ICH SpeedStep support. 784 */ 785 #define SS_READ(sc, reg) \ 786 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 787 #define SS_WRITE(sc, reg, val) \ 788 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 789 790 /* 791 * Linux driver says that SpeedStep on older chipsets cause 792 * lockups on Dell Inspiron 8000 and 8100. 793 * It should also not be enabled on systems with the 82855GM 794 * Hub, which typically have an EST-enabled CPU. 795 */ 796 static int 797 speedstep_bad_hb_check(const struct pci_attach_args *pa) 798 { 799 800 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 801 PCI_REVISION(pa->pa_class) < 5) 802 return 1; 803 804 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 805 return 1; 806 807 return 0; 808 } 809 810 static void 811 speedstep_configure(device_t self) 812 { 813 struct lpcib_softc *sc = device_private(self); 814 const struct sysctlnode *node, *ssnode; 815 int rv; 816 817 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 818 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 819 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 820 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 821 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 822 pcireg_t pmcon; 823 824 /* Enable SpeedStep if it isn't already enabled. */ 825 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 826 LPCIB_PCI_GEN_PMCON_1); 827 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 828 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 829 LPCIB_PCI_GEN_PMCON_1, 830 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 831 832 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 833 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 834 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 835 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 836 goto err; 837 838 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 839 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 840 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 841 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 842 CTL_EOL)) != 0) 843 goto err; 844 845 /* XXX save the sc for IO tag/handle */ 846 speedstep_cookie = sc; 847 aprint_verbose_dev(self, "SpeedStep enabled\n"); 848 } 849 850 return; 851 852 err: 853 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 854 } 855 856 static void 857 speedstep_unconfigure(device_t self) 858 { 859 struct lpcib_softc *sc = device_private(self); 860 861 sysctl_teardown(&sc->sc_log); 862 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 863 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 864 865 speedstep_cookie = NULL; 866 } 867 868 /* 869 * get/set the SpeedStep state: 0 == low power, 1 == high power. 870 */ 871 static int 872 speedstep_sysctl_helper(SYSCTLFN_ARGS) 873 { 874 struct sysctlnode node; 875 struct lpcib_softc *sc = speedstep_cookie; 876 uint8_t state, state2; 877 int ostate, nstate, s, error = 0; 878 879 /* 880 * We do the dance with spl's to avoid being at high ipl during 881 * sysctl_lookup() which can both copyin and copyout. 882 */ 883 s = splserial(); 884 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 885 splx(s); 886 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 887 ostate = 1; 888 else 889 ostate = 0; 890 nstate = ostate; 891 892 node = *rnode; 893 node.sysctl_data = &nstate; 894 895 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 896 if (error || newp == NULL) 897 goto out; 898 899 /* Only two states are available */ 900 if (nstate != 0 && nstate != 1) { 901 error = EINVAL; 902 goto out; 903 } 904 905 s = splserial(); 906 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 907 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 908 ostate = 1; 909 else 910 ostate = 0; 911 912 if (ostate != nstate) { 913 uint8_t cntl; 914 915 if (nstate == 0) 916 state2 |= LPCIB_PM_SS_STATE_LOW; 917 else 918 state2 &= ~LPCIB_PM_SS_STATE_LOW; 919 920 /* 921 * Must disable bus master arbitration during the change. 922 */ 923 cntl = SS_READ(sc, LPCIB_PM_CTRL); 924 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 925 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 926 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 927 } 928 splx(s); 929 out: 930 return error; 931 } 932 933 static void 934 lpcib_hpet_configure(device_t self) 935 { 936 struct lpcib_softc *sc = device_private(self); 937 struct lpcib_hpet_attach_args arg; 938 uint32_t hpet_reg, val; 939 940 if (sc->sc_has_ich5_hpet) { 941 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 942 LPCIB_PCI_GEN_CNTL); 943 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 944 case LPCIB_ICH5_HPTC_0000: 945 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 946 break; 947 case LPCIB_ICH5_HPTC_1000: 948 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 949 break; 950 case LPCIB_ICH5_HPTC_2000: 951 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 952 break; 953 case LPCIB_ICH5_HPTC_3000: 954 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 955 break; 956 default: 957 return; 958 } 959 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 960 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 961 LPCIB_PCI_GEN_CNTL, val); 962 } else if (sc->sc_has_rcba) { 963 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 964 LPCIB_RCBA_HPTC); 965 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 966 case LPCIB_RCBA_HPTC_0000: 967 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 968 break; 969 case LPCIB_RCBA_HPTC_1000: 970 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 971 break; 972 case LPCIB_RCBA_HPTC_2000: 973 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 974 break; 975 case LPCIB_RCBA_HPTC_3000: 976 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 977 break; 978 default: 979 return; 980 } 981 val |= LPCIB_RCBA_HPTC_EN; 982 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 983 val); 984 } else { 985 /* No HPET here */ 986 return; 987 } 988 989 arg.hpet_mem_t = sc->sc_pa.pa_memt; 990 arg.hpet_reg = hpet_reg; 991 992 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 993 } 994 995 static int 996 lpcib_hpet_unconfigure(device_t self, int flags) 997 { 998 struct lpcib_softc *sc = device_private(self); 999 int rc; 1000 1001 if (sc->sc_hpetbus != NULL && 1002 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1003 return rc; 1004 1005 return 0; 1006 } 1007 1008 #if NGPIO > 0 1009 static void 1010 lpcib_gpio_configure(device_t self) 1011 { 1012 struct lpcib_softc *sc = device_private(self); 1013 struct gpiobus_attach_args gba; 1014 pcireg_t gpio_cntl; 1015 uint32_t use, io, bit; 1016 int pin, shift, base_reg, cntl_reg, reg; 1017 1018 /* this implies ICH >= 6, and thus different mapreg */ 1019 if (sc->sc_has_rcba) { 1020 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1021 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1022 } else { 1023 base_reg = LPCIB_PCI_GPIO_BASE; 1024 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1025 } 1026 1027 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1028 cntl_reg); 1029 1030 /* Is GPIO enabled? */ 1031 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1032 return; 1033 1034 if (pci_mapreg_map(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0, 1035 &sc->sc_gpio_iot, &sc->sc_gpio_ioh, 1036 NULL, &sc->sc_gpio_ios)) { 1037 aprint_error_dev(self, "can't map general purpose i/o space\n"); 1038 return; 1039 } 1040 1041 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1042 1043 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1044 sc->sc_gpio_pins[pin].pin_num = pin; 1045 1046 /* Read initial state */ 1047 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1048 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1049 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1050 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1051 shift = pin % 32; 1052 bit = __BIT(shift); 1053 1054 if ((use & bit) != 0) { 1055 sc->sc_gpio_pins[pin].pin_caps = 1056 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1057 if (pin < 32) 1058 sc->sc_gpio_pins[pin].pin_caps |= 1059 GPIO_PIN_PULSATE; 1060 if ((io & bit) != 0) 1061 sc->sc_gpio_pins[pin].pin_flags = 1062 GPIO_PIN_INPUT; 1063 else 1064 sc->sc_gpio_pins[pin].pin_flags = 1065 GPIO_PIN_OUTPUT; 1066 } else 1067 sc->sc_gpio_pins[pin].pin_caps = 0; 1068 1069 if (lpcib_gpio_pin_read(sc, pin) == 0) 1070 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1071 else 1072 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1073 1074 } 1075 1076 /* Create controller tag */ 1077 sc->sc_gpio_gc.gp_cookie = sc; 1078 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1079 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1080 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1081 1082 memset(&gba, 0, sizeof(gba)); 1083 1084 gba.gba_gc = &sc->sc_gpio_gc; 1085 gba.gba_pins = sc->sc_gpio_pins; 1086 gba.gba_npins = LPCIB_GPIO_NPINS; 1087 1088 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1089 } 1090 1091 static int 1092 lpcib_gpio_unconfigure(device_t self, int flags) 1093 { 1094 struct lpcib_softc *sc = device_private(self); 1095 int rc; 1096 1097 if (sc->sc_gpiobus != NULL && 1098 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1099 return rc; 1100 1101 mutex_destroy(&sc->sc_gpio_mtx); 1102 1103 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1104 1105 return 0; 1106 } 1107 1108 static int 1109 lpcib_gpio_pin_read(void *arg, int pin) 1110 { 1111 struct lpcib_softc *sc = arg; 1112 uint32_t data; 1113 int reg, shift; 1114 1115 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1116 shift = pin % 32; 1117 1118 mutex_enter(&sc->sc_gpio_mtx); 1119 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1120 mutex_exit(&sc->sc_gpio_mtx); 1121 1122 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1123 } 1124 1125 static void 1126 lpcib_gpio_pin_write(void *arg, int pin, int value) 1127 { 1128 struct lpcib_softc *sc = arg; 1129 uint32_t data; 1130 int reg, shift; 1131 1132 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1133 shift = pin % 32; 1134 1135 mutex_enter(&sc->sc_gpio_mtx); 1136 1137 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1138 1139 if(value) 1140 data |= __BIT(shift); 1141 else 1142 data &= ~__BIT(shift); 1143 1144 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1145 1146 mutex_exit(&sc->sc_gpio_mtx); 1147 } 1148 1149 static void 1150 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1151 { 1152 struct lpcib_softc *sc = arg; 1153 uint32_t data; 1154 int reg, shift; 1155 1156 shift = pin % 32; 1157 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1158 1159 mutex_enter(&sc->sc_gpio_mtx); 1160 1161 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1162 1163 if (flags & GPIO_PIN_OUTPUT) 1164 data &= ~__BIT(shift); 1165 1166 if (flags & GPIO_PIN_INPUT) 1167 data |= __BIT(shift); 1168 1169 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1170 1171 1172 if (pin < 32) { 1173 reg = LPCIB_GPIO_GPO_BLINK; 1174 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1175 1176 if (flags & GPIO_PIN_PULSATE) 1177 data |= __BIT(shift); 1178 else 1179 data &= ~__BIT(shift); 1180 1181 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1182 } 1183 1184 mutex_exit(&sc->sc_gpio_mtx); 1185 } 1186 #endif 1187 1188 #if NFWHRNG > 0 1189 static void 1190 lpcib_fwh_configure(device_t self) 1191 { 1192 struct lpcib_softc *sc; 1193 pcireg_t pr; 1194 1195 sc = device_private(self); 1196 1197 if (sc->sc_has_rcba) { 1198 /* 1199 * Very unlikely to find a 82802 on a ICH6 or newer. 1200 * Also the write enable register moved at that point. 1201 */ 1202 return; 1203 } else { 1204 /* Enable FWH write to identify FWH. */ 1205 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1206 LPCIB_PCI_BIOS_CNTL); 1207 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1208 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1209 } 1210 1211 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1212 1213 /* restore previous write enable setting */ 1214 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1215 LPCIB_PCI_BIOS_CNTL, pr); 1216 } 1217 1218 static int 1219 lpcib_fwh_unconfigure(device_t self, int flags) 1220 { 1221 struct lpcib_softc *sc = device_private(self); 1222 int rc; 1223 1224 if (sc->sc_fwhbus != NULL && 1225 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1226 return rc; 1227 1228 return 0; 1229 } 1230 #endif 1231
Indexes created Wed Oct 01 15:09:59 GMT 2025